1//==- RISCVSchedSyntacoreSCR345.td - SCR3/4/5 Sched Defs -----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10 11// This file covers scheduling models for Syntacore SCR3, SCR4 and SCR5 12// processors. 13// Configurations: 14// * SCR3 rv32imc and rv64imac, overview https://syntacore.com/products/scr3 15// * SCR4 rv32imfdc and rv64imafdc, overview https://syntacore.com/products/scr4 16// * SCR5 rv32imafdc and rv64imafdc, overview 17// https://syntacore.com/products/scr5 18 19// SCR3-5 are single-issue in-order processors 20class SyntacoreSchedModel : SchedMachineModel { 21 let MicroOpBufferSize = 0; 22 let IssueWidth = 1; 23 let MispredictPenalty = 3; 24 let CompleteModel = 0; 25 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 26 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 27 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 28 HasVInstructions]; 29} 30 31// Branching 32multiclass SCR_Branching<ProcResourceKind BRU> { 33 def : WriteRes<WriteJmp, [BRU]>; 34 def : WriteRes<WriteJal, [BRU]>; 35 def : WriteRes<WriteJalr, [BRU]>; 36} 37 38// Single-cycle integer arithmetic and logic 39multiclass SCR_IntALU<ProcResourceKind ALU> { 40 def : WriteRes<WriteIALU, [ALU]>; 41 def : WriteRes<WriteIALU32, [ALU]>; 42 def : WriteRes<WriteShiftImm, [ALU]>; 43 def : WriteRes<WriteShiftImm32, [ALU]>; 44 def : WriteRes<WriteShiftReg, [ALU]>; 45 def : WriteRes<WriteShiftReg32, [ALU]>; 46} 47 48// Integer multiplication 49multiclass SCR_IntMul<ProcResourceKind MUL> { 50 let Latency = 2 in { 51 def : WriteRes<WriteIMul, [MUL]>; 52 def : WriteRes<WriteIMul32, [MUL]>; 53 } 54} 55 56// Integer division 57multiclass SCR_IntDiv<ProcResourceKind DIV, int DivLatency> { 58 let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in { 59 def : WriteRes<WriteIDiv, [DIV]>; 60 def : WriteRes<WriteIDiv32, [DIV]>; 61 def : WriteRes<WriteIRem, [DIV]>; 62 def : WriteRes<WriteIRem32, [DIV]>; 63 } 64} 65 66// Load/store instructions 67multiclass SCR_BasicMemory<ProcResourceKind LSU, int LoadStoreLatency> { 68 let Latency = LoadStoreLatency in { 69 def : WriteRes<WriteSTB, [LSU]>; 70 def : WriteRes<WriteSTH, [LSU]>; 71 def : WriteRes<WriteSTW, [LSU]>; 72 def : WriteRes<WriteSTD, [LSU]>; 73 def : WriteRes<WriteLDB, [LSU]>; 74 def : WriteRes<WriteLDH, [LSU]>; 75 def : WriteRes<WriteLDW, [LSU]>; 76 def : WriteRes<WriteLDD, [LSU]>; 77 } 78} 79 80// Floating-point load/store instructions 81multiclass SCR_FPMemory<ProcResourceKind LSU, int FPLoadStoreLatency> { 82 let Latency = FPLoadStoreLatency in { 83 def : WriteRes<WriteFST32, [LSU]>; 84 def : WriteRes<WriteFST64, [LSU]>; 85 def : WriteRes<WriteFLD32, [LSU]>; 86 def : WriteRes<WriteFLD64, [LSU]>; 87 } 88} 89 90// Atomic memory 91multiclass SCR_AtomicMemory<ProcResourceKind LSU> { 92 let Latency = 20 in { 93 def : WriteRes<WriteAtomicLDW, [LSU]>; 94 def : WriteRes<WriteAtomicLDD, [LSU]>; 95 def : WriteRes<WriteAtomicW, [LSU]>; 96 def : WriteRes<WriteAtomicD, [LSU]>; 97 def : WriteRes<WriteAtomicSTW, [LSU]>; 98 def : WriteRes<WriteAtomicSTD, [LSU]>; 99 } 100} 101 102// Floating-point unit (without division and SQRT) 103multiclass SCR_FPU<ProcResourceKind FPU> { 104 // Single and double-precision computational instructions 105 def : WriteRes<WriteFAdd32, [FPU]> { let Latency = 3; } 106 def : WriteRes<WriteFAdd64, [FPU]> { let Latency = 3; } 107 def : WriteRes<WriteFMul32, [FPU]> { let Latency = 4; } 108 def : WriteRes<WriteFMul64, [FPU]> { let Latency = 4; } 109 def : WriteRes<WriteFMA32, [FPU]> { let Latency = 4; } 110 def : WriteRes<WriteFMA64, [FPU]> { let Latency = 4; } 111 def : WriteRes<WriteFSGNJ32, [FPU]> { let Latency = 2; } 112 def : WriteRes<WriteFSGNJ64, [FPU]> { let Latency = 2; } 113 def : WriteRes<WriteFMinMax32, [FPU]> { let Latency = 2; } 114 def : WriteRes<WriteFMinMax64, [FPU]> { let Latency = 2; } 115 116 // Conversion and move instructions 117 let Latency = 3 in { 118 def : WriteRes<WriteFCvtI32ToF32, [FPU]>; 119 def : WriteRes<WriteFCvtI32ToF64, [FPU]>; 120 def : WriteRes<WriteFCvtI64ToF32, [FPU]>; 121 def : WriteRes<WriteFCvtI64ToF64, [FPU]>; 122 def : WriteRes<WriteFCvtF32ToF64, [FPU]>; 123 def : WriteRes<WriteFCvtF64ToF32, [FPU]>; 124 } 125 126 let Latency = 2 in { 127 def : WriteRes<WriteFCvtF32ToI32, [FPU]>; 128 def : WriteRes<WriteFCvtF64ToI32, [FPU]>; 129 def : WriteRes<WriteFCvtF32ToI64, [FPU]>; 130 def : WriteRes<WriteFCvtF64ToI64, [FPU]>; 131 } 132 133 let Latency = 2 in { 134 def : WriteRes<WriteFMovI32ToF32, [FPU]>; 135 def : WriteRes<WriteFMovF32ToI32, [FPU]>; 136 def : WriteRes<WriteFMovI64ToF64, [FPU]>; 137 def : WriteRes<WriteFMovF64ToI64, [FPU]>; 138 } 139 140 let Latency = 2 in { 141 def : WriteRes<WriteFClass32, [FPU]>; 142 def : WriteRes<WriteFClass64, [FPU]>; 143 } 144 145 // Comparisons 146 let Latency = 2 in { 147 def : WriteRes<WriteFCmp32, [FPU]>; 148 def : WriteRes<WriteFCmp64, [FPU]>; 149 } 150} 151 152// FP division and SQRT is not pipelined 153multiclass SCR_FDU<ProcResourceKind FDU> { 154 def : WriteRes<WriteFDiv32, [FDU]> { 155 let Latency = 10; 156 let ReleaseAtCycles = [8]; 157 } 158 def : WriteRes<WriteFDiv64, [FDU]> { 159 let Latency = 17; 160 let ReleaseAtCycles = [15]; 161 } 162 163 def : WriteRes<WriteFSqrt32, [FDU]> { 164 let Latency = 19; 165 let ReleaseAtCycles = [19]; 166 } 167 def : WriteRes<WriteFSqrt64, [FDU]> { 168 let Latency = 33; 169 let ReleaseAtCycles = [33]; 170 } 171} 172 173// Others 174multiclass SCR_Other { 175 def : WriteRes<WriteCSR, []>; 176 def : WriteRes<WriteNop, []>; 177 178 def : InstRW<[WriteIALU], (instrs COPY)>; 179} 180 181// Unsupported scheduling classes for SCR3-5. 182multiclass SCR_Unsupported : 183 UnsupportedSchedSFB, 184 UnsupportedSchedV, 185 UnsupportedSchedZabha, 186 UnsupportedSchedZba, 187 UnsupportedSchedZbb, 188 UnsupportedSchedZbc, 189 UnsupportedSchedZbs, 190 UnsupportedSchedZbkb, 191 UnsupportedSchedZbkx, 192 UnsupportedSchedZfa, 193 UnsupportedSchedZvk, 194 UnsupportedSchedXsf; 195 196multiclass SCR3_Unsupported : 197 SCR_Unsupported, 198 UnsupportedSchedF; 199 200multiclass SCR4_SCR5_Unsupported : 201 SCR_Unsupported, 202 UnsupportedSchedQ, 203 UnsupportedSchedZfhmin; 204 205// Bypasses (none) 206multiclass SCR_NoReadAdvances { 207 def : ReadAdvance<ReadJmp, 0>; 208 def : ReadAdvance<ReadJalr, 0>; 209 def : ReadAdvance<ReadCSR, 0>; 210 def : ReadAdvance<ReadStoreData, 0>; 211 def : ReadAdvance<ReadMemBase, 0>; 212 def : ReadAdvance<ReadIALU, 0>; 213 def : ReadAdvance<ReadIALU32, 0>; 214 def : ReadAdvance<ReadShiftImm, 0>; 215 def : ReadAdvance<ReadShiftImm32, 0>; 216 def : ReadAdvance<ReadShiftReg, 0>; 217 def : ReadAdvance<ReadShiftReg32, 0>; 218 def : ReadAdvance<ReadIDiv, 0>; 219 def : ReadAdvance<ReadIDiv32, 0>; 220 def : ReadAdvance<ReadIRem, 0>; 221 def : ReadAdvance<ReadIRem32, 0>; 222 def : ReadAdvance<ReadIMul, 0>; 223 def : ReadAdvance<ReadIMul32, 0>; 224 def : ReadAdvance<ReadAtomicWA, 0>; 225 def : ReadAdvance<ReadAtomicWD, 0>; 226 def : ReadAdvance<ReadAtomicDA, 0>; 227 def : ReadAdvance<ReadAtomicDD, 0>; 228 def : ReadAdvance<ReadAtomicLDW, 0>; 229 def : ReadAdvance<ReadAtomicLDD, 0>; 230 def : ReadAdvance<ReadAtomicSTW, 0>; 231 def : ReadAdvance<ReadAtomicSTD, 0>; 232} 233 234// Floating-point bypasses (none) 235multiclass SCR4_SCR5_NoReadAdvances : SCR_NoReadAdvances { 236 def : ReadAdvance<ReadFStoreData, 0>; 237 def : ReadAdvance<ReadFMemBase, 0>; 238 def : ReadAdvance<ReadFAdd32, 0>; 239 def : ReadAdvance<ReadFAdd64, 0>; 240 def : ReadAdvance<ReadFMul32, 0>; 241 def : ReadAdvance<ReadFMul64, 0>; 242 def : ReadAdvance<ReadFMA32, 0>; 243 def : ReadAdvance<ReadFMA32Addend, 0>; 244 def : ReadAdvance<ReadFMA64, 0>; 245 def : ReadAdvance<ReadFMA64Addend, 0>; 246 def : ReadAdvance<ReadFDiv32, 0>; 247 def : ReadAdvance<ReadFDiv64, 0>; 248 def : ReadAdvance<ReadFSqrt32, 0>; 249 def : ReadAdvance<ReadFSqrt64, 0>; 250 def : ReadAdvance<ReadFCmp32, 0>; 251 def : ReadAdvance<ReadFCmp64, 0>; 252 def : ReadAdvance<ReadFSGNJ32, 0>; 253 def : ReadAdvance<ReadFSGNJ64, 0>; 254 def : ReadAdvance<ReadFMinMax32, 0>; 255 def : ReadAdvance<ReadFMinMax64, 0>; 256 def : ReadAdvance<ReadFCvtF32ToI32, 0>; 257 def : ReadAdvance<ReadFCvtF32ToI64, 0>; 258 def : ReadAdvance<ReadFCvtF64ToI32, 0>; 259 def : ReadAdvance<ReadFCvtF64ToI64, 0>; 260 def : ReadAdvance<ReadFCvtI32ToF32, 0>; 261 def : ReadAdvance<ReadFCvtI32ToF64, 0>; 262 def : ReadAdvance<ReadFCvtI64ToF32, 0>; 263 def : ReadAdvance<ReadFCvtI64ToF64, 0>; 264 def : ReadAdvance<ReadFCvtF32ToF64, 0>; 265 def : ReadAdvance<ReadFCvtF64ToF32, 0>; 266 def : ReadAdvance<ReadFMovF32ToI32, 0>; 267 def : ReadAdvance<ReadFMovI32ToF32, 0>; 268 def : ReadAdvance<ReadFMovF64ToI64, 0>; 269 def : ReadAdvance<ReadFMovI64ToF64, 0>; 270 def : ReadAdvance<ReadFClass32, 0>; 271 def : ReadAdvance<ReadFClass64, 0>; 272} 273 274//===----------------------------------------------------------------------===// 275// SCR3 scheduling model definition 276 277def SyntacoreSCR3RV32Model : SyntacoreSchedModel { 278 let LoadLatency = 2; 279} 280 281let SchedModel = SyntacoreSCR3RV32Model in { 282 let BufferSize = 0 in { 283 def SCR3RV32_ALU : ProcResource<1>; 284 def SCR3RV32_MUL : ProcResource<1>; 285 def SCR3RV32_DIV : ProcResource<1>; 286 def SCR3RV32_LSU : ProcResource<1>; 287 def SCR3RV32_CFU : ProcResource<1>; 288 } 289 290 defm : SCR_Branching<SCR3RV32_CFU>; 291 defm : SCR_IntALU<SCR3RV32_ALU>; 292 defm : SCR_IntMul<SCR3RV32_MUL>; 293 defm : SCR_IntDiv<SCR3RV32_DIV, /* div latency = */ 8>; 294 defm : SCR_BasicMemory<SCR3RV32_LSU, /* load & store latency = */ 2>; 295 defm : SCR_AtomicMemory<SCR3RV32_LSU>; 296 defm : SCR_Other; 297 298 defm : SCR3_Unsupported; 299 defm : SCR_NoReadAdvances; 300} 301 302def SyntacoreSCR3RV64Model : SyntacoreSchedModel { 303 let LoadLatency = 2; 304} 305 306let SchedModel = SyntacoreSCR3RV64Model in { 307 let BufferSize = 0 in { 308 def SCR3RV64_ALU : ProcResource<1>; 309 def SCR3RV64_MUL : ProcResource<1>; 310 def SCR3RV64_DIV : ProcResource<1>; 311 def SCR3RV64_LSU : ProcResource<1>; 312 def SCR3RV64_CFU : ProcResource<1>; 313 } 314 315 defm : SCR_Branching<SCR3RV64_CFU>; 316 defm : SCR_IntALU<SCR3RV64_ALU>; 317 defm : SCR_IntMul<SCR3RV64_MUL>; 318 defm : SCR_IntDiv<SCR3RV64_DIV, /* div latency = */ 11>; 319 defm : SCR_BasicMemory<SCR3RV64_LSU, /* load & store latency = */ 2>; 320 defm : SCR_AtomicMemory<SCR3RV64_LSU>; 321 defm : SCR_Other; 322 323 defm : SCR3_Unsupported; 324 defm : SCR_NoReadAdvances; 325} 326 327//===----------------------------------------------------------------------===// 328// SCR4 scheduling model definition 329 330def SyntacoreSCR4RV32Model : SyntacoreSchedModel { 331 let LoadLatency = 2; 332} 333 334let SchedModel = SyntacoreSCR4RV32Model in { 335 let BufferSize = 0 in { 336 def SCR4RV32_ALU : ProcResource<1>; 337 def SCR4RV32_MUL : ProcResource<1>; 338 def SCR4RV32_DIV : ProcResource<1>; 339 def SCR4RV32_LSU : ProcResource<1>; 340 def SCR4RV32_CFU : ProcResource<1>; 341 def SCR4RV32_FPU : ProcResource<1>; 342 def SCR4RV32_FDU : ProcResource<1>; // FP div and sqrt resource 343 } 344 345 defm : SCR_Branching<SCR4RV32_CFU>; 346 defm : SCR_IntALU<SCR4RV32_ALU>; 347 defm : SCR_IntMul<SCR4RV32_MUL>; 348 defm : SCR_IntDiv<SCR4RV32_DIV, /* div latency = */ 8>; 349 defm : SCR_BasicMemory<SCR4RV32_LSU, /* load & store latency = */ 2>; 350 defm : SCR_FPMemory<SCR4RV32_LSU, /* load & store latency = */ 2>; 351 defm : SCR_AtomicMemory<SCR4RV32_LSU>; 352 defm : SCR_FPU<SCR4RV32_FPU>; 353 defm : SCR_FDU<SCR4RV32_FDU>; 354 defm : SCR_Other; 355 356 defm : SCR4_SCR5_Unsupported; 357 defm : SCR4_SCR5_NoReadAdvances; 358} 359 360def SyntacoreSCR4RV64Model : SyntacoreSchedModel { 361 let LoadLatency = 2; 362} 363 364let SchedModel = SyntacoreSCR4RV64Model in { 365 let BufferSize = 0 in { 366 def SCR4RV64_ALU : ProcResource<1>; 367 def SCR4RV64_MUL : ProcResource<1>; 368 def SCR4RV64_DIV : ProcResource<1>; 369 def SCR4RV64_LSU : ProcResource<1>; 370 def SCR4RV64_CFU : ProcResource<1>; 371 def SCR4RV64_FPU : ProcResource<1>; 372 def SCR4RV64_FDU : ProcResource<1>; // FP div and sqrt resource 373 } 374 375 defm : SCR_Branching<SCR4RV64_CFU>; 376 defm : SCR_IntALU<SCR4RV64_ALU>; 377 defm : SCR_IntMul<SCR4RV64_MUL>; 378 defm : SCR_IntDiv<SCR4RV64_DIV, /* div latency = */ 11>; 379 defm : SCR_BasicMemory<SCR4RV64_LSU, /* load & store latency = */ 2>; 380 defm : SCR_FPMemory<SCR4RV64_LSU, /* load & store latency = */ 2>; 381 defm : SCR_AtomicMemory<SCR4RV64_LSU>; 382 defm : SCR_FPU<SCR4RV64_FPU>; 383 defm : SCR_FDU<SCR4RV64_FDU>; 384 defm : SCR_Other; 385 386 defm : SCR4_SCR5_Unsupported; 387 defm : SCR4_SCR5_NoReadAdvances; 388} 389 390//===----------------------------------------------------------------------===// 391// SCR5 scheduling model definition 392 393def SyntacoreSCR5RV32Model : SyntacoreSchedModel { 394 let LoadLatency = 3; 395} 396 397let SchedModel = SyntacoreSCR5RV32Model in { 398 let BufferSize = 0 in { 399 def SCR5RV32_ALU : ProcResource<1>; 400 def SCR5RV32_MUL : ProcResource<1>; 401 def SCR5RV32_DIV : ProcResource<1>; 402 def SCR5RV32_LSU : ProcResource<1>; 403 def SCR5RV32_CFU : ProcResource<1>; 404 def SCR5RV32_FPU : ProcResource<1>; 405 def SCR5RV32_FDU : ProcResource<1>; // FP div and sqrt resource 406 } 407 408 defm : SCR_Branching<SCR5RV32_CFU>; 409 defm : SCR_IntALU<SCR5RV32_ALU>; 410 defm : SCR_IntMul<SCR5RV32_MUL>; 411 defm : SCR_IntDiv<SCR5RV32_DIV, /* div latency = */ 8>; 412 defm : SCR_BasicMemory<SCR5RV32_LSU, /* load & store latency = */ 3>; 413 defm : SCR_FPMemory<SCR5RV32_LSU, /* load & store latency = */ 3>; 414 defm : SCR_AtomicMemory<SCR5RV32_LSU>; 415 defm : SCR_FPU<SCR5RV32_FPU>; 416 defm : SCR_FDU<SCR5RV32_FDU>; 417 defm : SCR_Other; 418 419 defm : SCR4_SCR5_Unsupported; 420 defm : SCR4_SCR5_NoReadAdvances; 421} 422 423def SyntacoreSCR5RV64Model : SyntacoreSchedModel { 424 let LoadLatency = 3; 425} 426 427let SchedModel = SyntacoreSCR5RV64Model in { 428 let BufferSize = 0 in { 429 def SCR5RV64_ALU : ProcResource<1>; 430 def SCR5RV64_MUL : ProcResource<1>; 431 def SCR5RV64_DIV : ProcResource<1>; 432 def SCR5RV64_LSU : ProcResource<1>; 433 def SCR5RV64_CFU : ProcResource<1>; 434 def SCR5RV64_FPU : ProcResource<1>; 435 def SCR5RV64_FDU : ProcResource<1>; // FP div and sqrt resource 436 } 437 438 defm : SCR_Branching<SCR5RV64_CFU>; 439 defm : SCR_IntALU<SCR5RV64_ALU>; 440 defm : SCR_IntMul<SCR5RV64_MUL>; 441 defm : SCR_IntDiv<SCR5RV64_DIV, /* div latency = */ 11>; 442 defm : SCR_BasicMemory<SCR5RV64_LSU, /* load & store latency = */ 3>; 443 defm : SCR_FPMemory<SCR5RV64_LSU, /* load & store latency = */ 3>; 444 defm : SCR_AtomicMemory<SCR5RV64_LSU>; 445 defm : SCR_FPU<SCR5RV64_FPU>; 446 defm : SCR_FDU<SCR5RV64_FDU>; 447 defm : SCR_Other; 448 449 defm : SCR4_SCR5_Unsupported; 450 defm : SCR4_SCR5_NoReadAdvances; 451} 452