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Searched refs:TRM (Results 1 – 25 of 49) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.txt37 TRM to determine which are valid for each pin or group.
48 or "LPMD1" and "LPMD0" in the Tegra TRM.
51 Tegra TRM.
54 Tegra TRM.
57 "DRVDN_SLWR" in the Tegra TRM.
60 "DRVUP_SLWF" in the Tegra TRM.
63 or groups. See the Tegra TRM and various pinmux spreadsheets for complete
H A Dnvidia,tegra210-pinmux.txt31 See the TRM to determine which properties and values apply to each pin/group.
68 Tegra TRM.
71 Tegra TRM.
74 "DRVDN_SLWR" in the Tegra TRM.
77 "DRVUP_SLWF" in the Tegra TRM.
H A Dnvidia,tegra194-pinmux.txt19 See the TRM to determine which properties and values apply to each pin/group.
53 Tegra TRM.
56 Tegra TRM.
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-dfll.txt40 - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41 - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42 - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43 - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44 - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
47 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
H A Dzynq-7000.txt7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dti-sysc.txt60 Manual (TRM) for the interconnect target module
63 target module as documented in the TRM for SYSCONFIG
67 target module as documented in the TRM for SYSCONFIG
74 TRM for SYSSTATUS registers, typically 1 with some devices
87 optional clocks that can be specified as listed in TRM
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-gta04a5one.dts21 /* data lines, gpmc_d0..d7 not muxable according to TRM */
33 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
H A Dam3517.dtsi34 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
182 /* Table Table 5-79 of the TRM shows 480ab000 is reserved */
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4-j742s2-common.dtsi5 * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
6 * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
71 /* Recommendation from GIC500 TRM Table A.3 */
H A Dk3-am62d2.dtsi5 * TRM: https://www.ti.com/lit/pdf/sprujd4
H A Dk3-j742s2-main.dtsi5 * TRM: https://www.ti.com/lit/pdf/spruje3
H A Dk3-j721s2.dtsi5 * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
110 /* Recommendation from GIC500 TRM Table A.3 */
H A Dk3-j742s2.dtsi5 * TRM: https://www.ti.com/lit/pdf/spruje3
H A Dk3-am62a7.dtsi5 * TRM: https://www.ti.com/lit/zip/spruj16
H A Dk3-am625.dtsi5 * TRM: https://www.ti.com/lit/pdf/spruiv7
H A Dk3-am62p5.dtsi6 * TRM: https://www.ti.com/lit/pdf/spruj83
/freebsd/contrib/tcsh/
H A Dsh.dir.h50 #define TRM(a) ((a) & TRIM) macro
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dvexpress-sysreg.txt62 numbers - see motherboard's TRM for more details. All configuration
68 - compatible value : must be one of (corresponding to the TRM):
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt59 interconnect entry. Consult TRM documentation for information about
144 interconnect entry. Consult TRM documentation for information about
165 interconnect entry. Consult TRM documentation for information about
186 interconnect entry. Consult TRM documentation for information about
207 interconnect entry. Consult TRM documentation for information about
235 interconnect entry. Consult TRM documentation for information about
269 interconnect entry. Consult TRM documentation for information about
430 interconnect entry. Consult TRM documentation for information about
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dnvidia,tegra20-apbdma.txt16 select value for the peripheral. For more details, consult the Tegra TRM's
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dxlnx,zynqmp-reset.txt6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
H A Dzynq-reset.txt5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dtwl4030-audio.txt19 -ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-mc.txt14 or in the TRM documentation.
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra30-actmon.txt25 interconnect entry. Consult TRM documentation for

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