xref: /freebsd/sys/contrib/device-tree/src/arm64/ti/k3-j742s2.dtsi (revision 5f62a964e9f8abc6a05d8338273fadd154f0a206)

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J742S2 SoC Family
 *
 * TRM: https://www.ti.com/lit/pdf/spruje3
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 */
#include "k3-j784s4-j742s2-common.dtsi"

/ {
	model = "Texas Instruments K3 J742S2 SoC";
	compatible = "ti,j742s2";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a72";
			reg = <0x002>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a72";
			reg = <0x003>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};
	};
};

#include "k3-j742s2-main.dtsi"