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Searched refs:SETCC (Results 1 – 25 of 62) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp84 case ISD::SETCC: in hasNativeBF16Support()
H A DNVPTXISelLowering.cpp605 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
606 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
614 setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
615 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
616 if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote) in NVPTXTargetLowering()
617 AddPromotedToType(ISD::SETCC, MVT::bf16, MVT::f32); in NVPTXTargetLowering()
646 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
814 ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::SETCC}, in NVPTXTargetLowering()
849 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
5808 case ISD::SETCC: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3405 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } }, in getCmpSelInstrCost()
3416 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3417 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3418 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3419 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3426 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3427 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3428 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3429 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3431 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
[all …]
H A DX86ISelLowering.cpp494 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
502 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
634 setOperationAction(ISD::SETCC, VT, Action); in X86TargetLowering()
940 setOperationAction(ISD::SETCC, MVT::f128, Custom); in X86TargetLowering()
1017 setOperationAction(ISD::SETCC, VT, Expand); in X86TargetLowering()
1171 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
1183 setOperationAction(ISD::SETCC, MVT::v2f64, Custom); in X86TargetLowering()
1184 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); in X86TargetLowering()
1555 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
1566 setOperationAction(ISD::SETCC, MVT::v4f64, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.h185 static inline bool IsSETCC(unsigned SETCC) { in IsSETCC() argument
186 switch (SETCC) { in IsSETCC()
H A DM68kISelLowering.cpp131 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
1391 case ISD::SETCC: in LowerOperation()
1646 Overflow = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
1672 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
1862 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
2174 if (Op0.getOpcode() == M68kISD::SETCC) { in LowerSETCC()
2182 DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2206 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2230 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCCCARRY()
2270 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
[all …]
H A DM68kInstrInfo.td161 def MxSetCC : SDNode<"M68kISD::SETCC", MxSDT_SetCC>;
163 // Same as SETCC except it's materialized with a subx and the value is all
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def119 ADD_VVP_OP(VVP_SETCC, SETCC)
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def65 // Both of these match to FCmp / SETCC.
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h801 SETCC, enumerator
H A DSDPatternMatch.h539 return TernaryOpc_match<T0_P, T1_P, T2_P>(ISD::SETCC, LHS, RHS, CC);
545 return TernaryOpc_match<T0_P, T1_P, T2_P, true, false>(ISD::SETCC, LHS, RHS,
681 if (sd_context_match(Cond, Ctx, m_Opc(ISD::SETCC))) {
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp74 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
591 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
697 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_SETCC()
789 case ISD::SETCC: in ScalarizeVectorOperand()
975 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecOp_VSETCC()
1168 case ISD::SETCC: in SplitVectorResult()
2173 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_LOAD()
2249 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_STRIDED_LOAD()
2329 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MLOAD()
2420 if (SplitSETCC && Ops.Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_Gather()
[all …]
H A DLegalizeVectorOps.cpp523 case ISD::SETCC: { in LegalizeOp()
728 case ISD::SETCC: in Promote()
1005 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
1041 case ISD::SETCC: in Expand()
2071 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
2354 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
H A DDAGCombiner.cpp989 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1294 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC && in reassociateOpsCommutative()
1295 N01->getOpcode() == ISD::SETCC) { in reassociateOpsCommutative()
1963 case ISD::SETCC: return visitSETCC(N); in visit()
5953 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
6456 TLI.isOperationLegal(ISD::SETCC, OpVT)))) in foldLogicOfSetCCs()
6539 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || in foldAndOrOfSETCC()
6672 return DAG.getNode(ISD::SETCC, DL, VT, AbsOp, in foldAndOrOfSETCC()
6702 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
6710 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp86 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
183 case ISD::SETCC: in LowerOperation()
968 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue); in LowerSETCC()
1449 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp171 setOperationAction(ISD::SETCC, P, Custom); in initializeHVXLowering()
311 setOperationAction(ISD::SETCC, T, Custom); in initializeHVXLowering()
386 setOperationAction(ISD::SETCC, BoolW, Custom); in initializeHVXLowering()
430 setOperationAction(ISD::SETCC, VecTy, Custom); in initializeHVXLowering()
444 setOperationAction(ISD::SETCC, BoolTy, Custom); in initializeHVXLowering()
3166 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC()
3222 case ISD::SETCC: in LowerHvxOperation()
3263 case ISD::SETCC: in LowerHvxOperation()
3413 case ISD::SETCC: in LowerHvxOperationWrapper()
3479 case ISD::SETCC: in ReplaceHvxNodeResults()
H A DHexagonISelLowering.cpp1603 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1604 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1605 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1606 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1850 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
3417 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp141 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
163 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
283 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
287 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
292 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
330 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
398 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
435 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
1089 case ISD::SETCC: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp91 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
92 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
227 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp112 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
113 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
114 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
940 case ISD::SETCC: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp96 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
113 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
749 ISD::SETCC, in lowerFP_TO_UINT()
759 ISD::SETCC, in lowerFP_TO_SINT()
H A DAMDGPUISelLowering.h442 SETCC, enumerator
H A DSIISelLowering.cpp224 ISD::SETCC}) { in SITargetLowering()
282 setOperationAction(ISD::SETCC, MVT::i1, Promote); in SITargetLowering()
283 setOperationAction(ISD::SETCC, {MVT::v2i1, MVT::v4i1}, Expand); in SITargetLowering()
284 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in SITargetLowering()
970 ISD::SETCC, in SITargetLowering()
2069 if (VT == MVT::i1 && Op == ISD::SETCC) in isTypeDesirableForOp()
6384 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic()
6413 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, Src1, in lowerFCMPIntrinsic()
6426 if (Src.getOpcode() == ISD::SETCC) { in lowerBALLOTIntrinsic()
6428 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0), in lowerBALLOTIntrinsic()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp291 setOperationAction(ISD::SETCC, VT, Legal); in LoongArchTargetLowering()
359 setOperationAction(ISD::SETCC, VT, Legal); in LoongArchTargetLowering()
406 setTargetDAGCombine(ISD::SETCC); in LoongArchTargetLowering()
545 assert(Val->getOpcode() == ISD::SETCC); in matchSetCC()
610 if (CondV.getOpcode() == ISD::SETCC && TrueV.getOpcode() == ISD::SETCC && in combineSelectToBinOp()
611 FalseV.getOpcode() == ISD::SETCC) { in combineSelectToBinOp()
794 if (CondV.getOpcode() != ISD::SETCC || in lowerSELECT()
4521 case ISD::SETCC: in checkBitcastSrcVectorSize()
4547 case ISD::SETCC: in signExtendBitcastSrcVector()
4578 if (Src.getOpcode() != ISD::SETCC || !Src.hasOneUse()) in performSETCC_BITCASTCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp487 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
488 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
489 setOperationAction(ISD::SETCC, MVT::bf16, Custom); in AArch64TargetLowering()
490 setOperationAction(ISD::SETCC, MVT::f16, Custom); in AArch64TargetLowering()
491 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
492 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
566 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
788 ISD::SETCC, in AArch64TargetLowering()
855 setOperationPromotedToType(ISD::SETCC, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
868 setOperationPromotedToType(ISD::SETCC, V8Narrow, MVT::v8f32); in AArch64TargetLowering()
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