Searched full:v2_1 (Results 1 – 12 of 12) sorted by relevance
522 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1; member544 args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ in amdgpu_atombios_crtc_set_dce_clock()545 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()546 args.v2_1.asParam.ucDCEClkSrc = clk_src; in amdgpu_atombios_crtc_set_dce_clock()548 ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; in amdgpu_atombios_crtc_set_dce_clock()
1637 struct gc_info_v2_1 v2_1; member1725 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); in amdgpu_discovery_get_gfx_info()1726 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); in amdgpu_discovery_get_gfx_info()1727 …adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XC… in amdgpu_discovery_get_gfx_info()1728 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); in amdgpu_discovery_get_gfx_info()1729 …adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_c… in amdgpu_discovery_get_gfx_info()1730 …adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_si… in amdgpu_discovery_get_gfx_info()1731 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ in amdgpu_discovery_get_gfx_info()
1440 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member1474 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in amdgpu_atombios_init_mc_reg_table()1477 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in amdgpu_atombios_init_mc_reg_table()
118 /* EEPROM Table V2_1 */1496 * EEPROM table V2_1 supports ras info, in __read_table_ras_info()
281 const struct smc_firmware_header_v2_1 *v2_1; in smu_v15_0_set_pptable_v2_1() local286 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v15_0_set_pptable_v2_1()288 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v15_0_set_pptable_v2_1()289 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v15_0_set_pptable_v2_1()292 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v15_0_set_pptable_v2_1()
312 const struct smc_firmware_header_v2_1 *v2_1; in smu_v14_0_set_pptable_v2_1() local317 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v14_0_set_pptable_v2_1()319 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v14_0_set_pptable_v2_1()320 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v14_0_set_pptable_v2_1()323 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v14_0_set_pptable_v2_1()
290 const struct smc_firmware_header_v2_1 *v2_1; in smu_v11_0_set_pptable_v2_1() local295 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v11_0_set_pptable_v2_1()297 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v11_0_set_pptable_v2_1()298 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v11_0_set_pptable_v2_1()301 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v11_0_set_pptable_v2_1()
322 const struct smc_firmware_header_v2_1 *v2_1; in smu_v13_0_set_pptable_v2_1() local327 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v13_0_set_pptable_v2_1()329 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v13_0_set_pptable_v2_1()330 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v13_0_set_pptable_v2_1()333 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v13_0_set_pptable_v2_1()
491 const struct smc_firmware_header_v2_1 *v2_1; in smu_v13_0_6_init_microcode() local525 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data; in smu_v13_0_6_init_microcode()527 *)((uint8_t *)v2_1 + in smu_v13_0_6_init_microcode()528 le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v13_0_6_init_microcode()529 p2stable_count = le32_to_cpu(v2_1->pptable_count); in smu_v13_0_6_init_microcode()533 ((uint8_t *)v2_1 + in smu_v13_0_6_init_microcode()
345 /* new for v2_1 */
3808 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member3871 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_get_memory_info()3873 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; in radeon_atom_get_memory_info()3996 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_init_mc_reg_table()3999 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in radeon_atom_init_mc_reg_table()
1448 /* TODO: previous vv1_3, should v2_1 */ in get_embedded_panel_info_v2_1()