| /linux/include/linux/ |
| H A D | hp_sdc.h | 2 * HP i8042 System Device Controller -- header
7 * Redistribution and use in source and binary forms, with or without
10 * 1. Redistributions of source code must retain the above copyright
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
79 * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
[all …]
|
| H A D | crash_dump.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define ELFCORE_ADDR_MAX (-1ULL)
13 #define ELFCORE_ADDR_ERR (-2ULL)
34 /* Architecture code defines this if there are other possible ELF
35 * machine types, e.g. on bi-arch capable hardware. */
41 * Architecture code can redefine this if there are any special checks
42 * needed for 32-bit ELF or 64-bit ELF vmcores. In case of 32-bit
73 * This makes use of the fact that due to alignment -2ULL is not
94 * struct vmcore_cb - driver callbacks for /proc/vmcore handling
95 * @pfn_is_ram: check whether a PFN really is RAM and should be accessed when
[all …]
|
| /linux/Documentation/arch/arm/ |
| H A D | tcm.rst | 2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
47 be able to lock and hide one of the banks for use by the secure
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
[all …]
|
| H A D | porting.rst | 5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
[all …]
|
| H A D | memory.rst | 11 free for platforms to use, and which are used by generic code.
18 certain regions of VM space for use for new facilities; therefore
22 Start End Use
24 ffff8000 ffffffff copy_user_page / clear_user_page use.
31 Platforms must not use this address range.
39 in proc-xscale.S to flush the whole data
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
68 PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region.
69 This maps the platforms RAM, and typically
[all …]
|
| /linux/drivers/net/ethernet/amd/ |
| H A D | mvme147.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Uses the generic 7990.c LANCE code.
30 /* We have 32K of RAM for the init block and buffers. This places
31 * an upper limit on the number of buffers we can use. NetBSD uses 8 Rx
37 #include "7990.h" /* use generic LANCE code */
42 unsigned long ram; member
47 * plus board-specific init, open and close actions.
48 * Oh, and we need to tell the generic code how to read and write LANCE registers...
70 /* Initialise the one and only on-board 7990 */
83 return ERR_PTR(-ENODEV); in mvme147lance_probe()
[all …]
|
| /linux/kernel/power/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Suspend to RAM and standby"
9 suspend-to-RAM state (e.g. the ACPI S3 state).
12 bool "Enable freezer for suspend to RAM/standby" \
18 done, no tasks are frozen for suspend to RAM/standby.
23 bool "Skip kernel's sys_sync() on suspend to RAM/standby"
30 user-space before invoking suspend. There's a run-time switch
32 This setting changes the default for the run-tim switch. Say Y
54 Alternatively, you can use the additional userland tools available
59 of the reasons to use software suspend is that the firmware hooks
[all …]
|
| /linux/arch/riscv/include/asm/ |
| H A D | xip_fixup.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Fix-up address in Flash into address in RAM early during boot before
13 * MMU is up. Because generated code "thinks" data is in Flash, but it
14 * is actually in RAM (actually data is also in Flash, but Flash is
15 * read-only, thus we need to use the data residing in RAM).
17 * The start of data in Flash is _sdata and the start of data in RAM is
18 * CONFIG_PHYS_RAM_BASE. So this fix-up essentially does this:
19 * reg += CONFIG_PHYS_RAM_BASE - _start
27 /* In linker script, at the transition from read-only section to
32 * Consequently, early during boot before MMU is up, the generated code
[all …]
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
[all …]
|
| /linux/arch/arm/kernel/ |
| H A D | reboot.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
26 * A temporary stack to use for CPU reset. This is static so that we
30 * code.
88 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
89 * kexec'd kernel to use any and all RAM as it sees fit, without having to
90 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
111 * Power-off simply requires that the secondary CPUs stop performing any
126 * use soft_restart() as their machine descriptor's .restart hook, since that
129 * This is required so that any code running after reset on the primary CPU
[all …]
|
| /linux/Documentation/scsi/ |
| H A D | ChangeLog.ncr53c8xx | 1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version ncr53c8xx-3.4.3b
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
7 Mon Feb 12 22:30 2001 Gerard Roudier (groudier@club-internet.fr)
8 * version ncr53c8xx-3.4.3
9 - Call pci_enable_device() as AC wants this to be done.
10 - Get both the BAR cookies actual and PCI BAR values.
12 - Merge changes for linux-2.4 that declare the host template
[all …]
|
| /linux/Documentation/admin-guide/ |
| H A D | ramoops.rst | 9 ------------
11 Ramoops is an oops/panic logger that writes its logs to RAM before the system
13 needs a system with persistent RAM so that the content of that area can
17 ----------------
30 mapping to pgprot_writecombine. Setting ``mem_type=1`` attempts to use
56 to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat
60 ----------------------
64 A. Use the module parameters (which have the names of the variables described
66 boot and then use the reserved memory for ramoops. For example, assuming a
68 the kernel to use only the first 128 MB of memory, and place ECC-protected
[all …]
|
| /linux/arch/x86/kernel/ |
| H A D | ebda.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * are code), that must not be used by the kernel as available
13 * RAM.
20 * guess the reserved BIOS area by looking at the low BIOS RAM size
26 * - This code also contains a quirk for Dell systems that neglect
27 * to reserve the EBDA area in the 'RAM size' value ...
29 * - The same quirk also avoids a problem with the AMD768MPX
34 * - Plus paravirt systems don't have a reliable value in the
35 * 'BIOS RAM size' pointer we can rely on, so we must quirk
46 * Using memory that is in use by the BIOS or by some DMA device
[all …]
|
| /linux/arch/xtensa/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
61 Xtensa processors are 32-bit RISC machines designed by Tensilica
66 a home page at <http://www.linux-xtensa.org/>.
105 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
111 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
120 bool "fsf - default (not generic) configuration"
124 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
131 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
141 Select this variant to use a custom Xtensa processor configuration.
167 ie: it supports a TLB with auto-loading, page protection.
[all …]
|
| /linux/Documentation/arch/arm/keystone/ |
| H A D | knav-qmss.rst | 5 Driver source code path
11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
12 processors(PDSP), linking RAM, descriptor pools and infrastructure
15 management of the packet queues. Packets are queued/de-queued by writing or
18 Linking RAM registers are used to link the descriptors which are stored in
19 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 The QMSS driver manages the PDSP setups, linking RAM regions,
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
[all …]
|
| /linux/Documentation/fb/ |
| H A D | cirrusfb.rst | 12 - SD64
13 - Piccolo
14 - Picasso
15 - Spectrum
16 - Alpine (GD-543x/4x)
17 - Picasso4 (GD-5446)
18 - GD-5480
19 - Laguna (GD-546x)
22 - PCI
23 - Zorro
[all …]
|
| /linux/drivers/mtd/chips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
23 compatible with the Common Flash Interface, but will use the common
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
39 option does not directly affect the code, but will enable other
53 are expected to be wired to the CPU in 'host-endian' form.
[all …]
|
| /linux/drivers/mtd/ |
| H A D | Kconfig | 5 Memory Technology Devices are flash, RAM and similar chips, often
24 test. Do not use these tests unless you really know what you do.
44 as block devices, it is possible to use MTD devices which are based
45 on RAM chips in this manner. This block device is a user of MTD
57 You do not need this option for use with the DiskOnChip devices. For
65 This allows you to mount read-only file systems (such as cramfs)
69 You do not need this option for use with the DiskOnChip devices. For
81 is part of the PCMCIA specification. It uses a kind of pseudo-
83 512-byte sectors, on top of which you put a 'normal' file system.
85 You may find that the algorithms used in this code are patented
[all …]
|
| /linux/drivers/mtd/devices/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Self-contained MTD device drivers"
7 tristate "Ramix PMC551 PCI Mezzanine RAM card support"
10 This provides a MTD device driver for the Ramix PMC551 RAM PCI card
12 These devices come in memory configurations from 32M - 1G. If you
18 will use a 1G memory map as its view of the device. As a module,
41 tristate "DEC MS02-NV NVRAM module support"
44 This is an MTD driver for the DEC's MS02-NV (54-20948-01) battery
45 backed-up NVRAM module. The module was originally meant as an NFS
49 If you want to compile this driver as a module ( = code which can be
[all …]
|
| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
53 provide current information about the system's RAM, for instance
55 for the DRAM's temperature. Slower refresh rate means cooler RAM,
56 higher refresh rate means hotter RAM.
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
[all …]
|
| /linux/drivers/mtd/maps/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
17 ROM driver code to communicate with chips which are mapped
21 with config options or at run-time.
74 and RAM driver code to communicate with chips which are mapped
79 bool "Baikal-T1 Boot ROMs OF-based physical memory map handling"
86 This provides some extra DT physmap parsing for the Baikal-T1
87 platforms, some detection and setting up ROMs-specific accessors.
90 bool "ARM Versatile OF-based physical memory map handling"
100 bool "Cortina Gemini OF-based physical memory map handling"
[all …]
|
| /linux/Documentation/admin-guide/pm/ |
| H A D | sleep-states.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 Sleep states are global low-power states of the entire system in which user
14 space code cannot be executed and the overall system activity is significantly
28 Suspend-to-Idle
29 ---------------
31 This is a generic, pure software, light-weight variant of system suspend (also
34 I/O devices into low-power states (possibly lower-power than available in the
38 The system is woken up from this state by in-band interrupts, so theoretically
43 or :ref:`suspend-to-RAM <s2ram>`, or it can be used in addition to any of the
50 -------
[all …]
|
| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
10 * i40e_init_nvm - Initialize NVM function pointers
17 * We are accessing FLASH always thru the Shadow RAM.
21 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
32 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
38 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
39 nvm->blank_nvm_mode = false; in i40e_init_nvm()
41 nvm->blank_nvm_mode = true; in i40e_init_nvm()
42 ret_code = -EIO; in i40e_init_nvm()
[all …]
|
| /linux/arch/powerpc/include/asm/ |
| H A D | cpm1.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * are needed. -- Dan
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
14 * bytes of the DP RAM and relocates the I2C parameter area to the
15 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
16 * or other use.
48 * and dual port ram.
58 /* Parameter RAM offsets.
70 /* Define enough so I can at least use the serial port as a UART.
76 u_char smc_rfcr; /* Rx function code */
[all …]
|
| /linux/drivers/soc/fsl/qe/ |
| H A D | qe_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Common CPM code
7 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
11 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
57 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); in cpm_muram_init()
60 np = of_find_node_by_name(NULL, "data-only"); in cpm_muram_init()
63 ret = -ENODEV; in cpm_muram_init()
68 muram_pool = gen_pool_create(0, -1); in cpm_muram_init()
71 ret = -ENOMEM; in cpm_muram_init()
77 ret = -ENODEV; in cpm_muram_init()
[all …]
|