Home
last modified time | relevance | path

Searched +full:tx +full:- +full:use +full:- +full:rgmii +full:- +full:clk (Results 1 – 25 of 53) sorted by relevance

123

/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
34 nvmem-cells:
40 nvmem-cell-names:
[all …]
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
19 - if:
24 - ethernet-phy-id004d.d0c0
33 - description:
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
16 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
17 starfive,tx-use-rgmii-clk;
26 cap-mmc-highspeed;
27 cap-mmc-hw-reset;
28 mmc-ddr-1_8v;
[all …]
H A Djh7110-orangepi-rv.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
11 compatible = "xunlong,orangepi-rv", "starfive,jh7110";
14 reg_vcc3v3_pcie: regulator-vcc3v3-pcie {
15 compatible = "regulator-fixed";
16 regulator-name = "vcc3v3-pcie";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
19 regulator-always-on;
[all …]
H A Djh7110-milkv-marscm.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "jh7110-common.dtsi"
18 sdio_pwrseq: sdio-pwrseq {
19 compatible = "mmc-pwrseq-simple";
20 reset-gpios = <&sysgpio 33 GPIO_ACTIVE_LOW>;
25 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
26 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
27 starfive,tx-use-rgmii-clk;
[all …]
H A Djh7110-starfive-visionfive-2-lite.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-common.dtsi"
11 vcc_3v3_pcie: regulator-vcc-3v3-pcie {
12 compatible = "regulator-fixed";
13 enable-active-high;
15 regulator-name = "vcc_3v3_pcie";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
22 /delete-node/ opp-375000000;
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
40 * internal TX clock just fine. The A31 GMAC clock module does not have
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
33 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
34 * cycle of the 125MHz RGMII TX cloc
145 struct clk *clk; meson8b_init_rgmii_tx_clk() local
272 meson8b_devm_clk_prepare_enable(struct meson8b_dwmac * dwmac,struct clk * clk) meson8b_devm_clk_prepare_enable() argument
[all...]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
7 * port is connected via RGMII. This port is not TSN aware.
9 * all led out to the carrier for customer use.
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
[all …]
H A Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
24 stdout-path = &lpuart0;
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
30 mbox-names = "tx", "rx", "rxdb";
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
[all …]
H A Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
[all …]
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8155p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
24 stdout-path = "serial0:115200n8";
27 vreg_3p3: vreg-3p3-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_3p3";
30 regulator-min-microvolt = <3300000>;
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/linux/drivers/net/ethernet/broadcom/genet/
H A Dbcmmii.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2025 Broadcom
23 #include <linux/platform_data/mdio-bcm-unimac.h>
30 struct phy_device *phydev = dev->phydev; in bcmgenet_mac_config()
35 if (phydev->speed == SPEED_1000) in bcmgenet_mac_config()
37 else if (phydev->spee in bcmgenet_mac_config()
136 bcmgenet_phy_pause_set(struct net_device * dev,bool rx,bool tx) bcmgenet_phy_pause_set() argument
[all...]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp151c-mect1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial0:1500000n8";
33 v3v3: regulator-v3v3 {
34 compatible = "regulator-fixed";
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1",
12 "altr,socfpga-arria10", "altr,socfpga";
27 stdout-path = "serial1:115200n8";
30 /* Adjusted the i2c labels to use generic base-board dtsi files for
34 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
36 * bus in a generic base-board .dtsi file.
48 i2c-sda-hold-time-ns = <300>;
49 clock-frequency = <100000>;
63 i2c-sda-hold-time-ns = <300>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
26 * restriction, including without limitation the rights to use,
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
[all …]
H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
26 * restriction, including without limitation the rights to use,
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
26 * restriction, including without limitation the rights to use,
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp257f-ev1.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
13 #include "stm32mp25-pinctrl.dtsi"
14 #include "stm32mp25xxai-pinctrl.dtsi"
17 model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
18 compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
28 stdout-path = "serial0:115200n8";
[all …]

123