14bd3bb7bSSamin Guo // SPDX-License-Identifier: GPL-2.0+
24bd3bb7bSSamin Guo /*
34bd3bb7bSSamin Guo * StarFive DWMAC platform driver
44bd3bb7bSSamin Guo *
54bd3bb7bSSamin Guo * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
64bd3bb7bSSamin Guo * Copyright (C) 2022 StarFive Technology Co., Ltd.
74bd3bb7bSSamin Guo *
84bd3bb7bSSamin Guo */
94bd3bb7bSSamin Guo
103d40aed8SRob Herring #include <linux/mod_devicetable.h>
113d40aed8SRob Herring #include <linux/platform_device.h>
123d40aed8SRob Herring #include <linux/property.h>
134bd3bb7bSSamin Guo #include <linux/mfd/syscon.h>
144bd3bb7bSSamin Guo #include <linux/regmap.h>
154bd3bb7bSSamin Guo
164bd3bb7bSSamin Guo #include "stmmac_platform.h"
174bd3bb7bSSamin Guo
18b4a5afa5SSamin Guo #define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
19b4a5afa5SSamin Guo #define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
20b4a5afa5SSamin Guo #define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
21b4a5afa5SSamin Guo
22*8d4597b8SCristian Ciocaltea #define JH7100_SYSMAIN_REGISTER49_DLYCHAIN 0xc8
23*8d4597b8SCristian Ciocaltea
24*8d4597b8SCristian Ciocaltea struct starfive_dwmac_data {
25*8d4597b8SCristian Ciocaltea unsigned int gtxclk_dlychain;
26*8d4597b8SCristian Ciocaltea };
27*8d4597b8SCristian Ciocaltea
284bd3bb7bSSamin Guo struct starfive_dwmac {
294bd3bb7bSSamin Guo struct device *dev;
304bd3bb7bSSamin Guo struct clk *clk_tx;
31*8d4597b8SCristian Ciocaltea const struct starfive_dwmac_data *data;
324bd3bb7bSSamin Guo };
334bd3bb7bSSamin Guo
starfive_dwmac_fix_mac_speed(void * priv,unsigned int speed,unsigned int mode)341fc04a0bSShenwei Wang static void starfive_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
354bd3bb7bSSamin Guo {
364bd3bb7bSSamin Guo struct starfive_dwmac *dwmac = priv;
374bd3bb7bSSamin Guo unsigned long rate;
384bd3bb7bSSamin Guo int err;
394bd3bb7bSSamin Guo
404bd3bb7bSSamin Guo rate = clk_get_rate(dwmac->clk_tx);
414bd3bb7bSSamin Guo
424bd3bb7bSSamin Guo switch (speed) {
434bd3bb7bSSamin Guo case SPEED_1000:
444bd3bb7bSSamin Guo rate = 125000000;
454bd3bb7bSSamin Guo break;
464bd3bb7bSSamin Guo case SPEED_100:
474bd3bb7bSSamin Guo rate = 25000000;
484bd3bb7bSSamin Guo break;
494bd3bb7bSSamin Guo case SPEED_10:
504bd3bb7bSSamin Guo rate = 2500000;
514bd3bb7bSSamin Guo break;
524bd3bb7bSSamin Guo default:
534bd3bb7bSSamin Guo dev_err(dwmac->dev, "invalid speed %u\n", speed);
544bd3bb7bSSamin Guo break;
554bd3bb7bSSamin Guo }
564bd3bb7bSSamin Guo
574bd3bb7bSSamin Guo err = clk_set_rate(dwmac->clk_tx, rate);
584bd3bb7bSSamin Guo if (err)
594bd3bb7bSSamin Guo dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
604bd3bb7bSSamin Guo }
614bd3bb7bSSamin Guo
starfive_dwmac_set_mode(struct plat_stmmacenet_data * plat_dat)62b4a5afa5SSamin Guo static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
63b4a5afa5SSamin Guo {
64b4a5afa5SSamin Guo struct starfive_dwmac *dwmac = plat_dat->bsp_priv;
65b4a5afa5SSamin Guo struct regmap *regmap;
66b4a5afa5SSamin Guo unsigned int args[2];
67b4a5afa5SSamin Guo unsigned int mode;
68b4a5afa5SSamin Guo int err;
69b4a5afa5SSamin Guo
70a014c355SRussell King (Oracle) switch (plat_dat->mac_interface) {
71b4a5afa5SSamin Guo case PHY_INTERFACE_MODE_RMII:
72b4a5afa5SSamin Guo mode = STARFIVE_DWMAC_PHY_INFT_RMII;
73b4a5afa5SSamin Guo break;
74b4a5afa5SSamin Guo
75b4a5afa5SSamin Guo case PHY_INTERFACE_MODE_RGMII:
76b4a5afa5SSamin Guo case PHY_INTERFACE_MODE_RGMII_ID:
77*8d4597b8SCristian Ciocaltea case PHY_INTERFACE_MODE_RGMII_RXID:
78*8d4597b8SCristian Ciocaltea case PHY_INTERFACE_MODE_RGMII_TXID:
79b4a5afa5SSamin Guo mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
80b4a5afa5SSamin Guo break;
81b4a5afa5SSamin Guo
82b4a5afa5SSamin Guo default:
83b4a5afa5SSamin Guo dev_err(dwmac->dev, "unsupported interface %d\n",
84a014c355SRussell King (Oracle) plat_dat->mac_interface);
85b4a5afa5SSamin Guo return -EINVAL;
86b4a5afa5SSamin Guo }
87b4a5afa5SSamin Guo
88b4a5afa5SSamin Guo regmap = syscon_regmap_lookup_by_phandle_args(dwmac->dev->of_node,
89b4a5afa5SSamin Guo "starfive,syscon",
90b4a5afa5SSamin Guo 2, args);
91b4a5afa5SSamin Guo if (IS_ERR(regmap))
92b4a5afa5SSamin Guo return dev_err_probe(dwmac->dev, PTR_ERR(regmap), "getting the regmap failed\n");
93b4a5afa5SSamin Guo
94b4a5afa5SSamin Guo /* args[0]:offset args[1]: shift */
95b4a5afa5SSamin Guo err = regmap_update_bits(regmap, args[0],
96b4a5afa5SSamin Guo STARFIVE_DWMAC_PHY_INFT_FIELD << args[1],
97b4a5afa5SSamin Guo mode << args[1]);
98b4a5afa5SSamin Guo if (err)
99b4a5afa5SSamin Guo return dev_err_probe(dwmac->dev, err, "error setting phy mode\n");
100b4a5afa5SSamin Guo
101*8d4597b8SCristian Ciocaltea if (dwmac->data) {
102*8d4597b8SCristian Ciocaltea err = regmap_write(regmap, JH7100_SYSMAIN_REGISTER49_DLYCHAIN,
103*8d4597b8SCristian Ciocaltea dwmac->data->gtxclk_dlychain);
104*8d4597b8SCristian Ciocaltea if (err)
105*8d4597b8SCristian Ciocaltea return dev_err_probe(dwmac->dev, err,
106*8d4597b8SCristian Ciocaltea "error selecting gtxclk delay chain\n");
107*8d4597b8SCristian Ciocaltea }
108*8d4597b8SCristian Ciocaltea
109b4a5afa5SSamin Guo return 0;
110b4a5afa5SSamin Guo }
111b4a5afa5SSamin Guo
starfive_dwmac_probe(struct platform_device * pdev)1124bd3bb7bSSamin Guo static int starfive_dwmac_probe(struct platform_device *pdev)
1134bd3bb7bSSamin Guo {
1144bd3bb7bSSamin Guo struct plat_stmmacenet_data *plat_dat;
1154bd3bb7bSSamin Guo struct stmmac_resources stmmac_res;
1164bd3bb7bSSamin Guo struct starfive_dwmac *dwmac;
1174bd3bb7bSSamin Guo struct clk *clk_gtx;
1184bd3bb7bSSamin Guo int err;
1194bd3bb7bSSamin Guo
1204bd3bb7bSSamin Guo err = stmmac_get_platform_resources(pdev, &stmmac_res);
1214bd3bb7bSSamin Guo if (err)
1224bd3bb7bSSamin Guo return dev_err_probe(&pdev->dev, err,
1234bd3bb7bSSamin Guo "failed to get resources\n");
1244bd3bb7bSSamin Guo
1256d6c1193SJisheng Zhang plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1264bd3bb7bSSamin Guo if (IS_ERR(plat_dat))
1274bd3bb7bSSamin Guo return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
1284bd3bb7bSSamin Guo "dt configuration failed\n");
1294bd3bb7bSSamin Guo
1304bd3bb7bSSamin Guo dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
1314bd3bb7bSSamin Guo if (!dwmac)
1324bd3bb7bSSamin Guo return -ENOMEM;
1334bd3bb7bSSamin Guo
134*8d4597b8SCristian Ciocaltea dwmac->data = device_get_match_data(&pdev->dev);
135*8d4597b8SCristian Ciocaltea
1364bd3bb7bSSamin Guo dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx");
1374bd3bb7bSSamin Guo if (IS_ERR(dwmac->clk_tx))
1384bd3bb7bSSamin Guo return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx),
1394bd3bb7bSSamin Guo "error getting tx clock\n");
1404bd3bb7bSSamin Guo
1414bd3bb7bSSamin Guo clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx");
1424bd3bb7bSSamin Guo if (IS_ERR(clk_gtx))
1434bd3bb7bSSamin Guo return dev_err_probe(&pdev->dev, PTR_ERR(clk_gtx),
1444bd3bb7bSSamin Guo "error getting gtx clock\n");
1454bd3bb7bSSamin Guo
1464bd3bb7bSSamin Guo /* Generally, the rgmii_tx clock is provided by the internal clock,
1474bd3bb7bSSamin Guo * which needs to match the corresponding clock frequency according
1484bd3bb7bSSamin Guo * to different speeds. If the rgmii_tx clock is provided by the
1494bd3bb7bSSamin Guo * external rgmii_rxin, there is no need to configure the clock
1504bd3bb7bSSamin Guo * internally, because rgmii_rxin will be adaptively adjusted.
1514bd3bb7bSSamin Guo */
1524bd3bb7bSSamin Guo if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk"))
1534bd3bb7bSSamin Guo plat_dat->fix_mac_speed = starfive_dwmac_fix_mac_speed;
1544bd3bb7bSSamin Guo
1554bd3bb7bSSamin Guo dwmac->dev = &pdev->dev;
1564bd3bb7bSSamin Guo plat_dat->bsp_priv = dwmac;
1574bd3bb7bSSamin Guo plat_dat->dma_cfg->dche = true;
1584bd3bb7bSSamin Guo
159b4a5afa5SSamin Guo err = starfive_dwmac_set_mode(plat_dat);
160b4a5afa5SSamin Guo if (err)
161b4a5afa5SSamin Guo return err;
162b4a5afa5SSamin Guo
1636d6c1193SJisheng Zhang return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1644bd3bb7bSSamin Guo }
1654bd3bb7bSSamin Guo
166*8d4597b8SCristian Ciocaltea static const struct starfive_dwmac_data jh7100_data = {
167*8d4597b8SCristian Ciocaltea .gtxclk_dlychain = 4,
168*8d4597b8SCristian Ciocaltea };
169*8d4597b8SCristian Ciocaltea
1704bd3bb7bSSamin Guo static const struct of_device_id starfive_dwmac_match[] = {
171*8d4597b8SCristian Ciocaltea { .compatible = "starfive,jh7100-dwmac", .data = &jh7100_data },
1724bd3bb7bSSamin Guo { .compatible = "starfive,jh7110-dwmac" },
1734bd3bb7bSSamin Guo { /* sentinel */ }
1744bd3bb7bSSamin Guo };
1754bd3bb7bSSamin Guo MODULE_DEVICE_TABLE(of, starfive_dwmac_match);
1764bd3bb7bSSamin Guo
1774bd3bb7bSSamin Guo static struct platform_driver starfive_dwmac_driver = {
1784bd3bb7bSSamin Guo .probe = starfive_dwmac_probe,
1792c9fc838SJisheng Zhang .remove_new = stmmac_pltfr_remove,
1804bd3bb7bSSamin Guo .driver = {
1814bd3bb7bSSamin Guo .name = "starfive-dwmac",
1824bd3bb7bSSamin Guo .pm = &stmmac_pltfr_pm_ops,
1834bd3bb7bSSamin Guo .of_match_table = starfive_dwmac_match,
1844bd3bb7bSSamin Guo },
1854bd3bb7bSSamin Guo };
1864bd3bb7bSSamin Guo module_platform_driver(starfive_dwmac_driver);
1874bd3bb7bSSamin Guo
1884bd3bb7bSSamin Guo MODULE_LICENSE("GPL");
1894bd3bb7bSSamin Guo MODULE_DESCRIPTION("StarFive DWMAC platform driver");
1904bd3bb7bSSamin Guo MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1914bd3bb7bSSamin Guo MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
192