1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
29f2f381fSJeff Kirsher /*
39f2f381fSJeff Kirsher * Atmel MACB Ethernet Controller driver
49f2f381fSJeff Kirsher *
59f2f381fSJeff Kirsher * Copyright (C) 2004-2006 Atmel Corporation
69f2f381fSJeff Kirsher */
79f2f381fSJeff Kirsher #ifndef _MACB_H
89f2f381fSJeff Kirsher #define _MACB_H
99f2f381fSJeff Kirsher
1020c168beSAlexandre Belloni #include <linux/clk.h>
117897b071SAntoine Tenart #include <linux/phylink.h>
12ab91f0a9SRafal Ozieblo #include <linux/ptp_clock_kernel.h>
13ab91f0a9SRafal Ozieblo #include <linux/net_tstamp.h>
14032dc41bSHarini Katakam #include <linux/interrupt.h>
158b73fa3aSRobert Hancock #include <linux/phy/phy.h>
16*c5092ba3SAllen Pais #include <linux/workqueue.h>
17fc182b85SRussell King
187b429614SRafal Ozieblo #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
197b429614SRafal Ozieblo #define MACB_EXT_DESC
207b429614SRafal Ozieblo #endif
217b429614SRafal Ozieblo
22d1d1b53dSNicolas Ferre #define MACB_GREGS_NBR 16
237c39994fSNicolas Ferre #define MACB_GREGS_VERSION 2
2402c958ddSCyrille Pitchen #define MACB_MAX_QUEUES 8
25d1d1b53dSNicolas Ferre
269f2f381fSJeff Kirsher /* MACB register offsets */
275c2fa0f6SXander Huff #define MACB_NCR 0x0000 /* Network Control */
285c2fa0f6SXander Huff #define MACB_NCFGR 0x0004 /* Network Config */
295c2fa0f6SXander Huff #define MACB_NSR 0x0008 /* Network Status */
301fd3ca4eSJoachim Eastwood #define MACB_TAR 0x000c /* AT91RM9200 only */
311fd3ca4eSJoachim Eastwood #define MACB_TCR 0x0010 /* AT91RM9200 only */
325c2fa0f6SXander Huff #define MACB_TSR 0x0014 /* Transmit Status */
335c2fa0f6SXander Huff #define MACB_RBQP 0x0018 /* RX Q Base Address */
345c2fa0f6SXander Huff #define MACB_TBQP 0x001c /* TX Q Base Address */
355c2fa0f6SXander Huff #define MACB_RSR 0x0020 /* Receive Status */
365c2fa0f6SXander Huff #define MACB_ISR 0x0024 /* Interrupt Status */
375c2fa0f6SXander Huff #define MACB_IER 0x0028 /* Interrupt Enable */
385c2fa0f6SXander Huff #define MACB_IDR 0x002c /* Interrupt Disable */
395c2fa0f6SXander Huff #define MACB_IMR 0x0030 /* Interrupt Mask */
405c2fa0f6SXander Huff #define MACB_MAN 0x0034 /* PHY Maintenance */
419f2f381fSJeff Kirsher #define MACB_PTR 0x0038
429f2f381fSJeff Kirsher #define MACB_PFR 0x003c
439f2f381fSJeff Kirsher #define MACB_FTO 0x0040
449f2f381fSJeff Kirsher #define MACB_SCF 0x0044
459f2f381fSJeff Kirsher #define MACB_MCF 0x0048
469f2f381fSJeff Kirsher #define MACB_FRO 0x004c
479f2f381fSJeff Kirsher #define MACB_FCSE 0x0050
489f2f381fSJeff Kirsher #define MACB_ALE 0x0054
499f2f381fSJeff Kirsher #define MACB_DTF 0x0058
509f2f381fSJeff Kirsher #define MACB_LCOL 0x005c
519f2f381fSJeff Kirsher #define MACB_EXCOL 0x0060
529f2f381fSJeff Kirsher #define MACB_TUND 0x0064
539f2f381fSJeff Kirsher #define MACB_CSE 0x0068
549f2f381fSJeff Kirsher #define MACB_RRE 0x006c
559f2f381fSJeff Kirsher #define MACB_ROVR 0x0070
569f2f381fSJeff Kirsher #define MACB_RSE 0x0074
579f2f381fSJeff Kirsher #define MACB_ELE 0x0078
589f2f381fSJeff Kirsher #define MACB_RJA 0x007c
599f2f381fSJeff Kirsher #define MACB_USF 0x0080
609f2f381fSJeff Kirsher #define MACB_STE 0x0084
619f2f381fSJeff Kirsher #define MACB_RLE 0x0088
629f2f381fSJeff Kirsher #define MACB_TPF 0x008c
639f2f381fSJeff Kirsher #define MACB_HRB 0x0090
649f2f381fSJeff Kirsher #define MACB_HRT 0x0094
659f2f381fSJeff Kirsher #define MACB_SA1B 0x0098
669f2f381fSJeff Kirsher #define MACB_SA1T 0x009c
679f2f381fSJeff Kirsher #define MACB_SA2B 0x00a0
689f2f381fSJeff Kirsher #define MACB_SA2T 0x00a4
699f2f381fSJeff Kirsher #define MACB_SA3B 0x00a8
709f2f381fSJeff Kirsher #define MACB_SA3T 0x00ac
719f2f381fSJeff Kirsher #define MACB_SA4B 0x00b0
729f2f381fSJeff Kirsher #define MACB_SA4T 0x00b4
739f2f381fSJeff Kirsher #define MACB_TID 0x00b8
749f2f381fSJeff Kirsher #define MACB_TPQ 0x00bc
759f2f381fSJeff Kirsher #define MACB_USRIO 0x00c0
769f2f381fSJeff Kirsher #define MACB_WOL 0x00c4
77f75ba50bSJamie Iles #define MACB_MID 0x00fc
78fff8019aSHarini Katakam #define MACB_TBQPH 0x04C8
79fff8019aSHarini Katakam #define MACB_RBQPH 0x04D4
80f75ba50bSJamie Iles
81f75ba50bSJamie Iles /* GEM register offsets. */
82e4e143e2SParshuram Thombare #define GEM_NCR 0x0000 /* Network Control */
835c2fa0f6SXander Huff #define GEM_NCFGR 0x0004 /* Network Config */
845c2fa0f6SXander Huff #define GEM_USRIO 0x000c /* User IO */
855c2fa0f6SXander Huff #define GEM_DMACFG 0x0010 /* DMA Configuration */
86cae4bc06SMaulik Jodhani #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
8798b5a0f4SHarini Katakam #define GEM_JML 0x0048 /* Jumbo Max Length */
88e4e143e2SParshuram Thombare #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
895c2fa0f6SXander Huff #define GEM_HRB 0x0080 /* Hash Bottom */
905c2fa0f6SXander Huff #define GEM_HRT 0x0084 /* Hash Top */
915c2fa0f6SXander Huff #define GEM_SA1B 0x0088 /* Specific1 Bottom */
925c2fa0f6SXander Huff #define GEM_SA1T 0x008C /* Specific1 Top */
935c2fa0f6SXander Huff #define GEM_SA2B 0x0090 /* Specific2 Bottom */
945c2fa0f6SXander Huff #define GEM_SA2T 0x0094 /* Specific2 Top */
955c2fa0f6SXander Huff #define GEM_SA3B 0x0098 /* Specific3 Bottom */
965c2fa0f6SXander Huff #define GEM_SA3T 0x009C /* Specific3 Top */
975c2fa0f6SXander Huff #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
985c2fa0f6SXander Huff #define GEM_SA4T 0x00A4 /* Specific4 Top */
99558e35ccSNicolas Ferre #define GEM_WOL 0x00b8 /* Wake on LAN */
100ee4e92c2SHarini Katakam #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
101ee4e92c2SHarini Katakam #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
102ab91f0a9SRafal Ozieblo #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
103ab91f0a9SRafal Ozieblo #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
104ab91f0a9SRafal Ozieblo #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
105ab91f0a9SRafal Ozieblo #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
1065c2fa0f6SXander Huff #define GEM_OTX 0x0100 /* Octets transmitted */
1076f79eed8SXander Huff #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
1086f79eed8SXander Huff #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
1096f79eed8SXander Huff #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
1106f79eed8SXander Huff #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
1116f79eed8SXander Huff #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
1126f79eed8SXander Huff #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
1136f79eed8SXander Huff #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
1146f79eed8SXander Huff #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
1156f79eed8SXander Huff #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
1166f79eed8SXander Huff #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
1176f79eed8SXander Huff #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
1186f79eed8SXander Huff #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
1196f79eed8SXander Huff #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
1206f79eed8SXander Huff #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
1216f79eed8SXander Huff #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
1226f79eed8SXander Huff #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
1236f79eed8SXander Huff #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
1246f79eed8SXander Huff #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
1256f79eed8SXander Huff #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
1266f79eed8SXander Huff #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
1273ff13f1cSXander Huff #define GEM_ORX 0x0150 /* Octets received */
1286f79eed8SXander Huff #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
1296f79eed8SXander Huff #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
1306f79eed8SXander Huff #define GEM_RXCNT 0x0158 /* Frames Received Counter */
1316f79eed8SXander Huff #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
1326f79eed8SXander Huff #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
1336f79eed8SXander Huff #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
1346f79eed8SXander Huff #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
1356f79eed8SXander Huff #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
1366f79eed8SXander Huff #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
1376f79eed8SXander Huff #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
1386f79eed8SXander Huff #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
1396f79eed8SXander Huff #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
1406f79eed8SXander Huff #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
1416f79eed8SXander Huff #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
1426f79eed8SXander Huff #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
1436f79eed8SXander Huff #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
1446f79eed8SXander Huff #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
1456f79eed8SXander Huff #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
1466f79eed8SXander Huff #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
1476f79eed8SXander Huff #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
1486f79eed8SXander Huff #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
1496f79eed8SXander Huff #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
1506f79eed8SXander Huff #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
1516f79eed8SXander Huff #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
1526f79eed8SXander Huff #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
153c2594d80SAndrei.Pistirica@microchip.com #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
154c2594d80SAndrei.Pistirica@microchip.com #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
155c2594d80SAndrei.Pistirica@microchip.com #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
156c2594d80SAndrei.Pistirica@microchip.com #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
157c2594d80SAndrei.Pistirica@microchip.com #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
158c2594d80SAndrei.Pistirica@microchip.com #define GEM_TI 0x01dc /* 1588 Timer Increment */
159c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
160c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
161c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
162c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
163c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
164c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
165c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
166c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
167e276e5e4SRobert Hancock #define GEM_PCSCNTRL 0x0200 /* PCS Control */
168e276e5e4SRobert Hancock #define GEM_PCSSTS 0x0204 /* PCS Status */
169e276e5e4SRobert Hancock #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */
170e276e5e4SRobert Hancock #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */
171e276e5e4SRobert Hancock #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */
172e276e5e4SRobert Hancock #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */
173e276e5e4SRobert Hancock #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */
174e276e5e4SRobert Hancock #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */
175e276e5e4SRobert Hancock #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */
176e276e5e4SRobert Hancock #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */
1775c2fa0f6SXander Huff #define GEM_DCFG1 0x0280 /* Design Config 1 */
1785c2fa0f6SXander Huff #define GEM_DCFG2 0x0284 /* Design Config 2 */
1795c2fa0f6SXander Huff #define GEM_DCFG3 0x0288 /* Design Config 3 */
1805c2fa0f6SXander Huff #define GEM_DCFG4 0x028c /* Design Config 4 */
1815c2fa0f6SXander Huff #define GEM_DCFG5 0x0290 /* Design Config 5 */
1825c2fa0f6SXander Huff #define GEM_DCFG6 0x0294 /* Design Config 6 */
1835c2fa0f6SXander Huff #define GEM_DCFG7 0x0298 /* Design Config 7 */
184ae8223deSRafal Ozieblo #define GEM_DCFG8 0x029C /* Design Config 8 */
185404cd086SHarini Katakam #define GEM_DCFG10 0x02A4 /* Design Config 10 */
186e4e143e2SParshuram Thombare #define GEM_DCFG12 0x02AC /* Design Config 12 */
187e4e143e2SParshuram Thombare #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */
188e4e143e2SParshuram Thombare #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */
1899f2f381fSJeff Kirsher
190ab91f0a9SRafal Ozieblo #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
191ab91f0a9SRafal Ozieblo #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
192ab91f0a9SRafal Ozieblo
193ae8223deSRafal Ozieblo /* Screener Type 2 match registers */
194ae8223deSRafal Ozieblo #define GEM_SCRT2 0x540
195ae8223deSRafal Ozieblo
196ae8223deSRafal Ozieblo /* EtherType registers */
197ae8223deSRafal Ozieblo #define GEM_ETHT 0x06E0
198ae8223deSRafal Ozieblo
199ae8223deSRafal Ozieblo /* Type 2 compare registers */
200ae8223deSRafal Ozieblo #define GEM_T2CMPW0 0x0700
201ae8223deSRafal Ozieblo #define GEM_T2CMPW1 0x0704
202ae8223deSRafal Ozieblo #define T2CMP_OFST(t2idx) (t2idx * 2)
203ae8223deSRafal Ozieblo
204ae8223deSRafal Ozieblo /* type 2 compare registers
205ae8223deSRafal Ozieblo * each location requires 3 compare regs
206ae8223deSRafal Ozieblo */
207ae8223deSRafal Ozieblo #define GEM_IP4SRC_CMP(idx) (idx * 3)
208ae8223deSRafal Ozieblo #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
209ae8223deSRafal Ozieblo #define GEM_PORT_CMP(idx) (idx * 3 + 2)
210ae8223deSRafal Ozieblo
211ae8223deSRafal Ozieblo /* Which screening type 2 EtherType register will be used (0 - 7) */
212ae8223deSRafal Ozieblo #define SCRT2_ETHT 0
213ae8223deSRafal Ozieblo
21402c958ddSCyrille Pitchen #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
21502c958ddSCyrille Pitchen #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
216fff8019aSHarini Katakam #define GEM_TBQPH(hw_q) (0x04C8)
21702c958ddSCyrille Pitchen #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
218ae1f2a56SRafal Ozieblo #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
219ae1f2a56SRafal Ozieblo #define GEM_RBQPH(hw_q) (0x04D4)
22002c958ddSCyrille Pitchen #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
22102c958ddSCyrille Pitchen #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
22202c958ddSCyrille Pitchen #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
22302c958ddSCyrille Pitchen
2249f2f381fSJeff Kirsher /* Bitfields in NCR */
2255c2fa0f6SXander Huff #define MACB_LB_OFFSET 0 /* reserved */
2269f2f381fSJeff Kirsher #define MACB_LB_SIZE 1
2275c2fa0f6SXander Huff #define MACB_LLB_OFFSET 1 /* Loop back local */
2289f2f381fSJeff Kirsher #define MACB_LLB_SIZE 1
2295c2fa0f6SXander Huff #define MACB_RE_OFFSET 2 /* Receive enable */
2309f2f381fSJeff Kirsher #define MACB_RE_SIZE 1
2315c2fa0f6SXander Huff #define MACB_TE_OFFSET 3 /* Transmit enable */
2329f2f381fSJeff Kirsher #define MACB_TE_SIZE 1
2335c2fa0f6SXander Huff #define MACB_MPE_OFFSET 4 /* Management port enable */
2349f2f381fSJeff Kirsher #define MACB_MPE_SIZE 1
2355c2fa0f6SXander Huff #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
2369f2f381fSJeff Kirsher #define MACB_CLRSTAT_SIZE 1
2375c2fa0f6SXander Huff #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
2389f2f381fSJeff Kirsher #define MACB_INCSTAT_SIZE 1
2395c2fa0f6SXander Huff #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
2409f2f381fSJeff Kirsher #define MACB_WESTAT_SIZE 1
2415c2fa0f6SXander Huff #define MACB_BP_OFFSET 8 /* Back pressure */
2429f2f381fSJeff Kirsher #define MACB_BP_SIZE 1
2435c2fa0f6SXander Huff #define MACB_TSTART_OFFSET 9 /* Start transmission */
2449f2f381fSJeff Kirsher #define MACB_TSTART_SIZE 1
2455c2fa0f6SXander Huff #define MACB_THALT_OFFSET 10 /* Transmit halt */
2469f2f381fSJeff Kirsher #define MACB_THALT_SIZE 1
2475c2fa0f6SXander Huff #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
2489f2f381fSJeff Kirsher #define MACB_NCR_TPF_SIZE 1
2496f79eed8SXander Huff #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
2509f2f381fSJeff Kirsher #define MACB_TZQ_SIZE 1
2511dac0084SClaudiu Beznea #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
252ee4e92c2SHarini Katakam #define MACB_PTPUNI_OFFSET 20 /* PTP Unicast packet enable */
253ee4e92c2SHarini Katakam #define MACB_PTPUNI_SIZE 1
254ab91f0a9SRafal Ozieblo #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
255ab91f0a9SRafal Ozieblo #define MACB_OSSMODE_SIZE 1
2561a9b5a26SClaudiu Beznea #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
2571a9b5a26SClaudiu Beznea #define MACB_MIIONRGMII_SIZE 1
2589f2f381fSJeff Kirsher
2599f2f381fSJeff Kirsher /* Bitfields in NCFGR */
2605c2fa0f6SXander Huff #define MACB_SPD_OFFSET 0 /* Speed */
2619f2f381fSJeff Kirsher #define MACB_SPD_SIZE 1
2625c2fa0f6SXander Huff #define MACB_FD_OFFSET 1 /* Full duplex */
2639f2f381fSJeff Kirsher #define MACB_FD_SIZE 1
2645c2fa0f6SXander Huff #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
2659f2f381fSJeff Kirsher #define MACB_BIT_RATE_SIZE 1
2665c2fa0f6SXander Huff #define MACB_JFRAME_OFFSET 3 /* reserved */
2679f2f381fSJeff Kirsher #define MACB_JFRAME_SIZE 1
2685c2fa0f6SXander Huff #define MACB_CAF_OFFSET 4 /* Copy all frames */
2699f2f381fSJeff Kirsher #define MACB_CAF_SIZE 1
2705c2fa0f6SXander Huff #define MACB_NBC_OFFSET 5 /* No broadcast */
2719f2f381fSJeff Kirsher #define MACB_NBC_SIZE 1
2725c2fa0f6SXander Huff #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
2739f2f381fSJeff Kirsher #define MACB_NCFGR_MTI_SIZE 1
2745c2fa0f6SXander Huff #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
2759f2f381fSJeff Kirsher #define MACB_UNI_SIZE 1
2765c2fa0f6SXander Huff #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
2779f2f381fSJeff Kirsher #define MACB_BIG_SIZE 1
2786f79eed8SXander Huff #define MACB_EAE_OFFSET 9 /* External address match enable */
2799f2f381fSJeff Kirsher #define MACB_EAE_SIZE 1
2809f2f381fSJeff Kirsher #define MACB_CLK_OFFSET 10
2819f2f381fSJeff Kirsher #define MACB_CLK_SIZE 2
2825c2fa0f6SXander Huff #define MACB_RTY_OFFSET 12 /* Retry test */
2839f2f381fSJeff Kirsher #define MACB_RTY_SIZE 1
2845c2fa0f6SXander Huff #define MACB_PAE_OFFSET 13 /* Pause enable */
2859f2f381fSJeff Kirsher #define MACB_PAE_SIZE 1
2861fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
2871fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
2885c2fa0f6SXander Huff #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
2899f2f381fSJeff Kirsher #define MACB_RBOF_SIZE 2
2906f79eed8SXander Huff #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
2919f2f381fSJeff Kirsher #define MACB_RLCE_SIZE 1
2925c2fa0f6SXander Huff #define MACB_DRFCS_OFFSET 17 /* FCS remove */
2939f2f381fSJeff Kirsher #define MACB_DRFCS_SIZE 1
2949f2f381fSJeff Kirsher #define MACB_EFRHD_OFFSET 18
2959f2f381fSJeff Kirsher #define MACB_EFRHD_SIZE 1
2969f2f381fSJeff Kirsher #define MACB_IRXFCS_OFFSET 19
2979f2f381fSJeff Kirsher #define MACB_IRXFCS_SIZE 1
2989f2f381fSJeff Kirsher
299e4e143e2SParshuram Thombare /* GEM specific NCR bitfields. */
300e4e143e2SParshuram Thombare #define GEM_ENABLE_HS_MAC_OFFSET 31
301e4e143e2SParshuram Thombare #define GEM_ENABLE_HS_MAC_SIZE 1
302e4e143e2SParshuram Thombare
30370c9f3d4SJamie Iles /* GEM specific NCFGR bitfields. */
304e4e143e2SParshuram Thombare #define GEM_FD_OFFSET 1 /* Full duplex */
305e4e143e2SParshuram Thombare #define GEM_FD_SIZE 1
3065c2fa0f6SXander Huff #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
307140b7552SPatrice Vilchez #define GEM_GBE_SIZE 1
308022be25cSPunnaiah Choudary Kalluri #define GEM_PCSSEL_OFFSET 11
309022be25cSPunnaiah Choudary Kalluri #define GEM_PCSSEL_SIZE 1
310e4e143e2SParshuram Thombare #define GEM_PAE_OFFSET 13 /* Pause enable */
311e4e143e2SParshuram Thombare #define GEM_PAE_SIZE 1
3125c2fa0f6SXander Huff #define GEM_CLK_OFFSET 18 /* MDC clock division */
31370c9f3d4SJamie Iles #define GEM_CLK_SIZE 3
3145c2fa0f6SXander Huff #define GEM_DBW_OFFSET 21 /* Data bus width */
315757a03c6SJamie Iles #define GEM_DBW_SIZE 2
316924ec53cSCyrille Pitchen #define GEM_RXCOEN_OFFSET 24
317924ec53cSCyrille Pitchen #define GEM_RXCOEN_SIZE 1
318022be25cSPunnaiah Choudary Kalluri #define GEM_SGMIIEN_OFFSET 27
319022be25cSPunnaiah Choudary Kalluri #define GEM_SGMIIEN_SIZE 1
320022be25cSPunnaiah Choudary Kalluri
321757a03c6SJamie Iles
322757a03c6SJamie Iles /* Constants for data bus width. */
3236f79eed8SXander Huff #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
3246f79eed8SXander Huff #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
3256f79eed8SXander Huff #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
326757a03c6SJamie Iles
3270116da4fSJamie Iles /* Bitfields in DMACFG. */
3286f79eed8SXander Huff #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
329b3e3bd71SNicolas Ferre #define GEM_FBLDO_SIZE 5
330a50dad35SArun Chandran #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
331ea373041SArun Chandran #define GEM_ENDIA_DESC_SIZE 1
332a50dad35SArun Chandran #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
333ea373041SArun Chandran #define GEM_ENDIA_PKT_SIZE 1
3346f79eed8SXander Huff #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
335b3e3bd71SNicolas Ferre #define GEM_RXBMS_SIZE 2
3366f79eed8SXander Huff #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
337b3e3bd71SNicolas Ferre #define GEM_TXPBMS_SIZE 1
3386f79eed8SXander Huff #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
339b3e3bd71SNicolas Ferre #define GEM_TXCOEN_SIZE 1
3406f79eed8SXander Huff #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
3410116da4fSJamie Iles #define GEM_RXBS_SIZE 8
3425c2fa0f6SXander Huff #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
343b3e3bd71SNicolas Ferre #define GEM_DDRP_SIZE 1
3447b429614SRafal Ozieblo #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
3457b429614SRafal Ozieblo #define GEM_RXEXT_SIZE 1
3467b429614SRafal Ozieblo #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
3477b429614SRafal Ozieblo #define GEM_TXEXT_SIZE 1
348fff8019aSHarini Katakam #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
349fff8019aSHarini Katakam #define GEM_ADDR64_SIZE 1
350b3e3bd71SNicolas Ferre
3510116da4fSJamie Iles
352cae4bc06SMaulik Jodhani /* Bitfields in PBUFRXCUT */
353cae4bc06SMaulik Jodhani #define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */
354cae4bc06SMaulik Jodhani #define GEM_ENCUTTHRU_SIZE 1
355cae4bc06SMaulik Jodhani
3569f2f381fSJeff Kirsher /* Bitfields in NSR */
3575c2fa0f6SXander Huff #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
3589f2f381fSJeff Kirsher #define MACB_NSR_LINK_SIZE 1
3596f79eed8SXander Huff #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
3609f2f381fSJeff Kirsher #define MACB_MDIO_SIZE 1
3616f79eed8SXander Huff #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
3629f2f381fSJeff Kirsher #define MACB_IDLE_SIZE 1
3639f2f381fSJeff Kirsher
3649f2f381fSJeff Kirsher /* Bitfields in TSR */
3655c2fa0f6SXander Huff #define MACB_UBR_OFFSET 0 /* Used bit read */
3669f2f381fSJeff Kirsher #define MACB_UBR_SIZE 1
3675c2fa0f6SXander Huff #define MACB_COL_OFFSET 1 /* Collision occurred */
3689f2f381fSJeff Kirsher #define MACB_COL_SIZE 1
3695c2fa0f6SXander Huff #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
3709f2f381fSJeff Kirsher #define MACB_TSR_RLE_SIZE 1
3715c2fa0f6SXander Huff #define MACB_TGO_OFFSET 3 /* Transmit go */
3729f2f381fSJeff Kirsher #define MACB_TGO_SIZE 1
3736f79eed8SXander Huff #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
3749f2f381fSJeff Kirsher #define MACB_BEX_SIZE 1
3751fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
3761fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
3775c2fa0f6SXander Huff #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
3789f2f381fSJeff Kirsher #define MACB_COMP_SIZE 1
3795c2fa0f6SXander Huff #define MACB_UND_OFFSET 6 /* Trnasmit under run */
3809f2f381fSJeff Kirsher #define MACB_UND_SIZE 1
3819f2f381fSJeff Kirsher
3829f2f381fSJeff Kirsher /* Bitfields in RSR */
3835c2fa0f6SXander Huff #define MACB_BNA_OFFSET 0 /* Buffer not available */
3849f2f381fSJeff Kirsher #define MACB_BNA_SIZE 1
3855c2fa0f6SXander Huff #define MACB_REC_OFFSET 1 /* Frame received */
3869f2f381fSJeff Kirsher #define MACB_REC_SIZE 1
3875c2fa0f6SXander Huff #define MACB_OVR_OFFSET 2 /* Receive overrun */
3889f2f381fSJeff Kirsher #define MACB_OVR_SIZE 1
3899f2f381fSJeff Kirsher
3909f2f381fSJeff Kirsher /* Bitfields in ISR/IER/IDR/IMR */
3915c2fa0f6SXander Huff #define MACB_MFD_OFFSET 0 /* Management frame sent */
3929f2f381fSJeff Kirsher #define MACB_MFD_SIZE 1
3935c2fa0f6SXander Huff #define MACB_RCOMP_OFFSET 1 /* Receive complete */
3949f2f381fSJeff Kirsher #define MACB_RCOMP_SIZE 1
3955c2fa0f6SXander Huff #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
3969f2f381fSJeff Kirsher #define MACB_RXUBR_SIZE 1
3975c2fa0f6SXander Huff #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
3989f2f381fSJeff Kirsher #define MACB_TXUBR_SIZE 1
3996f79eed8SXander Huff #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
4009f2f381fSJeff Kirsher #define MACB_ISR_TUND_SIZE 1
4016f79eed8SXander Huff #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
4029f2f381fSJeff Kirsher #define MACB_ISR_RLE_SIZE 1
4036f79eed8SXander Huff #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
4049f2f381fSJeff Kirsher #define MACB_TXERR_SIZE 1
405fa6031dfSWilly Tarreau #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
406fa6031dfSWilly Tarreau #define MACB_RM9200_TBRE_SIZE 1
4076f79eed8SXander Huff #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
4089f2f381fSJeff Kirsher #define MACB_TCOMP_SIZE 1
4096f79eed8SXander Huff #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
4109f2f381fSJeff Kirsher #define MACB_ISR_LINK_SIZE 1
4116f79eed8SXander Huff #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
4129f2f381fSJeff Kirsher #define MACB_ISR_ROVR_SIZE 1
4136f79eed8SXander Huff #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
4149f2f381fSJeff Kirsher #define MACB_HRESP_SIZE 1
4156f79eed8SXander Huff #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
4169f2f381fSJeff Kirsher #define MACB_PFR_SIZE 1
4176f79eed8SXander Huff #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
4189f2f381fSJeff Kirsher #define MACB_PTZ_SIZE 1
4193e2a5e15SSergio Prado #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
4203e2a5e15SSergio Prado #define MACB_WOL_SIZE 1
421c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
422c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFR_SIZE 1
423c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
424c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFR_SIZE 1
425c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
426c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFT_SIZE 1
427c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
428c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFT_SIZE 1
429c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
430c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFR_SIZE 1
431c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
432c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFR_SIZE 1
433c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
434c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFT_SIZE 1
435c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
436c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFT_SIZE 1
437c2594d80SAndrei.Pistirica@microchip.com #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
438c2594d80SAndrei.Pistirica@microchip.com #define MACB_SRI_SIZE 1
439558e35ccSNicolas Ferre #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
440558e35ccSNicolas Ferre #define GEM_WOL_SIZE 1
441c2594d80SAndrei.Pistirica@microchip.com
442c2594d80SAndrei.Pistirica@microchip.com /* Timer increment fields */
443c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_CNS_OFFSET 0
444c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_CNS_SIZE 8
445c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_ACNS_OFFSET 8
446c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_ACNS_SIZE 8
447c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_NIT_OFFSET 16
448c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_NIT_SIZE 8
4499f2f381fSJeff Kirsher
4509f2f381fSJeff Kirsher /* Bitfields in MAN */
4515c2fa0f6SXander Huff #define MACB_DATA_OFFSET 0 /* data */
4529f2f381fSJeff Kirsher #define MACB_DATA_SIZE 16
4535c2fa0f6SXander Huff #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
4549f2f381fSJeff Kirsher #define MACB_CODE_SIZE 2
4555c2fa0f6SXander Huff #define MACB_REGA_OFFSET 18 /* Register address */
4569f2f381fSJeff Kirsher #define MACB_REGA_SIZE 5
4575c2fa0f6SXander Huff #define MACB_PHYA_OFFSET 23 /* PHY address */
4589f2f381fSJeff Kirsher #define MACB_PHYA_SIZE 5
4596f79eed8SXander Huff #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
4609f2f381fSJeff Kirsher #define MACB_RW_SIZE 2
4616f79eed8SXander Huff #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
4629f2f381fSJeff Kirsher #define MACB_SOF_SIZE 2
4639f2f381fSJeff Kirsher
4649f2f381fSJeff Kirsher /* Bitfields in USRIO (AVR32) */
4659f2f381fSJeff Kirsher #define MACB_MII_OFFSET 0
4669f2f381fSJeff Kirsher #define MACB_MII_SIZE 1
4679f2f381fSJeff Kirsher #define MACB_EAM_OFFSET 1
4689f2f381fSJeff Kirsher #define MACB_EAM_SIZE 1
4699f2f381fSJeff Kirsher #define MACB_TX_PAUSE_OFFSET 2
4709f2f381fSJeff Kirsher #define MACB_TX_PAUSE_SIZE 1
4719f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_OFFSET 3
4729f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_SIZE 1
4739f2f381fSJeff Kirsher
4749f2f381fSJeff Kirsher /* Bitfields in USRIO (AT91) */
4759f2f381fSJeff Kirsher #define MACB_RMII_OFFSET 0
4769f2f381fSJeff Kirsher #define MACB_RMII_SIZE 1
477140b7552SPatrice Vilchez #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
478140b7552SPatrice Vilchez #define GEM_RGMII_SIZE 1
4799f2f381fSJeff Kirsher #define MACB_CLKEN_OFFSET 1
4809f2f381fSJeff Kirsher #define MACB_CLKEN_SIZE 1
4819f2f381fSJeff Kirsher
4829f2f381fSJeff Kirsher /* Bitfields in WOL */
4839f2f381fSJeff Kirsher #define MACB_IP_OFFSET 0
4849f2f381fSJeff Kirsher #define MACB_IP_SIZE 16
4859f2f381fSJeff Kirsher #define MACB_MAG_OFFSET 16
4869f2f381fSJeff Kirsher #define MACB_MAG_SIZE 1
4879f2f381fSJeff Kirsher #define MACB_ARP_OFFSET 17
4889f2f381fSJeff Kirsher #define MACB_ARP_SIZE 1
4899f2f381fSJeff Kirsher #define MACB_SA1_OFFSET 18
4909f2f381fSJeff Kirsher #define MACB_SA1_SIZE 1
4919f2f381fSJeff Kirsher #define MACB_WOL_MTI_OFFSET 19
4929f2f381fSJeff Kirsher #define MACB_WOL_MTI_SIZE 1
4939f2f381fSJeff Kirsher
494f75ba50bSJamie Iles /* Bitfields in MID */
495f75ba50bSJamie Iles #define MACB_IDNUM_OFFSET 16
496d941bebfSPunnaiah Choudary Kalluri #define MACB_IDNUM_SIZE 12
497f75ba50bSJamie Iles #define MACB_REV_OFFSET 0
498f75ba50bSJamie Iles #define MACB_REV_SIZE 16
499f75ba50bSJamie Iles
500e4e143e2SParshuram Thombare /* Bitfield in HS_MAC_CONFIG */
501e4e143e2SParshuram Thombare #define GEM_HS_MAC_SPEED_OFFSET 0
502e4e143e2SParshuram Thombare #define GEM_HS_MAC_SPEED_SIZE 3
503e4e143e2SParshuram Thombare
504e276e5e4SRobert Hancock /* Bitfields in PCSCNTRL */
505e276e5e4SRobert Hancock #define GEM_PCSAUTONEG_OFFSET 12
506e276e5e4SRobert Hancock #define GEM_PCSAUTONEG_SIZE 1
507e276e5e4SRobert Hancock
508757a03c6SJamie Iles /* Bitfields in DCFG1. */
509581df9e1SNicolas Ferre #define GEM_IRQCOR_OFFSET 23
510581df9e1SNicolas Ferre #define GEM_IRQCOR_SIZE 1
511757a03c6SJamie Iles #define GEM_DBWDEF_OFFSET 25
512757a03c6SJamie Iles #define GEM_DBWDEF_SIZE 3
513e4e143e2SParshuram Thombare #define GEM_NO_PCS_OFFSET 0
514e4e143e2SParshuram Thombare #define GEM_NO_PCS_SIZE 1
515757a03c6SJamie Iles
516e175587fSNicolas Ferre /* Bitfields in DCFG2. */
517e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_OFFSET 20
518e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_SIZE 1
519e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_OFFSET 21
520e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_SIZE 1
521e175587fSNicolas Ferre
522cae4bc06SMaulik Jodhani #define GEM_RX_PBUF_ADDR_OFFSET 22
523cae4bc06SMaulik Jodhani #define GEM_RX_PBUF_ADDR_SIZE 4
5247b429614SRafal Ozieblo
5257b429614SRafal Ozieblo /* Bitfields in DCFG5. */
5267b429614SRafal Ozieblo #define GEM_TSU_OFFSET 8
5277b429614SRafal Ozieblo #define GEM_TSU_SIZE 1
5287b429614SRafal Ozieblo
5291629dd4fSRafal Ozieblo /* Bitfields in DCFG6. */
5301629dd4fSRafal Ozieblo #define GEM_PBUF_LSO_OFFSET 27
5311629dd4fSRafal Ozieblo #define GEM_PBUF_LSO_SIZE 1
532cae4bc06SMaulik Jodhani #define GEM_PBUF_CUTTHRU_OFFSET 25
533cae4bc06SMaulik Jodhani #define GEM_PBUF_CUTTHRU_SIZE 1
534dc97a89eSRafal Ozieblo #define GEM_DAW64_OFFSET 23
535dc97a89eSRafal Ozieblo #define GEM_DAW64_SIZE 1
5361629dd4fSRafal Ozieblo
537ae8223deSRafal Ozieblo /* Bitfields in DCFG8. */
538ae8223deSRafal Ozieblo #define GEM_T1SCR_OFFSET 24
539ae8223deSRafal Ozieblo #define GEM_T1SCR_SIZE 8
540ae8223deSRafal Ozieblo #define GEM_T2SCR_OFFSET 16
541ae8223deSRafal Ozieblo #define GEM_T2SCR_SIZE 8
542ae8223deSRafal Ozieblo #define GEM_SCR2ETH_OFFSET 8
543ae8223deSRafal Ozieblo #define GEM_SCR2ETH_SIZE 8
544ae8223deSRafal Ozieblo #define GEM_SCR2CMP_OFFSET 0
545ae8223deSRafal Ozieblo #define GEM_SCR2CMP_SIZE 8
546ae8223deSRafal Ozieblo
547404cd086SHarini Katakam /* Bitfields in DCFG10 */
548404cd086SHarini Katakam #define GEM_TXBD_RDBUFF_OFFSET 12
549404cd086SHarini Katakam #define GEM_TXBD_RDBUFF_SIZE 4
550404cd086SHarini Katakam #define GEM_RXBD_RDBUFF_OFFSET 8
551404cd086SHarini Katakam #define GEM_RXBD_RDBUFF_SIZE 4
552404cd086SHarini Katakam
553e4e143e2SParshuram Thombare /* Bitfields in DCFG12. */
554e4e143e2SParshuram Thombare #define GEM_HIGH_SPEED_OFFSET 26
555e4e143e2SParshuram Thombare #define GEM_HIGH_SPEED_SIZE 1
556e4e143e2SParshuram Thombare
557e4e143e2SParshuram Thombare /* Bitfields in USX_CONTROL. */
558e4e143e2SParshuram Thombare #define GEM_USX_CTRL_SPEED_OFFSET 14
559e4e143e2SParshuram Thombare #define GEM_USX_CTRL_SPEED_SIZE 3
560e4e143e2SParshuram Thombare #define GEM_SERDES_RATE_OFFSET 12
561e4e143e2SParshuram Thombare #define GEM_SERDES_RATE_SIZE 2
562e4e143e2SParshuram Thombare #define GEM_RX_SCR_BYPASS_OFFSET 9
563e4e143e2SParshuram Thombare #define GEM_RX_SCR_BYPASS_SIZE 1
564e4e143e2SParshuram Thombare #define GEM_TX_SCR_BYPASS_OFFSET 8
565e4e143e2SParshuram Thombare #define GEM_TX_SCR_BYPASS_SIZE 1
566e4e143e2SParshuram Thombare #define GEM_TX_EN_OFFSET 1
567e4e143e2SParshuram Thombare #define GEM_TX_EN_SIZE 1
568e4e143e2SParshuram Thombare #define GEM_SIGNAL_OK_OFFSET 0
569e4e143e2SParshuram Thombare #define GEM_SIGNAL_OK_SIZE 1
570e4e143e2SParshuram Thombare
571e4e143e2SParshuram Thombare /* Bitfields in USX_STATUS. */
572e4e143e2SParshuram Thombare #define GEM_USX_BLOCK_LOCK_OFFSET 0
573e4e143e2SParshuram Thombare #define GEM_USX_BLOCK_LOCK_SIZE 1
574e4e143e2SParshuram Thombare
575c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in TISUBN */
576c2594d80SAndrei.Pistirica@microchip.com #define GEM_SUBNSINCR_OFFSET 0
5777ad342bcSHarini Katakam #define GEM_SUBNSINCRL_OFFSET 24
5787ad342bcSHarini Katakam #define GEM_SUBNSINCRL_SIZE 8
5797ad342bcSHarini Katakam #define GEM_SUBNSINCRH_OFFSET 0
5807ad342bcSHarini Katakam #define GEM_SUBNSINCRH_SIZE 16
5817ad342bcSHarini Katakam #define GEM_SUBNSINCR_SIZE 24
582c2594d80SAndrei.Pistirica@microchip.com
583c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in TI */
584c2594d80SAndrei.Pistirica@microchip.com #define GEM_NSINCR_OFFSET 0
585c2594d80SAndrei.Pistirica@microchip.com #define GEM_NSINCR_SIZE 8
586c2594d80SAndrei.Pistirica@microchip.com
587ab91f0a9SRafal Ozieblo /* Bitfields in TSH */
588ab91f0a9SRafal Ozieblo #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
589ab91f0a9SRafal Ozieblo #define GEM_TSH_SIZE 16
590ab91f0a9SRafal Ozieblo
591ab91f0a9SRafal Ozieblo /* Bitfields in TSL */
592ab91f0a9SRafal Ozieblo #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
593ab91f0a9SRafal Ozieblo #define GEM_TSL_SIZE 32
594ab91f0a9SRafal Ozieblo
595ab91f0a9SRafal Ozieblo /* Bitfields in TN */
596ab91f0a9SRafal Ozieblo #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
597ab91f0a9SRafal Ozieblo #define GEM_TN_SIZE 30
598ab91f0a9SRafal Ozieblo
599ab91f0a9SRafal Ozieblo /* Bitfields in TXBDCTRL */
600ab91f0a9SRafal Ozieblo #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
601ab91f0a9SRafal Ozieblo #define GEM_TXTSMODE_SIZE 2
602ab91f0a9SRafal Ozieblo
603ab91f0a9SRafal Ozieblo /* Bitfields in RXBDCTRL */
604ab91f0a9SRafal Ozieblo #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
605ab91f0a9SRafal Ozieblo #define GEM_RXTSMODE_SIZE 2
606ab91f0a9SRafal Ozieblo
607ae8223deSRafal Ozieblo /* Bitfields in SCRT2 */
608ae8223deSRafal Ozieblo #define GEM_QUEUE_OFFSET 0 /* Queue Number */
609ae8223deSRafal Ozieblo #define GEM_QUEUE_SIZE 4
610ae8223deSRafal Ozieblo #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
611ae8223deSRafal Ozieblo #define GEM_VLANPR_SIZE 3
612ae8223deSRafal Ozieblo #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
613ae8223deSRafal Ozieblo #define GEM_VLANEN_SIZE 1
614ae8223deSRafal Ozieblo #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
615ae8223deSRafal Ozieblo #define GEM_ETHT2IDX_SIZE 3
616ae8223deSRafal Ozieblo #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
617ae8223deSRafal Ozieblo #define GEM_ETHTEN_SIZE 1
618ae8223deSRafal Ozieblo #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
619ae8223deSRafal Ozieblo #define GEM_CMPA_SIZE 5
620ae8223deSRafal Ozieblo #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
621ae8223deSRafal Ozieblo #define GEM_CMPAEN_SIZE 1
622ae8223deSRafal Ozieblo #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
623ae8223deSRafal Ozieblo #define GEM_CMPB_SIZE 5
624ae8223deSRafal Ozieblo #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
625ae8223deSRafal Ozieblo #define GEM_CMPBEN_SIZE 1
626ae8223deSRafal Ozieblo #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
627ae8223deSRafal Ozieblo #define GEM_CMPC_SIZE 5
628ae8223deSRafal Ozieblo #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
629ae8223deSRafal Ozieblo #define GEM_CMPCEN_SIZE 1
630ae8223deSRafal Ozieblo
631ae8223deSRafal Ozieblo /* Bitfields in ETHT */
632ae8223deSRafal Ozieblo #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
633ae8223deSRafal Ozieblo #define GEM_ETHTCMP_SIZE 16
634ae8223deSRafal Ozieblo
635ae8223deSRafal Ozieblo /* Bitfields in T2CMPW0 */
636ae8223deSRafal Ozieblo #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
637ae8223deSRafal Ozieblo #define GEM_T2CMP_SIZE 16
638ae8223deSRafal Ozieblo #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
639ae8223deSRafal Ozieblo #define GEM_T2MASK_SIZE 16
640ae8223deSRafal Ozieblo
641ae8223deSRafal Ozieblo /* Bitfields in T2CMPW1 */
642ae8223deSRafal Ozieblo #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
643ae8223deSRafal Ozieblo #define GEM_T2DISMSK_SIZE 1
644ae8223deSRafal Ozieblo #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
645ae8223deSRafal Ozieblo #define GEM_T2CMPOFST_SIZE 2
646ae8223deSRafal Ozieblo #define GEM_T2OFST_OFFSET 0 /* offset value */
647ae8223deSRafal Ozieblo #define GEM_T2OFST_SIZE 7
648ae8223deSRafal Ozieblo
649759cc793SVineeth Karumanchi /* Bitfields in queue pointer registers */
650759cc793SVineeth Karumanchi #define MACB_QUEUE_DISABLE_OFFSET 0 /* disable queue */
651759cc793SVineeth Karumanchi #define MACB_QUEUE_DISABLE_SIZE 1
652759cc793SVineeth Karumanchi
653ae8223deSRafal Ozieblo /* Offset for screener type 2 compare values (T2CMPOFST).
654ae8223deSRafal Ozieblo * Note the offset is applied after the specified point,
655ae8223deSRafal Ozieblo * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
656ae8223deSRafal Ozieblo * of 12 bytes from this would be the source IP address in an IP header
657ae8223deSRafal Ozieblo */
658ae8223deSRafal Ozieblo #define GEM_T2COMPOFST_SOF 0
659ae8223deSRafal Ozieblo #define GEM_T2COMPOFST_ETYPE 1
660ae8223deSRafal Ozieblo #define GEM_T2COMPOFST_IPHDR 2
661ae8223deSRafal Ozieblo #define GEM_T2COMPOFST_TCPUDP 3
662ae8223deSRafal Ozieblo
663ae8223deSRafal Ozieblo /* offset from EtherType to IP address */
664ae8223deSRafal Ozieblo #define ETYPE_SRCIP_OFFSET 12
665ae8223deSRafal Ozieblo #define ETYPE_DSTIP_OFFSET 16
666ae8223deSRafal Ozieblo
667ae8223deSRafal Ozieblo /* offset from IP header to port */
668ae8223deSRafal Ozieblo #define IPHDR_SRCPORT_OFFSET 0
669ae8223deSRafal Ozieblo #define IPHDR_DSTPORT_OFFSET 2
670ae8223deSRafal Ozieblo
671ab91f0a9SRafal Ozieblo /* Transmit DMA buffer descriptor Word 1 */
672ab91f0a9SRafal Ozieblo #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
673ab91f0a9SRafal Ozieblo #define GEM_DMA_TXVALID_SIZE 1
674ab91f0a9SRafal Ozieblo
675ab91f0a9SRafal Ozieblo /* Receive DMA buffer descriptor Word 0 */
676ab91f0a9SRafal Ozieblo #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
677ab91f0a9SRafal Ozieblo #define GEM_DMA_RXVALID_SIZE 1
678ab91f0a9SRafal Ozieblo
679ab91f0a9SRafal Ozieblo /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
680ab91f0a9SRafal Ozieblo #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
681ab91f0a9SRafal Ozieblo #define GEM_DMA_SECL_SIZE 2
682ab91f0a9SRafal Ozieblo #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
683ab91f0a9SRafal Ozieblo #define GEM_DMA_NSEC_SIZE 30
684ab91f0a9SRafal Ozieblo
685ab91f0a9SRafal Ozieblo /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
686ab91f0a9SRafal Ozieblo
687ab91f0a9SRafal Ozieblo /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
688ab91f0a9SRafal Ozieblo * Old hardware supports only 6 bit precision but it is enough for PTP.
689ab91f0a9SRafal Ozieblo * Less accuracy is used always instead of checking hardware version.
690ab91f0a9SRafal Ozieblo */
691ab91f0a9SRafal Ozieblo #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
692ab91f0a9SRafal Ozieblo #define GEM_DMA_SECH_SIZE 4
693ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
694ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
695ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
696ab91f0a9SRafal Ozieblo
697c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in ADJ */
698c2594d80SAndrei.Pistirica@microchip.com #define GEM_ADDSUB_OFFSET 31
699c2594d80SAndrei.Pistirica@microchip.com #define GEM_ADDSUB_SIZE 1
7009f2f381fSJeff Kirsher /* Constants for CLK */
7019f2f381fSJeff Kirsher #define MACB_CLK_DIV8 0
7029f2f381fSJeff Kirsher #define MACB_CLK_DIV16 1
7039f2f381fSJeff Kirsher #define MACB_CLK_DIV32 2
7049f2f381fSJeff Kirsher #define MACB_CLK_DIV64 3
7059f2f381fSJeff Kirsher
70670c9f3d4SJamie Iles /* GEM specific constants for CLK. */
70770c9f3d4SJamie Iles #define GEM_CLK_DIV8 0
70870c9f3d4SJamie Iles #define GEM_CLK_DIV16 1
70970c9f3d4SJamie Iles #define GEM_CLK_DIV32 2
71070c9f3d4SJamie Iles #define GEM_CLK_DIV48 3
71170c9f3d4SJamie Iles #define GEM_CLK_DIV64 4
71270c9f3d4SJamie Iles #define GEM_CLK_DIV96 5
713b31587feSBartosz Wawrzyniak #define GEM_CLK_DIV128 6
714b31587feSBartosz Wawrzyniak #define GEM_CLK_DIV224 7
71570c9f3d4SJamie Iles
7169f2f381fSJeff Kirsher /* Constants for MAN register */
71743ad352dSMilind Parab #define MACB_MAN_C22_SOF 1
71843ad352dSMilind Parab #define MACB_MAN_C22_WRITE 1
71943ad352dSMilind Parab #define MACB_MAN_C22_READ 2
72043ad352dSMilind Parab #define MACB_MAN_C22_CODE 2
72143ad352dSMilind Parab
72243ad352dSMilind Parab #define MACB_MAN_C45_SOF 0
72343ad352dSMilind Parab #define MACB_MAN_C45_ADDR 0
72443ad352dSMilind Parab #define MACB_MAN_C45_WRITE 1
72543ad352dSMilind Parab #define MACB_MAN_C45_POST_READ_INCR 2
72643ad352dSMilind Parab #define MACB_MAN_C45_READ 3
72743ad352dSMilind Parab #define MACB_MAN_C45_CODE 2
7289f2f381fSJeff Kirsher
729581df9e1SNicolas Ferre /* Capability mask bits */
730e175587fSNicolas Ferre #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
731a8487489SBoris BREZILLON #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
7326bdaa5e9SNicolas Ferre #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
733222ca8e0SNathan Sullivan #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
734ce721a70SNeil Armstrong #define MACB_CAPS_USRIO_DISABLED 0x00000010
735c5181895SHarini Katakam #define MACB_CAPS_JUMBO 0x00000020
736c2594d80SAndrei.Pistirica@microchip.com #define MACB_CAPS_GEM_HAS_PTP 0x00000040
737404cd086SHarini Katakam #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
738e501070eSHarini Katakam #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
7391a9b5a26SClaudiu Beznea #define MACB_CAPS_MIIONRGMII 0x00000200
7408a1c9753SHarini Katakam #define MACB_CAPS_NEED_TSUCLK 0x00000400
741759cc793SVineeth Karumanchi #define MACB_CAPS_QUEUE_DISABLE 0x00000800
7421d3ded64SHarini Katakam #define MACB_CAPS_PCS 0x01000000
7431d3ded64SHarini Katakam #define MACB_CAPS_HIGH_SPEED 0x02000000
744daafa1d3SClaudiu Beznea #define MACB_CAPS_CLK_HW_CHG 0x04000000
745ac2fcfa9SAlexandre Belloni #define MACB_CAPS_MACB_IS_EMAC 0x08000000
746e175587fSNicolas Ferre #define MACB_CAPS_FIFO_MODE 0x10000000
747e175587fSNicolas Ferre #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
748a4c35ed3SCyrille Pitchen #define MACB_CAPS_SG_DISABLED 0x40000000
749e175587fSNicolas Ferre #define MACB_CAPS_MACB_IS_GEM 0x80000000
750581df9e1SNicolas Ferre
7511629dd4fSRafal Ozieblo /* LSO settings */
7521629dd4fSRafal Ozieblo #define MACB_LSO_UFO_ENABLE 0x01
7531629dd4fSRafal Ozieblo #define MACB_LSO_TSO_ENABLE 0x02
7541629dd4fSRafal Ozieblo
7559f2f381fSJeff Kirsher /* Bit manipulation macros */
7569f2f381fSJeff Kirsher #define MACB_BIT(name) \
7579f2f381fSJeff Kirsher (1 << MACB_##name##_OFFSET)
7589f2f381fSJeff Kirsher #define MACB_BF(name,value) \
7599f2f381fSJeff Kirsher (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
7609f2f381fSJeff Kirsher << MACB_##name##_OFFSET)
7619f2f381fSJeff Kirsher #define MACB_BFEXT(name,value)\
7629f2f381fSJeff Kirsher (((value) >> MACB_##name##_OFFSET) \
7639f2f381fSJeff Kirsher & ((1 << MACB_##name##_SIZE) - 1))
7649f2f381fSJeff Kirsher #define MACB_BFINS(name,value,old) \
7659f2f381fSJeff Kirsher (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
7669f2f381fSJeff Kirsher << MACB_##name##_OFFSET)) \
7679f2f381fSJeff Kirsher | MACB_BF(name,value))
7689f2f381fSJeff Kirsher
769f75ba50bSJamie Iles #define GEM_BIT(name) \
770f75ba50bSJamie Iles (1 << GEM_##name##_OFFSET)
771f75ba50bSJamie Iles #define GEM_BF(name, value) \
772f75ba50bSJamie Iles (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
773f75ba50bSJamie Iles << GEM_##name##_OFFSET)
774f75ba50bSJamie Iles #define GEM_BFEXT(name, value)\
775f75ba50bSJamie Iles (((value) >> GEM_##name##_OFFSET) \
776f75ba50bSJamie Iles & ((1 << GEM_##name##_SIZE) - 1))
777f75ba50bSJamie Iles #define GEM_BFINS(name, value, old) \
778f75ba50bSJamie Iles (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
779f75ba50bSJamie Iles << GEM_##name##_OFFSET)) \
780f75ba50bSJamie Iles | GEM_BF(name, value))
781f75ba50bSJamie Iles
7829f2f381fSJeff Kirsher /* Register access macros */
7837a6e0706SDavid S. Miller #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
7847a6e0706SDavid S. Miller #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
7857a6e0706SDavid S. Miller #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
7867a6e0706SDavid S. Miller #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
7877a6e0706SDavid S. Miller #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
7887a6e0706SDavid S. Miller #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
789ae8223deSRafal Ozieblo #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
790ae8223deSRafal Ozieblo #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
791f75ba50bSJamie Iles
7926f79eed8SXander Huff /* Conditional GEM/MACB macros. These perform the operation to the correct
793f75ba50bSJamie Iles * register dependent on whether the device is a GEM or a MACB. For registers
794f75ba50bSJamie Iles * and bitfields that are common across both devices, use macb_{read,write}l
795f75ba50bSJamie Iles * to avoid the cost of the conditional.
796f75ba50bSJamie Iles */
797f75ba50bSJamie Iles #define macb_or_gem_writel(__bp, __reg, __value) \
798f75ba50bSJamie Iles ({ \
799f75ba50bSJamie Iles if (macb_is_gem((__bp))) \
800f75ba50bSJamie Iles gem_writel((__bp), __reg, __value); \
801f75ba50bSJamie Iles else \
802f75ba50bSJamie Iles macb_writel((__bp), __reg, __value); \
803f75ba50bSJamie Iles })
804f75ba50bSJamie Iles
805f75ba50bSJamie Iles #define macb_or_gem_readl(__bp, __reg) \
806f75ba50bSJamie Iles ({ \
807f75ba50bSJamie Iles u32 __v; \
808f75ba50bSJamie Iles if (macb_is_gem((__bp))) \
809f75ba50bSJamie Iles __v = gem_readl((__bp), __reg); \
810f75ba50bSJamie Iles else \
811f75ba50bSJamie Iles __v = macb_readl((__bp), __reg); \
812f75ba50bSJamie Iles __v; \
813f75ba50bSJamie Iles })
8149f2f381fSJeff Kirsher
8158beb79b7SHarini Katakam #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
8168beb79b7SHarini Katakam
8176f79eed8SXander Huff /* struct macb_dma_desc - Hardware DMA descriptor
81855054a16SHavard Skinnemoen * @addr: DMA address of data buffer
81955054a16SHavard Skinnemoen * @ctrl: Control and status bits
82055054a16SHavard Skinnemoen */
82155054a16SHavard Skinnemoen struct macb_dma_desc {
8229f2f381fSJeff Kirsher u32 addr;
8239f2f381fSJeff Kirsher u32 ctrl;
824dc97a89eSRafal Ozieblo };
825dc97a89eSRafal Ozieblo
8267b429614SRafal Ozieblo #ifdef MACB_EXT_DESC
8277b429614SRafal Ozieblo #define HW_DMA_CAP_32B 0
8287b429614SRafal Ozieblo #define HW_DMA_CAP_64B (1 << 0)
8297b429614SRafal Ozieblo #define HW_DMA_CAP_PTP (1 << 1)
8307b429614SRafal Ozieblo #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
831dc97a89eSRafal Ozieblo
832dc97a89eSRafal Ozieblo struct macb_dma_desc_64 {
833fff8019aSHarini Katakam u32 addrh;
834fff8019aSHarini Katakam u32 resvd;
8359f2f381fSJeff Kirsher };
8367b429614SRafal Ozieblo
8377b429614SRafal Ozieblo struct macb_dma_desc_ptp {
8387b429614SRafal Ozieblo u32 ts_1;
8397b429614SRafal Ozieblo u32 ts_2;
8407b429614SRafal Ozieblo };
841dc97a89eSRafal Ozieblo #endif
8429f2f381fSJeff Kirsher
8439f2f381fSJeff Kirsher /* DMA descriptor bitfields */
8449f2f381fSJeff Kirsher #define MACB_RX_USED_OFFSET 0
8459f2f381fSJeff Kirsher #define MACB_RX_USED_SIZE 1
8469f2f381fSJeff Kirsher #define MACB_RX_WRAP_OFFSET 1
8479f2f381fSJeff Kirsher #define MACB_RX_WRAP_SIZE 1
8489f2f381fSJeff Kirsher #define MACB_RX_WADDR_OFFSET 2
8499f2f381fSJeff Kirsher #define MACB_RX_WADDR_SIZE 30
8509f2f381fSJeff Kirsher
8519f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_OFFSET 0
8529f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_SIZE 12
8539f2f381fSJeff Kirsher #define MACB_RX_OFFSET_OFFSET 12
8549f2f381fSJeff Kirsher #define MACB_RX_OFFSET_SIZE 2
8559f2f381fSJeff Kirsher #define MACB_RX_SOF_OFFSET 14
8569f2f381fSJeff Kirsher #define MACB_RX_SOF_SIZE 1
8579f2f381fSJeff Kirsher #define MACB_RX_EOF_OFFSET 15
8589f2f381fSJeff Kirsher #define MACB_RX_EOF_SIZE 1
8599f2f381fSJeff Kirsher #define MACB_RX_CFI_OFFSET 16
8609f2f381fSJeff Kirsher #define MACB_RX_CFI_SIZE 1
8619f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_OFFSET 17
8629f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_SIZE 3
8639f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_OFFSET 20
8649f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_SIZE 1
8659f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_OFFSET 21
8669f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_SIZE 1
8679f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_OFFSET 22
8689f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_SIZE 1
8699f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_OFFSET 23
8709f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_SIZE 1
8719f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_OFFSET 24
8729f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_SIZE 1
8739f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_OFFSET 25
8749f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_SIZE 1
8759f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_OFFSET 26
8769f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_SIZE 1
8779f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_OFFSET 28
8789f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_SIZE 1
8799f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_OFFSET 29
8809f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_SIZE 1
8819f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_OFFSET 30
8829f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_SIZE 1
8839f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_OFFSET 31
8849f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_SIZE 1
8859f2f381fSJeff Kirsher
88698b5a0f4SHarini Katakam #define MACB_RX_FRMLEN_MASK 0xFFF
88798b5a0f4SHarini Katakam #define MACB_RX_JFRMLEN_MASK 0x3FFF
88898b5a0f4SHarini Katakam
889924ec53cSCyrille Pitchen /* RX checksum offload disabled: bit 24 clear in NCFGR */
890924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_OFFSET 22
891924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_SIZE 2
892924ec53cSCyrille Pitchen
893924ec53cSCyrille Pitchen /* RX checksum offload enabled: bit 24 set in NCFGR */
894924ec53cSCyrille Pitchen #define GEM_RX_CSUM_OFFSET 22
895924ec53cSCyrille Pitchen #define GEM_RX_CSUM_SIZE 2
896924ec53cSCyrille Pitchen
8979f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_OFFSET 0
8989f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_SIZE 11
8999f2f381fSJeff Kirsher #define MACB_TX_LAST_OFFSET 15
9009f2f381fSJeff Kirsher #define MACB_TX_LAST_SIZE 1
9019f2f381fSJeff Kirsher #define MACB_TX_NOCRC_OFFSET 16
9029f2f381fSJeff Kirsher #define MACB_TX_NOCRC_SIZE 1
9031629dd4fSRafal Ozieblo #define MACB_MSS_MFS_OFFSET 16
9041629dd4fSRafal Ozieblo #define MACB_MSS_MFS_SIZE 14
9051629dd4fSRafal Ozieblo #define MACB_TX_LSO_OFFSET 17
9061629dd4fSRafal Ozieblo #define MACB_TX_LSO_SIZE 2
9071629dd4fSRafal Ozieblo #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
9081629dd4fSRafal Ozieblo #define MACB_TX_TCP_SEQ_SRC_SIZE 1
9099f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
9109f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_SIZE 1
9119f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_OFFSET 28
9129f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_SIZE 1
9139f2f381fSJeff Kirsher #define MACB_TX_ERROR_OFFSET 29
9149f2f381fSJeff Kirsher #define MACB_TX_ERROR_SIZE 1
9159f2f381fSJeff Kirsher #define MACB_TX_WRAP_OFFSET 30
9169f2f381fSJeff Kirsher #define MACB_TX_WRAP_SIZE 1
9179f2f381fSJeff Kirsher #define MACB_TX_USED_OFFSET 31
9189f2f381fSJeff Kirsher #define MACB_TX_USED_SIZE 1
9199f2f381fSJeff Kirsher
920a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_OFFSET 0
921a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_SIZE 14
922a4c35ed3SCyrille Pitchen
923924ec53cSCyrille Pitchen /* Buffer descriptor constants */
924924ec53cSCyrille Pitchen #define GEM_RX_CSUM_NONE 0
925924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_ONLY 1
926924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_TCP 2
927924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_UDP 3
928924ec53cSCyrille Pitchen
929924ec53cSCyrille Pitchen /* limit RX checksum offload to TCP and UDP packets */
930924ec53cSCyrille Pitchen #define GEM_RX_CSUM_CHECKED_MASK 2
931924ec53cSCyrille Pitchen
932a8ee4dc1SHarini Katakam /* Scaled PPM fraction */
933a8ee4dc1SHarini Katakam #define PPM_FRACTION 16
934a8ee4dc1SHarini Katakam
9356f79eed8SXander Huff /* struct macb_tx_skb - data about an skb which is being transmitted
936a4c35ed3SCyrille Pitchen * @skb: skb currently being transmitted, only set for the last buffer
937a4c35ed3SCyrille Pitchen * of the frame
938a4c35ed3SCyrille Pitchen * @mapping: DMA address of the skb's fragment buffer
939a4c35ed3SCyrille Pitchen * @size: size of the DMA mapped buffer
940a4c35ed3SCyrille Pitchen * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
941a4c35ed3SCyrille Pitchen * false when buffer was mapped with dma_map_single()
94255054a16SHavard Skinnemoen */
94355054a16SHavard Skinnemoen struct macb_tx_skb {
9449f2f381fSJeff Kirsher struct sk_buff *skb;
9459f2f381fSJeff Kirsher dma_addr_t mapping;
946a4c35ed3SCyrille Pitchen size_t size;
947a4c35ed3SCyrille Pitchen bool mapped_as_page;
9489f2f381fSJeff Kirsher };
9499f2f381fSJeff Kirsher
9506f79eed8SXander Huff /* Hardware-collected statistics. Used when updating the network
9519f2f381fSJeff Kirsher * device stats by a periodic timer.
9529f2f381fSJeff Kirsher */
9539f2f381fSJeff Kirsher struct macb_stats {
9549f2f381fSJeff Kirsher u32 rx_pause_frames;
9559f2f381fSJeff Kirsher u32 tx_ok;
9569f2f381fSJeff Kirsher u32 tx_single_cols;
9579f2f381fSJeff Kirsher u32 tx_multiple_cols;
9589f2f381fSJeff Kirsher u32 rx_ok;
9599f2f381fSJeff Kirsher u32 rx_fcs_errors;
9609f2f381fSJeff Kirsher u32 rx_align_errors;
9619f2f381fSJeff Kirsher u32 tx_deferred;
9629f2f381fSJeff Kirsher u32 tx_late_cols;
9639f2f381fSJeff Kirsher u32 tx_excessive_cols;
9649f2f381fSJeff Kirsher u32 tx_underruns;
9659f2f381fSJeff Kirsher u32 tx_carrier_errors;
9669f2f381fSJeff Kirsher u32 rx_resource_errors;
9679f2f381fSJeff Kirsher u32 rx_overruns;
9689f2f381fSJeff Kirsher u32 rx_symbol_errors;
9699f2f381fSJeff Kirsher u32 rx_oversize_pkts;
9709f2f381fSJeff Kirsher u32 rx_jabbers;
9719f2f381fSJeff Kirsher u32 rx_undersize_pkts;
9729f2f381fSJeff Kirsher u32 sqe_test_errors;
9739f2f381fSJeff Kirsher u32 rx_length_mismatch;
9749f2f381fSJeff Kirsher u32 tx_pause_frames;
9759f2f381fSJeff Kirsher };
9769f2f381fSJeff Kirsher
977a494ed8eSJamie Iles struct gem_stats {
978a494ed8eSJamie Iles u32 tx_octets_31_0;
979a494ed8eSJamie Iles u32 tx_octets_47_32;
980a494ed8eSJamie Iles u32 tx_frames;
981a494ed8eSJamie Iles u32 tx_broadcast_frames;
982a494ed8eSJamie Iles u32 tx_multicast_frames;
983a494ed8eSJamie Iles u32 tx_pause_frames;
984a494ed8eSJamie Iles u32 tx_64_byte_frames;
985a494ed8eSJamie Iles u32 tx_65_127_byte_frames;
986a494ed8eSJamie Iles u32 tx_128_255_byte_frames;
987a494ed8eSJamie Iles u32 tx_256_511_byte_frames;
988a494ed8eSJamie Iles u32 tx_512_1023_byte_frames;
989a494ed8eSJamie Iles u32 tx_1024_1518_byte_frames;
990a494ed8eSJamie Iles u32 tx_greater_than_1518_byte_frames;
991a494ed8eSJamie Iles u32 tx_underrun;
992a494ed8eSJamie Iles u32 tx_single_collision_frames;
993a494ed8eSJamie Iles u32 tx_multiple_collision_frames;
994a494ed8eSJamie Iles u32 tx_excessive_collisions;
995a494ed8eSJamie Iles u32 tx_late_collisions;
996a494ed8eSJamie Iles u32 tx_deferred_frames;
997a494ed8eSJamie Iles u32 tx_carrier_sense_errors;
998a494ed8eSJamie Iles u32 rx_octets_31_0;
999a494ed8eSJamie Iles u32 rx_octets_47_32;
1000a494ed8eSJamie Iles u32 rx_frames;
1001a494ed8eSJamie Iles u32 rx_broadcast_frames;
1002a494ed8eSJamie Iles u32 rx_multicast_frames;
1003a494ed8eSJamie Iles u32 rx_pause_frames;
1004a494ed8eSJamie Iles u32 rx_64_byte_frames;
1005a494ed8eSJamie Iles u32 rx_65_127_byte_frames;
1006a494ed8eSJamie Iles u32 rx_128_255_byte_frames;
1007a494ed8eSJamie Iles u32 rx_256_511_byte_frames;
1008a494ed8eSJamie Iles u32 rx_512_1023_byte_frames;
1009a494ed8eSJamie Iles u32 rx_1024_1518_byte_frames;
1010a494ed8eSJamie Iles u32 rx_greater_than_1518_byte_frames;
1011a494ed8eSJamie Iles u32 rx_undersized_frames;
1012a494ed8eSJamie Iles u32 rx_oversize_frames;
1013a494ed8eSJamie Iles u32 rx_jabbers;
1014a494ed8eSJamie Iles u32 rx_frame_check_sequence_errors;
1015a494ed8eSJamie Iles u32 rx_length_field_frame_errors;
1016a494ed8eSJamie Iles u32 rx_symbol_errors;
1017a494ed8eSJamie Iles u32 rx_alignment_errors;
1018a494ed8eSJamie Iles u32 rx_resource_errors;
1019a494ed8eSJamie Iles u32 rx_overruns;
1020a494ed8eSJamie Iles u32 rx_ip_header_checksum_errors;
1021a494ed8eSJamie Iles u32 rx_tcp_checksum_errors;
1022a494ed8eSJamie Iles u32 rx_udp_checksum_errors;
1023a494ed8eSJamie Iles };
1024a494ed8eSJamie Iles
10253ff13f1cSXander Huff /* Describes the name and offset of an individual statistic register, as
10263ff13f1cSXander Huff * returned by `ethtool -S`. Also describes which net_device_stats statistics
10273ff13f1cSXander Huff * this register should contribute to.
10283ff13f1cSXander Huff */
10293ff13f1cSXander Huff struct gem_statistic {
10303ff13f1cSXander Huff char stat_string[ETH_GSTRING_LEN];
10313ff13f1cSXander Huff int offset;
10323ff13f1cSXander Huff u32 stat_bits;
10333ff13f1cSXander Huff };
10343ff13f1cSXander Huff
10353ff13f1cSXander Huff /* Bitfield defs for net_device_stat statistics */
10363ff13f1cSXander Huff #define GEM_NDS_RXERR_OFFSET 0
10373ff13f1cSXander Huff #define GEM_NDS_RXLENERR_OFFSET 1
10383ff13f1cSXander Huff #define GEM_NDS_RXOVERERR_OFFSET 2
10393ff13f1cSXander Huff #define GEM_NDS_RXCRCERR_OFFSET 3
10403ff13f1cSXander Huff #define GEM_NDS_RXFRAMEERR_OFFSET 4
10413ff13f1cSXander Huff #define GEM_NDS_RXFIFOERR_OFFSET 5
10423ff13f1cSXander Huff #define GEM_NDS_TXERR_OFFSET 6
10433ff13f1cSXander Huff #define GEM_NDS_TXABORTEDERR_OFFSET 7
10443ff13f1cSXander Huff #define GEM_NDS_TXCARRIERERR_OFFSET 8
10453ff13f1cSXander Huff #define GEM_NDS_TXFIFOERR_OFFSET 9
10463ff13f1cSXander Huff #define GEM_NDS_COLLISIONS_OFFSET 10
10473ff13f1cSXander Huff
10483ff13f1cSXander Huff #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
10493ff13f1cSXander Huff #define GEM_STAT_TITLE_BITS(name, title, bits) { \
10503ff13f1cSXander Huff .stat_string = title, \
10513ff13f1cSXander Huff .offset = GEM_##name, \
10523ff13f1cSXander Huff .stat_bits = bits \
10533ff13f1cSXander Huff }
10543ff13f1cSXander Huff
10553ff13f1cSXander Huff /* list of gem statistic registers. The names MUST match the
10563ff13f1cSXander Huff * corresponding GEM_* definitions.
10573ff13f1cSXander Huff */
10583ff13f1cSXander Huff static const struct gem_statistic gem_statistics[] = {
10593ff13f1cSXander Huff GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
10603ff13f1cSXander Huff GEM_STAT_TITLE(TXCNT, "tx_frames"),
10613ff13f1cSXander Huff GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
10623ff13f1cSXander Huff GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
10633ff13f1cSXander Huff GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
10643ff13f1cSXander Huff GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
10653ff13f1cSXander Huff GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
10663ff13f1cSXander Huff GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
10673ff13f1cSXander Huff GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
10683ff13f1cSXander Huff GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
10693ff13f1cSXander Huff GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
10703ff13f1cSXander Huff GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
10713ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
10723ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
10733ff13f1cSXander Huff GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
10743ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
10753ff13f1cSXander Huff GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
10763ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
10773ff13f1cSXander Huff GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
10783ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|
10793ff13f1cSXander Huff GEM_BIT(NDS_TXABORTEDERR)|
10803ff13f1cSXander Huff GEM_BIT(NDS_COLLISIONS)),
10813ff13f1cSXander Huff GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
10823ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
10833ff13f1cSXander Huff GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
10843ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
10853ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
10863ff13f1cSXander Huff GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
10873ff13f1cSXander Huff GEM_STAT_TITLE(RXCNT, "rx_frames"),
10883ff13f1cSXander Huff GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
10893ff13f1cSXander Huff GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
10903ff13f1cSXander Huff GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
10913ff13f1cSXander Huff GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
10923ff13f1cSXander Huff GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
10933ff13f1cSXander Huff GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
10943ff13f1cSXander Huff GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
10953ff13f1cSXander Huff GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
10963ff13f1cSXander Huff GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
10973ff13f1cSXander Huff GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
10983ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
10993ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
11003ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
11013ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
11023ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
11033ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
11043ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
11053ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
11063ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
11073ff13f1cSXander Huff GEM_BIT(NDS_RXERR)),
11083ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
11093ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
11103ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
11113ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
11123ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
11133ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
11143ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
11153ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
11163ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
11173ff13f1cSXander Huff GEM_BIT(NDS_RXERR)),
11183ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
11193ff13f1cSXander Huff GEM_BIT(NDS_RXERR)),
11203ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
11213ff13f1cSXander Huff GEM_BIT(NDS_RXERR)),
11223ff13f1cSXander Huff };
11233ff13f1cSXander Huff
11243ff13f1cSXander Huff #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
11253ff13f1cSXander Huff
1126512286bbSRafal Ozieblo #define QUEUE_STAT_TITLE(title) { \
1127512286bbSRafal Ozieblo .stat_string = title, \
1128512286bbSRafal Ozieblo }
1129512286bbSRafal Ozieblo
1130512286bbSRafal Ozieblo /* per queue statistics, each should be unsigned long type */
1131512286bbSRafal Ozieblo struct queue_stats {
1132512286bbSRafal Ozieblo union {
1133512286bbSRafal Ozieblo unsigned long first;
1134512286bbSRafal Ozieblo unsigned long rx_packets;
1135512286bbSRafal Ozieblo };
1136512286bbSRafal Ozieblo unsigned long rx_bytes;
1137512286bbSRafal Ozieblo unsigned long rx_dropped;
1138512286bbSRafal Ozieblo unsigned long tx_packets;
1139512286bbSRafal Ozieblo unsigned long tx_bytes;
1140512286bbSRafal Ozieblo unsigned long tx_dropped;
1141512286bbSRafal Ozieblo };
1142512286bbSRafal Ozieblo
1143512286bbSRafal Ozieblo static const struct gem_statistic queue_statistics[] = {
1144512286bbSRafal Ozieblo QUEUE_STAT_TITLE("rx_packets"),
1145512286bbSRafal Ozieblo QUEUE_STAT_TITLE("rx_bytes"),
1146512286bbSRafal Ozieblo QUEUE_STAT_TITLE("rx_dropped"),
1147512286bbSRafal Ozieblo QUEUE_STAT_TITLE("tx_packets"),
1148512286bbSRafal Ozieblo QUEUE_STAT_TITLE("tx_bytes"),
1149512286bbSRafal Ozieblo QUEUE_STAT_TITLE("tx_dropped"),
1150512286bbSRafal Ozieblo };
1151512286bbSRafal Ozieblo
1152512286bbSRafal Ozieblo #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1153512286bbSRafal Ozieblo
11544df95131SNicolas Ferre struct macb;
1155ae1f2a56SRafal Ozieblo struct macb_queue;
11564df95131SNicolas Ferre
11574df95131SNicolas Ferre struct macb_or_gem_ops {
11584df95131SNicolas Ferre int (*mog_alloc_rx_buffers)(struct macb *bp);
11594df95131SNicolas Ferre void (*mog_free_rx_buffers)(struct macb *bp);
11604df95131SNicolas Ferre void (*mog_init_rings)(struct macb *bp);
116197236cdaSAntoine Tenart int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
116297236cdaSAntoine Tenart int budget);
11634df95131SNicolas Ferre };
11644df95131SNicolas Ferre
1165c2594d80SAndrei.Pistirica@microchip.com /* MACB-PTP interface: adapt to platform needs. */
1166c2594d80SAndrei.Pistirica@microchip.com struct macb_ptp_info {
1167c2594d80SAndrei.Pistirica@microchip.com void (*ptp_init)(struct net_device *ndev);
1168c2594d80SAndrei.Pistirica@microchip.com void (*ptp_remove)(struct net_device *ndev);
1169c2594d80SAndrei.Pistirica@microchip.com s32 (*get_ptp_max_adj)(void);
1170c2594d80SAndrei.Pistirica@microchip.com unsigned int (*get_tsu_rate)(struct macb *bp);
1171c2594d80SAndrei.Pistirica@microchip.com int (*get_ts_info)(struct net_device *dev,
11722111375bSKory Maincent struct kernel_ethtool_ts_info *info);
1173c2594d80SAndrei.Pistirica@microchip.com int (*get_hwtst)(struct net_device *netdev,
1174202cb220SKory Maincent struct kernel_hwtstamp_config *tstamp_config);
1175c2594d80SAndrei.Pistirica@microchip.com int (*set_hwtst)(struct net_device *netdev,
1176202cb220SKory Maincent struct kernel_hwtstamp_config *tstamp_config,
1177202cb220SKory Maincent struct netlink_ext_ack *extack);
1178c2594d80SAndrei.Pistirica@microchip.com };
1179c2594d80SAndrei.Pistirica@microchip.com
1180c1e85c6cSClaudiu Beznea struct macb_pm_data {
1181c1e85c6cSClaudiu Beznea u32 scrt2;
1182c1e85c6cSClaudiu Beznea u32 usrio;
1183c1e85c6cSClaudiu Beznea };
1184c1e85c6cSClaudiu Beznea
1185edac6386SClaudiu Beznea struct macb_usrio_config {
1186edac6386SClaudiu Beznea u32 mii;
1187edac6386SClaudiu Beznea u32 rmii;
1188edac6386SClaudiu Beznea u32 rgmii;
1189edac6386SClaudiu Beznea u32 refclk;
1190edac6386SClaudiu Beznea u32 hdfctlen;
1191edac6386SClaudiu Beznea };
1192edac6386SClaudiu Beznea
1193e175587fSNicolas Ferre struct macb_config {
1194e175587fSNicolas Ferre u32 caps;
1195e175587fSNicolas Ferre unsigned int dma_burst_length;
1196c69618b3SNicolas Ferre int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1197aead88bdSshubhrajyoti.datta@xilinx.com struct clk **hclk, struct clk **tx_clk,
1198f5473d1dSHarini Katakam struct clk **rx_clk, struct clk **tsu_clk);
1199421d9df0SCyrille Pitchen int (*init)(struct platform_device *pdev);
1200314cf958SDaire McNamara unsigned int max_tx_length;
120198b5a0f4SHarini Katakam int jumbo_max_len;
1202edac6386SClaudiu Beznea const struct macb_usrio_config *usrio;
1203e175587fSNicolas Ferre };
1204e175587fSNicolas Ferre
1205ab91f0a9SRafal Ozieblo struct tsu_incr {
1206ab91f0a9SRafal Ozieblo u32 sub_ns;
1207ab91f0a9SRafal Ozieblo u32 ns;
1208ab91f0a9SRafal Ozieblo };
1209ab91f0a9SRafal Ozieblo
121002c958ddSCyrille Pitchen struct macb_queue {
121102c958ddSCyrille Pitchen struct macb *bp;
121202c958ddSCyrille Pitchen int irq;
121302c958ddSCyrille Pitchen
121402c958ddSCyrille Pitchen unsigned int ISR;
121502c958ddSCyrille Pitchen unsigned int IER;
121602c958ddSCyrille Pitchen unsigned int IDR;
121702c958ddSCyrille Pitchen unsigned int IMR;
121802c958ddSCyrille Pitchen unsigned int TBQP;
1219fff8019aSHarini Katakam unsigned int TBQPH;
1220ae1f2a56SRafal Ozieblo unsigned int RBQS;
1221ae1f2a56SRafal Ozieblo unsigned int RBQP;
1222ae1f2a56SRafal Ozieblo unsigned int RBQPH;
122302c958ddSCyrille Pitchen
1224138badbcSRobert Hancock /* Lock to protect tx_head and tx_tail */
1225138badbcSRobert Hancock spinlock_t tx_ptr_lock;
122602c958ddSCyrille Pitchen unsigned int tx_head, tx_tail;
122702c958ddSCyrille Pitchen struct macb_dma_desc *tx_ring;
122802c958ddSCyrille Pitchen struct macb_tx_skb *tx_skb;
122902c958ddSCyrille Pitchen dma_addr_t tx_ring_dma;
123002c958ddSCyrille Pitchen struct work_struct tx_error_task;
1231138badbcSRobert Hancock bool txubr_pending;
1232138badbcSRobert Hancock struct napi_struct napi_tx;
1233ab91f0a9SRafal Ozieblo
1234ae1f2a56SRafal Ozieblo dma_addr_t rx_ring_dma;
1235ae1f2a56SRafal Ozieblo dma_addr_t rx_buffers_dma;
1236ae1f2a56SRafal Ozieblo unsigned int rx_tail;
1237ae1f2a56SRafal Ozieblo unsigned int rx_prepared_head;
1238ae1f2a56SRafal Ozieblo struct macb_dma_desc *rx_ring;
1239ae1f2a56SRafal Ozieblo struct sk_buff **rx_skbuff;
1240ae1f2a56SRafal Ozieblo void *rx_buffers;
1241138badbcSRobert Hancock struct napi_struct napi_rx;
1242512286bbSRafal Ozieblo struct queue_stats stats;
124302c958ddSCyrille Pitchen };
124402c958ddSCyrille Pitchen
1245ae8223deSRafal Ozieblo struct ethtool_rx_fs_item {
1246ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec fs;
1247ae8223deSRafal Ozieblo struct list_head list;
1248ae8223deSRafal Ozieblo };
1249ae8223deSRafal Ozieblo
1250ae8223deSRafal Ozieblo struct ethtool_rx_fs_list {
1251ae8223deSRafal Ozieblo struct list_head list;
1252ae8223deSRafal Ozieblo unsigned int count;
1253ae8223deSRafal Ozieblo };
1254ae8223deSRafal Ozieblo
12559f2f381fSJeff Kirsher struct macb {
12569f2f381fSJeff Kirsher void __iomem *regs;
1257f2ce8a9eSAndy Shevchenko bool native_io;
1258f2ce8a9eSAndy Shevchenko
1259f2ce8a9eSAndy Shevchenko /* hardware IO accessors */
12607a6e0706SDavid S. Miller u32 (*macb_reg_readl)(struct macb *bp, int offset);
12617a6e0706SDavid S. Miller void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
12629f2f381fSJeff Kirsher
1263759cc793SVineeth Karumanchi struct macb_dma_desc *rx_ring_tieoff;
1264759cc793SVineeth Karumanchi dma_addr_t rx_ring_tieoff_dma;
12651b44791aSNicolas Ferre size_t rx_buffer_size;
12669f2f381fSJeff Kirsher
1267b410d13eSZach Brown unsigned int rx_ring_size;
1268b410d13eSZach Brown unsigned int tx_ring_size;
1269b410d13eSZach Brown
127002c958ddSCyrille Pitchen unsigned int num_queues;
1271bfa0914aSNicolas Ferre unsigned int queue_mask;
127202c958ddSCyrille Pitchen struct macb_queue queues[MACB_MAX_QUEUES];
12739f2f381fSJeff Kirsher
12749f2f381fSJeff Kirsher spinlock_t lock;
12759f2f381fSJeff Kirsher struct platform_device *pdev;
12769f2f381fSJeff Kirsher struct clk *pclk;
12779f2f381fSJeff Kirsher struct clk *hclk;
1278e1824dfeSSoren Brinkmann struct clk *tx_clk;
1279aead88bdSshubhrajyoti.datta@xilinx.com struct clk *rx_clk;
1280f5473d1dSHarini Katakam struct clk *tsu_clk;
12819f2f381fSJeff Kirsher struct net_device *dev;
1282a494ed8eSJamie Iles union {
1283a494ed8eSJamie Iles struct macb_stats macb;
1284a494ed8eSJamie Iles struct gem_stats gem;
1285a494ed8eSJamie Iles } hw_stats;
12869f2f381fSJeff Kirsher
12874df95131SNicolas Ferre struct macb_or_gem_ops macbgem_ops;
12884df95131SNicolas Ferre
12899f2f381fSJeff Kirsher struct mii_bus *mii_bus;
12907897b071SAntoine Tenart struct phylink *phylink;
12917897b071SAntoine Tenart struct phylink_config phylink_config;
12928876769bSRussell King (Oracle) struct phylink_pcs phylink_usx_pcs;
12938876769bSRussell King (Oracle) struct phylink_pcs phylink_sgmii_pcs;
1294fb97a846SJean-Christophe PLAGNIOL-VILLARD
1295581df9e1SNicolas Ferre u32 caps;
1296e175587fSNicolas Ferre unsigned int dma_burst_length;
1297581df9e1SNicolas Ferre
1298fb97a846SJean-Christophe PLAGNIOL-VILLARD phy_interface_t phy_interface;
1299b85008b7SJoachim Eastwood
130073d74228SWilly Tarreau /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
130173d74228SWilly Tarreau struct macb_tx_skb rm9200_txq[2];
1302a4c35ed3SCyrille Pitchen unsigned int max_tx_length;
13033ff13f1cSXander Huff
1304512286bbSRafal Ozieblo u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
130598b5a0f4SHarini Katakam
130698b5a0f4SHarini Katakam unsigned int rx_frm_len_mask;
130798b5a0f4SHarini Katakam unsigned int jumbo_max_len;
13083e2a5e15SSergio Prado
13093e2a5e15SSergio Prado u32 wol;
13100cb8de39SVineeth Karumanchi u32 wolopts;
1311c2594d80SAndrei.Pistirica@microchip.com
1312cae4bc06SMaulik Jodhani /* holds value of rx watermark value for pbuf_rxcutthru register */
1313cae4bc06SMaulik Jodhani u32 rx_watermark;
1314cae4bc06SMaulik Jodhani
1315c2594d80SAndrei.Pistirica@microchip.com struct macb_ptp_info *ptp_info; /* macb-ptp interface */
13168b73fa3aSRobert Hancock
13178b73fa3aSRobert Hancock struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
13188b73fa3aSRobert Hancock
13197b429614SRafal Ozieblo #ifdef MACB_EXT_DESC
13207b429614SRafal Ozieblo uint8_t hw_dma_cap;
1321dc97a89eSRafal Ozieblo #endif
1322ab91f0a9SRafal Ozieblo spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1323ab91f0a9SRafal Ozieblo unsigned int tsu_rate;
1324ab91f0a9SRafal Ozieblo struct ptp_clock *ptp_clock;
1325ab91f0a9SRafal Ozieblo struct ptp_clock_info ptp_clock_info;
1326ab91f0a9SRafal Ozieblo struct tsu_incr tsu_incr;
1327202cb220SKory Maincent struct kernel_hwtstamp_config tstamp_config;
1328ae8223deSRafal Ozieblo
1329ae8223deSRafal Ozieblo /* RX queue filer rule set*/
1330ae8223deSRafal Ozieblo struct ethtool_rx_fs_list rx_fs_list;
1331ae8223deSRafal Ozieblo spinlock_t rx_fs_lock;
1332ae8223deSRafal Ozieblo unsigned int max_tuples;
1333032dc41bSHarini Katakam
1334*c5092ba3SAllen Pais struct work_struct hresp_err_bh_work;
1335404cd086SHarini Katakam
1336404cd086SHarini Katakam int rx_bd_rd_prefetch;
1337404cd086SHarini Katakam int tx_bd_rd_prefetch;
1338e501070eSHarini Katakam
1339e501070eSHarini Katakam u32 rx_intr_mask;
1340c1e85c6cSClaudiu Beznea
1341c1e85c6cSClaudiu Beznea struct macb_pm_data pm_data;
1342edac6386SClaudiu Beznea const struct macb_usrio_config *usrio;
13439f2f381fSJeff Kirsher };
13449f2f381fSJeff Kirsher
1345ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP
1346ab91f0a9SRafal Ozieblo #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1347ab91f0a9SRafal Ozieblo #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1348ab91f0a9SRafal Ozieblo #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1349ab91f0a9SRafal Ozieblo
1350ab91f0a9SRafal Ozieblo enum macb_bd_control {
1351ab91f0a9SRafal Ozieblo TSTAMP_DISABLED,
1352ab91f0a9SRafal Ozieblo TSTAMP_FRAME_PTP_EVENT_ONLY,
1353ab91f0a9SRafal Ozieblo TSTAMP_ALL_PTP_FRAMES,
1354ab91f0a9SRafal Ozieblo TSTAMP_ALL_FRAMES,
1355ab91f0a9SRafal Ozieblo };
1356ab91f0a9SRafal Ozieblo
1357ab91f0a9SRafal Ozieblo void gem_ptp_init(struct net_device *ndev);
1358ab91f0a9SRafal Ozieblo void gem_ptp_remove(struct net_device *ndev);
13598e7610e6SRobert Hancock void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1360ab91f0a9SRafal Ozieblo void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)13618e7610e6SRobert Hancock static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1362ab91f0a9SRafal Ozieblo {
13638e7610e6SRobert Hancock if (bp->tstamp_config.tx_type == TSTAMP_DISABLED)
13648e7610e6SRobert Hancock return;
1365ab91f0a9SRafal Ozieblo
13668e7610e6SRobert Hancock gem_ptp_txstamp(bp, skb, desc);
1367ab91f0a9SRafal Ozieblo }
1368ab91f0a9SRafal Ozieblo
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1369ab91f0a9SRafal Ozieblo static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1370ab91f0a9SRafal Ozieblo {
1371ab91f0a9SRafal Ozieblo if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1372ab91f0a9SRafal Ozieblo return;
1373ab91f0a9SRafal Ozieblo
1374ab91f0a9SRafal Ozieblo gem_ptp_rxstamp(bp, skb, desc);
1375ab91f0a9SRafal Ozieblo }
1376202cb220SKory Maincent
1377202cb220SKory Maincent int gem_get_hwtst(struct net_device *dev,
1378202cb220SKory Maincent struct kernel_hwtstamp_config *tstamp_config);
1379202cb220SKory Maincent int gem_set_hwtst(struct net_device *dev,
1380202cb220SKory Maincent struct kernel_hwtstamp_config *tstamp_config,
1381202cb220SKory Maincent struct netlink_ext_ack *extack);
1382ab91f0a9SRafal Ozieblo #else
gem_ptp_init(struct net_device * ndev)1383ab91f0a9SRafal Ozieblo static inline void gem_ptp_init(struct net_device *ndev) { }
gem_ptp_remove(struct net_device * ndev)1384ab91f0a9SRafal Ozieblo static inline void gem_ptp_remove(struct net_device *ndev) { }
1385ab91f0a9SRafal Ozieblo
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)13868e7610e6SRobert Hancock static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1387ab91f0a9SRafal Ozieblo static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1388ab91f0a9SRafal Ozieblo #endif
1389ab91f0a9SRafal Ozieblo
macb_is_gem(struct macb * bp)1390f75ba50bSJamie Iles static inline bool macb_is_gem(struct macb *bp)
1391f75ba50bSJamie Iles {
1392e175587fSNicolas Ferre return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1393f75ba50bSJamie Iles }
1394f75ba50bSJamie Iles
gem_has_ptp(struct macb * bp)1395c2594d80SAndrei.Pistirica@microchip.com static inline bool gem_has_ptp(struct macb *bp)
1396c2594d80SAndrei.Pistirica@microchip.com {
1397adee474aSHarini Katakam return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP);
1398c2594d80SAndrei.Pistirica@microchip.com }
1399c2594d80SAndrei.Pistirica@microchip.com
140020c168beSAlexandre Belloni /**
140120c168beSAlexandre Belloni * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
140220c168beSAlexandre Belloni * @pclk: platform clock
140320c168beSAlexandre Belloni * @hclk: AHB clock
140420c168beSAlexandre Belloni */
140520c168beSAlexandre Belloni struct macb_platform_data {
140620c168beSAlexandre Belloni struct clk *pclk;
140720c168beSAlexandre Belloni struct clk *hclk;
140820c168beSAlexandre Belloni };
140920c168beSAlexandre Belloni
14109f2f381fSJeff Kirsher #endif /* _MACB_H */
1411