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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer External Interrupt Unit (EXIU)
10 - Ard Biesheuvel <ardb@kernel.org>
13 The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
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H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/linux/Documentation/devicetree/bindings/spi/
H A Dsocionext,synquacer-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer HS-SPI Controller
10 - Masahisa Kojima <masahisa.kojima@linaro.org>
11 - Jassi Brar <jaswinder.singh@linaro.org>
14 - $ref: spi-controller.yaml#
18 const: socionext,synquacer-spi
26 - description: core clock
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/linux/drivers/char/tpm/
H A Dtpm_tis_synquacer.c1 // SPDX-License-Identifier: GPL-2.0
5 * This device driver implements MMIO TPM on SynQuacer Platform.
19 * irq = -1 means: no irq support
43 while (len--) in tpm_tis_synquacer_read_bytes()
44 *result++ = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
47 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
48 result[0] = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
51 result[3] = ioread8(phy->iobase + addr + 3); in tpm_tis_synquacer_read_bytes()
52 result[2] = ioread8(phy->iobase + addr + 2); in tpm_tis_synquacer_read_bytes()
53 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 which is required to validate the PCR 0-7 values.
40 and interposer attacks (see tpm-security.rst). Saying Y
73 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
74 depends on SPI
78 non-tcg SPI master (i.e. most embedded platforms) that is compliant with the
85 bool "Cr50 SPI Interface"
88 If you have a H1 secure module running Cr50 firmware on SPI bus,
92 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
104 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
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/linux/arch/arm64/boot/dts/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
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/linux/drivers/spi/
H A Dspi-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
3 // Synquacer HSSPI controller driver
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
19 #include <linux/spi/spi.h>
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for kernel SPI drivers.
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
16 # SPI master controller drivers (bus)
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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/linux/drivers/irqchip/
H A Dirq-sni-exiu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
69 writel_relaxed(val, data->base + EIMASK); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
79 writel_relaxed(val, data->base + EIMASK); in exiu_irq_unmask()
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H A Dirq-gic-v3-its.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
41 #include "irq-msi-lib.h"
57 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
66 * Collection structure - just an ID, and a redistributor address to
76 * The ITS_BASER structure - contains memory information, cached
89 * The ITS structure - contains most of the infrastructure, with the
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/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
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H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
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H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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