Lines Matching +full:synquacer +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "reg-mux";
38 #mux-control-cells = <1>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
44 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
45 ti,qsgmii-main-ports = <1>;
47 #phy-cells = <1>;
50 usb_serdes_mux: mux-controller@4000 {
51 compatible = "reg-mux";
53 #mux-control-cells = <1>;
54 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
58 gic500: interrupt-controller@1800000 {
59 compatible = "arm,gic-v3";
60 #address-cells = <2>;
61 #size-cells = <2>;
63 #interrupt-cells = <3>;
64 interrupt-controller;
74 gic_its: msi-controller@1820000 {
75 compatible = "arm,gic-v3-its";
77 socionext,synquacer-pre-its = <0x1000000 0x400000>;
78 msi-controller;
79 #msi-cells = <1>;
83 main_gpio_intr: interrupt-controller@a00000 {
84 compatible = "ti,sci-intr";
86 ti,intr-trigger-type = <1>;
87 interrupt-controller;
88 interrupt-parent = <&gic500>;
89 #interrupt-cells = <1>;
91 ti,sci-dev-id = <131>;
92 ti,interrupt-ranges = <8 392 56>;
96 compatible = "simple-bus";
97 #address-cells = <2>;
98 #size-cells = <2>;
100 ti,sci-dev-id = <199>;
101 dma-coherent;
102 dma-ranges;
104 main_navss_intr: interrupt-controller@310e0000 {
105 compatible = "ti,sci-intr";
107 ti,intr-trigger-type = <4>;
108 interrupt-controller;
109 interrupt-parent = <&gic500>;
110 #interrupt-cells = <1>;
112 ti,sci-dev-id = <213>;
113 ti,interrupt-ranges = <0 64 64>,
118 main_udmass_inta: msi-controller@33d00000 {
119 compatible = "ti,sci-inta";
121 interrupt-controller;
122 #interrupt-cells = <0>;
123 interrupt-parent = <&main_navss_intr>;
124 msi-controller;
126 ti,sci-dev-id = <209>;
127 ti,interrupt-ranges = <0 0 256>;
131 compatible = "ti,am654-secure-proxy";
132 #mbox-cells = <1>;
133 reg-names = "target_data", "rt", "scfg";
137 interrupt-names = "rx_011";
142 compatible = "ti,am654-hwspinlock";
144 #hwlock-cells = <1>;
148 compatible = "ti,am654-mailbox";
150 #mbox-cells = <1>;
151 ti,mbox-num-users = <4>;
152 ti,mbox-num-fifos = <16>;
153 interrupt-parent = <&main_navss_intr>;
158 compatible = "ti,am654-mailbox";
160 #mbox-cells = <1>;
161 ti,mbox-num-users = <4>;
162 ti,mbox-num-fifos = <16>;
163 interrupt-parent = <&main_navss_intr>;
168 compatible = "ti,am654-mailbox";
170 #mbox-cells = <1>;
171 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <16>;
173 interrupt-parent = <&main_navss_intr>;
178 compatible = "ti,am654-mailbox";
180 #mbox-cells = <1>;
181 ti,mbox-num-users = <4>;
182 ti,mbox-num-fifos = <16>;
183 interrupt-parent = <&main_navss_intr>;
188 compatible = "ti,am654-mailbox";
190 #mbox-cells = <1>;
191 ti,mbox-num-users = <4>;
192 ti,mbox-num-fifos = <16>;
193 interrupt-parent = <&main_navss_intr>;
198 compatible = "ti,am654-mailbox";
200 #mbox-cells = <1>;
201 ti,mbox-num-users = <4>;
202 ti,mbox-num-fifos = <16>;
203 interrupt-parent = <&main_navss_intr>;
208 compatible = "ti,am654-mailbox";
210 #mbox-cells = <1>;
211 ti,mbox-num-users = <4>;
212 ti,mbox-num-fifos = <16>;
213 interrupt-parent = <&main_navss_intr>;
218 compatible = "ti,am654-mailbox";
220 #mbox-cells = <1>;
221 ti,mbox-num-users = <4>;
222 ti,mbox-num-fifos = <16>;
223 interrupt-parent = <&main_navss_intr>;
228 compatible = "ti,am654-mailbox";
230 #mbox-cells = <1>;
231 ti,mbox-num-users = <4>;
232 ti,mbox-num-fifos = <16>;
233 interrupt-parent = <&main_navss_intr>;
238 compatible = "ti,am654-mailbox";
240 #mbox-cells = <1>;
241 ti,mbox-num-users = <4>;
242 ti,mbox-num-fifos = <16>;
243 interrupt-parent = <&main_navss_intr>;
248 compatible = "ti,am654-mailbox";
250 #mbox-cells = <1>;
251 ti,mbox-num-users = <4>;
252 ti,mbox-num-fifos = <16>;
253 interrupt-parent = <&main_navss_intr>;
258 compatible = "ti,am654-mailbox";
260 #mbox-cells = <1>;
261 ti,mbox-num-users = <4>;
262 ti,mbox-num-fifos = <16>;
263 interrupt-parent = <&main_navss_intr>;
268 compatible = "ti,am654-navss-ringacc";
274 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
275 ti,num-rings = <1024>;
276 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
278 ti,sci-dev-id = <211>;
279 msi-parent = <&main_udmass_inta>;
282 main_udmap: dma-controller@31150000 {
283 compatible = "ti,j721e-navss-main-udmap";
290 reg-names = "gcfg", "rchanrt", "tchanrt",
292 msi-parent = <&main_udmass_inta>;
293 #dma-cells = <1>;
296 ti,sci-dev-id = <212>;
299 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
302 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
305 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
309 compatible = "ti,j721e-cpts";
311 reg-names = "cpts";
313 clock-names = "cpts";
314 interrupts-extended = <&main_navss_intr 391>;
315 interrupt-names = "cpts";
316 ti,cpts-periodic-outputs = <6>;
317 ti,cpts-ext-ts-inputs = <8>;
322 compatible = "ti,j7200-cpswxg-nuss";
323 #address-cells = <2>;
324 #size-cells = <2>;
326 reg-names = "cpsw_nuss";
329 clock-names = "fck";
330 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
341 dma-names = "tx0", "tx1", "tx2", "tx3",
347 ethernet-ports {
348 #address-cells = <1>;
349 #size-cells = <0>;
352 ti,mac-only;
359 ti,mac-only;
366 ti,mac-only;
373 ti,mac-only;
380 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
382 #address-cells = <1>;
383 #size-cells = <0>;
385 clock-names = "fck";
391 compatible = "ti,j721e-cpts";
394 clock-names = "cpts";
395 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "cpts";
397 ti,cpts-ext-ts-inputs = <4>;
398 ti,cpts-periodic-outputs = <2>;
404 compatible = "ti,j7200-padconf", "pinctrl-single";
406 #pinctrl-cells = <1>;
407 pinctrl-single,register-width = <32>;
408 pinctrl-single,function-mask = <0x000001ff>;
413 compatible = "ti,j7200-padconf", "pinctrl-single";
415 #pinctrl-cells = <1>;
416 pinctrl-single,register-width = <32>;
417 pinctrl-single,function-mask = <0x0000001f>;
421 compatible = "ti,j7200-padconf", "pinctrl-single";
424 #pinctrl-cells = <1>;
425 pinctrl-single,register-width = <32>;
426 pinctrl-single,function-mask = <0xffffffff>;
430 compatible = "ti,j7200-padconf", "pinctrl-single";
433 #pinctrl-cells = <1>;
434 pinctrl-single,register-width = <32>;
435 pinctrl-single,function-mask = <0xffffffff>;
439 compatible = "ti,j721e-uart", "ti,am654-uart";
442 clock-frequency = <48000000>;
443 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
445 clock-names = "fclk";
450 compatible = "ti,j721e-uart", "ti,am654-uart";
453 clock-frequency = <48000000>;
454 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
456 clock-names = "fclk";
461 compatible = "ti,j721e-uart", "ti,am654-uart";
464 clock-frequency = <48000000>;
465 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
467 clock-names = "fclk";
472 compatible = "ti,j721e-uart", "ti,am654-uart";
475 clock-frequency = <48000000>;
476 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
478 clock-names = "fclk";
483 compatible = "ti,j721e-uart", "ti,am654-uart";
486 clock-frequency = <48000000>;
487 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
489 clock-names = "fclk";
494 compatible = "ti,j721e-uart", "ti,am654-uart";
497 clock-frequency = <48000000>;
498 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
500 clock-names = "fclk";
505 compatible = "ti,j721e-uart", "ti,am654-uart";
508 clock-frequency = <48000000>;
509 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
511 clock-names = "fclk";
516 compatible = "ti,j721e-uart", "ti,am654-uart";
519 clock-frequency = <48000000>;
520 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
522 clock-names = "fclk";
527 compatible = "ti,j721e-uart", "ti,am654-uart";
530 clock-frequency = <48000000>;
531 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
533 clock-names = "fclk";
538 compatible = "ti,j721e-uart", "ti,am654-uart";
541 clock-frequency = <48000000>;
542 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
544 clock-names = "fclk";
549 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 clock-names = "fck";
556 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
561 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clock-names = "fck";
568 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
573 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 clock-names = "fck";
580 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
585 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 clock-names = "fck";
592 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
597 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
600 #address-cells = <1>;
601 #size-cells = <0>;
602 clock-names = "fck";
604 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
609 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
612 #address-cells = <1>;
613 #size-cells = <0>;
614 clock-names = "fck";
616 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
621 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
624 #address-cells = <1>;
625 #size-cells = <0>;
626 clock-names = "fck";
628 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
633 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
636 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
637 clock-names = "clk_ahb", "clk_xin";
639 ti,otap-del-sel-legacy = <0x0>;
640 ti,otap-del-sel-mmc-hs = <0x0>;
641 ti,otap-del-sel-ddr52 = <0x6>;
642 ti,otap-del-sel-hs200 = <0x8>;
643 ti,otap-del-sel-hs400 = <0x5>;
644 ti,itap-del-sel-legacy = <0x10>;
645 ti,itap-del-sel-mmc-hs = <0xa>;
646 ti,itap-del-sel-ddr52 = <0x3>;
647 ti,strobe-sel = <0x77>;
648 ti,clkbuf-sel = <0x7>;
649 ti,trm-icp = <0x8>;
650 bus-width = <8>;
651 mmc-ddr-1_8v;
652 mmc-hs200-1_8v;
653 mmc-hs400-1_8v;
654 dma-coherent;
659 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
662 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
663 clock-names = "clk_ahb", "clk_xin";
665 ti,otap-del-sel-legacy = <0x0>;
666 ti,otap-del-sel-sd-hs = <0x0>;
667 ti,otap-del-sel-sdr12 = <0xf>;
668 ti,otap-del-sel-sdr25 = <0xf>;
669 ti,otap-del-sel-sdr50 = <0xc>;
670 ti,otap-del-sel-sdr104 = <0x5>;
671 ti,otap-del-sel-ddr50 = <0xc>;
672 ti,itap-del-sel-legacy = <0x0>;
673 ti,itap-del-sel-sd-hs = <0x0>;
674 ti,itap-del-sel-sdr12 = <0x0>;
675 ti,itap-del-sel-sdr25 = <0x0>;
676 ti,clkbuf-sel = <0x7>;
677 ti,trm-icp = <0x8>;
678 dma-coherent;
683 compatible = "ti,j721e-wiz-10g";
684 #address-cells = <1>;
685 #size-cells = <1>;
686 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
688 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
689 num-lanes = <4>;
690 #reset-cells = <1>;
693 assigned-clocks = <&k3_clks 292 85>;
694 assigned-clock-parents = <&k3_clks 292 89>;
696 wiz0_pll0_refclk: pll0-refclk {
698 clock-output-names = "wiz0_pll0_refclk";
699 #clock-cells = <0>;
700 assigned-clocks = <&wiz0_pll0_refclk>;
701 assigned-clock-parents = <&k3_clks 292 85>;
704 wiz0_pll1_refclk: pll1-refclk {
706 clock-output-names = "wiz0_pll1_refclk";
707 #clock-cells = <0>;
708 assigned-clocks = <&wiz0_pll1_refclk>;
709 assigned-clock-parents = <&k3_clks 292 85>;
712 wiz0_refclk_dig: refclk-dig {
714 clock-output-names = "wiz0_refclk_dig";
715 #clock-cells = <0>;
716 assigned-clocks = <&wiz0_refclk_dig>;
717 assigned-clock-parents = <&k3_clks 292 85>;
720 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
722 #clock-cells = <0>;
726 compatible = "ti,j721e-serdes-10g";
728 reg-names = "torrent_phy";
730 reset-names = "torrent_reset";
732 clock-names = "refclk";
733 #address-cells = <1>;
734 #size-cells = <0>;
739 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
744 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
745 interrupt-names = "link_state";
748 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
749 max-link-speed = <3>;
750 num-lanes = <4>;
751 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
753 clock-names = "fck";
754 #address-cells = <3>;
755 #size-cells = <2>;
756 bus-range = <0x0 0xff>;
757 cdns,no-bar-match-nbits = <64>;
758 vendor-id = <0x104c>;
759 device-id = <0xb00f>;
760 msi-map = <0x0 &gic_its 0x0 0x10000>;
761 dma-coherent;
764 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
768 usbss0: cdns-usb@4104000 {
769 compatible = "ti,j721e-usb";
771 dma-coherent;
772 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
774 clock-names = "ref", "lpm";
775 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
776 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
777 #address-cells = <2>;
778 #size-cells = <2>;
786 reg-names = "otg", "xhci", "dev";
790 interrupt-names = "host",
793 maximum-speed = "super-speed";
795 cdns,phyrst-a-enable;
800 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
802 gpio-controller;
803 #gpio-cells = <2>;
804 interrupt-parent = <&main_gpio_intr>;
807 interrupt-controller;
808 #interrupt-cells = <2>;
810 ti,davinci-gpio-unbanked = <0>;
811 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
813 clock-names = "gpio";
818 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
820 gpio-controller;
821 #gpio-cells = <2>;
822 interrupt-parent = <&main_gpio_intr>;
825 interrupt-controller;
826 #interrupt-cells = <2>;
828 ti,davinci-gpio-unbanked = <0>;
829 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
831 clock-names = "gpio";
836 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
838 gpio-controller;
839 #gpio-cells = <2>;
840 interrupt-parent = <&main_gpio_intr>;
843 interrupt-controller;
844 #interrupt-cells = <2>;
846 ti,davinci-gpio-unbanked = <0>;
847 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
849 clock-names = "gpio";
854 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
856 gpio-controller;
857 #gpio-cells = <2>;
858 interrupt-parent = <&main_gpio_intr>;
861 interrupt-controller;
862 #interrupt-cells = <2>;
864 ti,davinci-gpio-unbanked = <0>;
865 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
867 clock-names = "gpio";
875 reg-names = "m_can", "message_ram";
876 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
878 clock-names = "hclk", "cclk";
881 interrupt-names = "int0", "int1";
882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
890 reg-names = "m_can", "message_ram";
891 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
893 clock-names = "hclk", "cclk";
896 interrupt-names = "int0", "int1";
897 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
905 reg-names = "m_can", "message_ram";
906 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
908 clock-names = "hclk", "cclk";
911 interrupt-names = "int0", "int1";
912 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
920 reg-names = "m_can", "message_ram";
921 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
923 clock-names = "hclk", "cclk";
926 interrupt-names = "int0", "int1";
927 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
935 reg-names = "m_can", "message_ram";
936 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
938 clock-names = "hclk", "cclk";
941 interrupt-names = "int0", "int1";
942 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
950 reg-names = "m_can", "message_ram";
951 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
953 clock-names = "hclk", "cclk";
956 interrupt-names = "int0", "int1";
957 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
965 reg-names = "m_can", "message_ram";
966 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
968 clock-names = "hclk", "cclk";
971 interrupt-names = "int0", "int1";
972 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
980 reg-names = "m_can", "message_ram";
981 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
983 clock-names = "hclk", "cclk";
986 interrupt-names = "int0", "int1";
987 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
995 reg-names = "m_can", "message_ram";
996 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
998 clock-names = "hclk", "cclk";
1001 interrupt-names = "int0", "int1";
1002 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1010 reg-names = "m_can", "message_ram";
1011 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1013 clock-names = "hclk", "cclk";
1016 interrupt-names = "int0", "int1";
1017 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1025 reg-names = "m_can", "message_ram";
1026 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1028 clock-names = "hclk", "cclk";
1031 interrupt-names = "int0", "int1";
1032 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1040 reg-names = "m_can", "message_ram";
1041 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1043 clock-names = "hclk", "cclk";
1046 interrupt-names = "int0", "int1";
1047 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1055 reg-names = "m_can", "message_ram";
1056 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1058 clock-names = "hclk", "cclk";
1061 interrupt-names = "int0", "int1";
1062 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1070 reg-names = "m_can", "message_ram";
1071 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1073 clock-names = "hclk", "cclk";
1076 interrupt-names = "int0", "int1";
1077 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1085 reg-names = "m_can", "message_ram";
1086 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1088 clock-names = "hclk", "cclk";
1091 interrupt-names = "int0", "int1";
1092 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1100 reg-names = "m_can", "message_ram";
1101 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1103 clock-names = "hclk", "cclk";
1106 interrupt-names = "int0", "int1";
1107 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1115 reg-names = "m_can", "message_ram";
1116 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1118 clock-names = "hclk", "cclk";
1121 interrupt-names = "int0", "int1";
1122 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1130 reg-names = "m_can", "message_ram";
1131 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1133 clock-names = "hclk", "cclk";
1136 interrupt-names = "int0", "int1";
1137 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1141 main_spi0: spi@2100000 {
1142 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1152 main_spi1: spi@2110000 {
1153 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1163 main_spi2: spi@2120000 {
1164 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1169 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1174 main_spi3: spi@2130000 {
1175 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1185 main_spi4: spi@2140000 {
1186 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1191 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1196 main_spi5: spi@2150000 {
1197 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1202 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1207 main_spi6: spi@2160000 {
1208 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1218 main_spi7: spi@2170000 {
1219 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1230 compatible = "ti,j7-rti-wdt";
1233 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1234 assigned-clocks = <&k3_clks 252 1>;
1235 assigned-clock-parents = <&k3_clks 252 5>;
1239 compatible = "ti,j7-rti-wdt";
1242 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1243 assigned-clocks = <&k3_clks 253 1>;
1244 assigned-clock-parents = <&k3_clks 253 5>;
1248 compatible = "ti,am654-timer";
1252 clock-names = "fck";
1253 assigned-clocks = <&k3_clks 49 1>;
1254 assigned-clock-parents = <&k3_clks 49 2>;
1255 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1256 ti,timer-pwm;
1260 compatible = "ti,am654-timer";
1264 clock-names = "fck";
1265 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1266 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1267 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1268 ti,timer-pwm;
1272 compatible = "ti,am654-timer";
1276 clock-names = "fck";
1277 assigned-clocks = <&k3_clks 51 1>;
1278 assigned-clock-parents = <&k3_clks 51 2>;
1279 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1280 ti,timer-pwm;
1284 compatible = "ti,am654-timer";
1288 clock-names = "fck";
1289 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1290 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1291 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1292 ti,timer-pwm;
1296 compatible = "ti,am654-timer";
1300 clock-names = "fck";
1301 assigned-clocks = <&k3_clks 53 1>;
1302 assigned-clock-parents = <&k3_clks 53 2>;
1303 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1304 ti,timer-pwm;
1308 compatible = "ti,am654-timer";
1312 clock-names = "fck";
1313 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1314 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1315 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1316 ti,timer-pwm;
1320 compatible = "ti,am654-timer";
1324 clock-names = "fck";
1325 assigned-clocks = <&k3_clks 55 1>;
1326 assigned-clock-parents = <&k3_clks 55 2>;
1327 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1328 ti,timer-pwm;
1332 compatible = "ti,am654-timer";
1336 clock-names = "fck";
1337 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1338 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1339 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1340 ti,timer-pwm;
1344 compatible = "ti,am654-timer";
1348 clock-names = "fck";
1349 assigned-clocks = <&k3_clks 58 1>;
1350 assigned-clock-parents = <&k3_clks 58 2>;
1351 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1352 ti,timer-pwm;
1356 compatible = "ti,am654-timer";
1360 clock-names = "fck";
1361 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1362 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1363 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1364 ti,timer-pwm;
1368 compatible = "ti,am654-timer";
1372 clock-names = "fck";
1373 assigned-clocks = <&k3_clks 60 1>;
1374 assigned-clock-parents = <&k3_clks 60 2>;
1375 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1376 ti,timer-pwm;
1380 compatible = "ti,am654-timer";
1384 clock-names = "fck";
1385 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1386 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1387 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1388 ti,timer-pwm;
1392 compatible = "ti,am654-timer";
1396 clock-names = "fck";
1397 assigned-clocks = <&k3_clks 63 1>;
1398 assigned-clock-parents = <&k3_clks 63 2>;
1399 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1400 ti,timer-pwm;
1404 compatible = "ti,am654-timer";
1408 clock-names = "fck";
1409 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1410 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1411 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1412 ti,timer-pwm;
1416 compatible = "ti,am654-timer";
1420 clock-names = "fck";
1421 assigned-clocks = <&k3_clks 65 1>;
1422 assigned-clock-parents = <&k3_clks 65 2>;
1423 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1424 ti,timer-pwm;
1428 compatible = "ti,am654-timer";
1432 clock-names = "fck";
1433 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1434 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1435 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1436 ti,timer-pwm;
1440 compatible = "ti,am654-timer";
1444 clock-names = "fck";
1445 assigned-clocks = <&k3_clks 67 1>;
1446 assigned-clock-parents = <&k3_clks 67 2>;
1447 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1448 ti,timer-pwm;
1452 compatible = "ti,am654-timer";
1456 clock-names = "fck";
1457 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1458 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1459 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1460 ti,timer-pwm;
1464 compatible = "ti,am654-timer";
1468 clock-names = "fck";
1469 assigned-clocks = <&k3_clks 69 1>;
1470 assigned-clock-parents = <&k3_clks 69 2>;
1471 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1472 ti,timer-pwm;
1476 compatible = "ti,am654-timer";
1480 clock-names = "fck";
1481 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1482 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1483 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1484 ti,timer-pwm;
1488 compatible = "ti,j7200-r5fss";
1489 ti,cluster-mode = <1>;
1490 #address-cells = <1>;
1491 #size-cells = <1>;
1494 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1497 compatible = "ti,j7200-r5f";
1500 reg-names = "atcm", "btcm";
1502 ti,sci-dev-id = <245>;
1503 ti,sci-proc-ids = <0x06 0xff>;
1505 firmware-name = "j7200-main-r5f0_0-fw";
1506 ti,atcm-enable = <1>;
1507 ti,btcm-enable = <1>;
1512 compatible = "ti,j7200-r5f";
1515 reg-names = "atcm", "btcm";
1517 ti,sci-dev-id = <246>;
1518 ti,sci-proc-ids = <0x07 0xff>;
1520 firmware-name = "j7200-main-r5f0_1-fw";
1521 ti,atcm-enable = <1>;
1522 ti,btcm-enable = <1>;
1528 compatible = "ti,j721e-esm";
1530 ti,esm-pins = <656>, <657>;