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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a-tqmlx2160a-mblx2160a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
14 #include "fsl-lx2160a-tqmlx2160a.dtsi"
18 compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
31 stdout-path = &uart0;
[all …]
H A Dimx8mn-tqma8mqnl-mba8mx.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include "imx8mn-tqma8mqnl.dtsi"
12 model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
13 compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
14 chassis-type = "embedded";
25 reg_usdhc2_vmmc: regulator-vmmc {
26 compatible = "regulator-fixed";
27 pinctrl-names = "default";
[all …]
H A Dmba8xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
14 compatible = "iio-hwmon";
15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
23 backlight_lvds: backlight-lvds {
24 compatible = "pwm-backlight";
[all …]
H A Dimx8mp-tqma8mpql-mba8mpxl.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
141 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_a31.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun6i-a31-ccu.h>
48 #include <dt-bindings/reset/sun6i-a31-ccu.h>
50 /* Non-exported clocks */
148 CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_h3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
53 #include <dev/clk/allwinner/aw_ccung.h>
55 #include <dt-bindings/clock/sun8i-h3-ccu.h>
56 #include <dt-bindings/reset/sun8i-h3-ccu.h>
58 /* Non-exported resets */
61 /* Non-exported clocks */
[all …]
H A Dccu_a10.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun4i-a10-ccu.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
51 /* Non-exported resets */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
[all …]
H A Dspi-mt65xx.txt4 - compatible: should be one of the following.
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
13 - mediatek,mt8183-spi: for mt8183 platforms
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7981b.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a53";
[all …]
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
H A Dmt8188.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
15 #include <dt-bindings/reset/mt8188-resets.h>
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-cbus-gpio.txt1 Device tree bindings for i2c-cbus-gpio driver
4 - compatible = "i2c-cbus-gpio";
5 - gpios: clk, dat, sel
6 - #address-cells = <1>;
7 - #size-cells = <0>;
10 - child nodes conforming to i2c bus binding
15 compatible = "i2c-cbus-gpio";
16 gpios = <&gpio 66 0 /* clk */
18 &gpio 64 0 /* sel */
20 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subde
[all...]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
17 gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
19 &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
H A Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp151c-mecio1r0.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include "stm32mp15x-mecio1-io.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
22 compatible = "gpio-leds";
24 led-0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dhdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-tx-8084
17 - qcom,hdmi-tx-8660
18 - qcom,hdmi-tx-8960
19 - qcom,hdmi-tx-8974
20 - qcom,hdmi-tx-8994
21 - qcom,hdmi-tx-8996
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra124-pinmux.txt4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
14 -- third entry - the MIPI_PAD_CTRL register
18 include/dt-binding/pinctrl/pinctrl-tegra.h.
19 - nvidia,enable-input: Integer. Enable the pin's input path.
[all …]

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