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/linux/Documentation/devicetree/bindings/ata/
H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
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H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
21 const: ceva,ahci-1v84
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/linux/drivers/scsi/isci/
H A Dphy.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
72 /* Maximum arbitration wait time in micro-seconds */
77 return iphy->max_negotiated_speed; in sci_phy_linkrate()
82 struct isci_phy *table = iphy - iphy->phy_index; in phy_to_host()
90 return &phy_to_host(iphy)->pdev->dev; in sciphy_to_dev()
99 iphy->transport_layer_registers = reg; in sci_phy_transport_layer_initialization()
102 &iphy->transport_layer_registers->stp_rni); in sci_phy_transport_layer_initialization()
108 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
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H A Dphy.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
63 /* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
71 /* This is the timeout for the SATA OOB/SN because the hardware does not
72 * recognize a hot plug after OOB signal but before the SN signals. We need to
74 * notification from the hardware that we restart the hardware OOB state
80 * isci_phy - hba local phy infrastructure
83 * @phy_index: physical index relative to the controller (0-3)
85 * @sata_timer: timeout SATA signature FIS arrival
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/linux/drivers/scsi/mvsas/
H A Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
77 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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/linux/drivers/ata/
H A Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * CEVA AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
142 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()
150 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()
163 /* Phy Control OOB timing parameters COMINIT */ in ahci_ceva_setup()
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H A Dsata_fsl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Freescale 3.0Gbps SATA device driver
10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
82 * MPC8315 has two SATA controllers, SATA1 & SATA2
96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
103 * Host Controller command register set - per port
185 * SATA Superset Registers
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/linux/Documentation/scsi/
H A Dlibsas.rst1 .. SPDX-License-Identifier: GPL-2.0
11 phy/OOB/link management, the SAS layer is concerned with:
20 (SATA), and
25 phy/OOB management, and vendor specific tasks and generates
40 start OOB (at which point your driver will start calling the
47 ------------------
75 - must be set (0/1)
78 - must be set [0,MAX_PHYS)]
81 - must be set
84 - you set this when OOB has finished and then notify
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
45 #size-cells = <1>;
47 spi-tx-bus-width = <4>;
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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/linux/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/linux/drivers/scsi/aic94xx/
H A Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aic94xx SAS/SATA driver SCB management.
19 /* ---------- EMPTY SCB ---------- */
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
52 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
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H A Daic94xx_sas.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Aic94xx SAS/SATA driver SAS definitions and hardware interface header file.
14 /* ---------- DDBs ---------- */
16 * domain that this sequencer can maintain low-level connections for
27 u8 dest_sas_addr[8]; /* bytes 4-11 */
81 u8 dest_sas_addr[8]; /* bytes 4-11 */
153 u8 max_conn_to[3]; /* from Conn-Disc mode page, in us, LE */
155 __le16 bus_inact_to; /* from Conn-Disc mode page, in 100 us, LE */
160 /* This struct asd_ddb_sata_tag, describes a look-up table to be used
161 * by the sequencers. SATA II, IDENTIFY DEVICE data, word 76, bit 8:
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H A Daic94xx_reg_def.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Aic94xx SAS/SATA driver hardware registers definitions.
32 * CHIM Registers, Address Range : (0x00-0xFF)
172 /* 0x38 - 0x3C are reserved */
197 /* 0x58h - 0xFCh are reserved */
200 * DCH_SAS Registers, Address Range : (0x800-0xFFF)
291 /* 0x83Ch - 0xFFCh are reserved */
294 * ARP2 External Processor Registers, Address Range : (0x00-0x1F)
349 /* 0x14h - 0x1Ch are reserved */
352 * ARP2 Registers, Address Range : (0x00-0x1F)
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
231 Raspberry Pi 4's co-processor controls some of the board's HW
234 interfacing with RPi4's co-processor and model these firmware
272 - Altera SoCFPGAs
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/linux/drivers/bcma/
H A Dscan.c15 #include <linux/dma-mapping.h>
31 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
78 { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
119 switch (id->manuf) { in bcma_device_name()
137 if (names[i].id == id->id) in bcma_device_name()
146 return readl(bus->mmio + offset); in bcma_scan_read32()
151 if (bus->hosttype == BCMA_HOSTTYPE_PCI) in bcma_scan_switch_core()
152 pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN, in bcma_scan_switch_core()
165 (*eromptr)--; in bcma_erom_push_ent()
172 return -ENOENT; in bcma_erom_get_ci()
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/linux/drivers/scsi/libsas/
H A Dsas_discover.c1 // SPDX-License-Identifier: GPL-2.0
20 /* ---------- Basic task processing for discovery purposes ---------- */
24 switch (dev->dev_type) { in sas_init_dev()
26 INIT_LIST_HEAD(&dev->ssp_dev.eh_list_node); in sas_init_dev()
30 INIT_LIST_HEAD(&dev->ex_dev.children); in sas_init_dev()
31 mutex_init(&dev->ex_dev.cmd_mutex); in sas_init_dev()
38 /* ---------- Domain device discovery ---------- */
41 * sas_get_port_device - Discover devices which caused port creation
54 int rc = -ENODEV; in sas_get_port_device()
58 return -ENOMEM; in sas_get_port_device()
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/linux/drivers/message/fusion/
H A Dmptbase.c8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
47 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
61 #include <linux/dma-mapping.h>
68 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
106 " debug level - refer to mptdebug.h - (default=0)");
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
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