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/linux/Documentation/devicetree/bindings/ata/
H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
[all …]
H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
14 The Ceva SATA controller mostly conforms to the AHCI interface with some
15 special extensions to add functionality, is a high-performance dual-port
16 SATA host controller with an AHCI compliant command layer which supports
[all …]
/linux/drivers/scsi/isci/
H A Dphy.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
72 /* Maximum arbitration wait time in micro-seconds */
77 return iphy->max_negotiated_speed; in sci_phy_linkrate()
82 struct isci_phy *table = iphy - iphy->phy_index; in phy_to_host()
90 return &phy_to_host(iphy)->pdev->dev; in sciphy_to_dev()
99 iphy->transport_layer_registers = reg; in sci_phy_transport_layer_initialization()
102 &iphy->transport_layer_registers->stp_rni); in sci_phy_transport_layer_initialization()
108 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
[all …]
H A Dphy.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
63 /* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
71 /* This is the timeout for the SATA OOB/SN because the hardware does not
72 * recognize a hot plug after OOB signal but before the SN signals. We need to
74 * notification from the hardware that we restart the hardware OOB state
80 * isci_phy - hba local phy infrastructure
83 * @phy_index: physical index relative to the controller (0-3)
85 * @sata_timer: timeout SATA signature FIS arrival
[all …]
/linux/drivers/scsi/mvsas/
H A Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
77 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
[all …]
/linux/Documentation/scsi/
H A Dlibsas.rst1 .. SPDX-License-Identifier: GPL-2.0
11 phy/OOB/link management, the SAS layer is concerned with:
20 (SATA), and
25 phy/OOB management, and vendor specific tasks and generates
40 start OOB (at which point your driver will start calling the
47 ------------------
75 - must be set (0/1)
78 - must be set [0,MAX_PHYS)]
81 - must be set
84 - you set this when OOB has finished and then notify
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
45 #size-cells = <1>;
47 spi-tx-bus-width = <4>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
43 compatible = "fixed-clock";
[all …]
H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958525er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
84 #size-cells = <1>;
[all …]
H A Dbcm958525xmc.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
76 temperature-sensor@4c {
97 nand-on-flash-bbt;
99 #address-cells = <1>;
[all …]
H A Dbcm988312hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
88 #size-cells = <1>;
[all …]
H A Dbcm958625k.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
42 stdout-path = "serial0:115200n8";
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
88 read-only;
[all …]
/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-xmc.dts33 /dts-v1/;
39 compatible = "brcm,ns2-xmc", "brcm,ns2";
46 stdout-path = "serial0:115200n8";
70 gphy0: eth-phy@10 {
80 nand-ecc-mode = "hw";
81 nand-ecc-strength = <8>;
82 nand-ecc-step-size = <512>;
83 nand-bus-width = <16>;
84 brcm,nand-oob-sector-size = <16>;
85 #address-cells = <1>;
[all …]
H A Dns2-svk.dts33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
117 pl022,slave-tx-disable = <0>;
118 pl022,com-mode = <0>;
119 pl022,rx-level-trig = <1>;
120 pl022,tx-level-trig = <1>;
[all …]
/linux/drivers/scsi/aic94xx/
H A Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aic94xx SAS/SATA driver SCB management.
19 /* ---------- EMPTY SCB ---------- */
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
52 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
[all …]
H A Daic94xx_sas.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Aic94xx SAS/SATA driver SAS definitions and hardware interface header file.
14 /* ---------- DDBs ---------- */
16 * domain that this sequencer can maintain low-level connections for
27 u8 dest_sas_addr[8]; /* bytes 4-11 */
81 u8 dest_sas_addr[8]; /* bytes 4-11 */
153 u8 max_conn_to[3]; /* from Conn-Disc mode page, in us, LE */
155 __le16 bus_inact_to; /* from Conn-Disc mode page, in 100 us, LE */
160 /* This struct asd_ddb_sata_tag, describes a look-up table to be used
161 * by the sequencers. SATA II, IDENTIFY DEVICE data, word 76, bit 8:
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]
/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
208 Raspberry Pi 4's co-processor controls some of the board's HW
211 interfacing with RPi4's co-processor and model these firmware
242 - Altera SoCFPGAs
243 - ASPEED BMC SoCs
[all …]

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