| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
58 /* [0x0] Reserved register for the interrupt controller */
60 /* [0x4] Revision register */
62 /* [0x8] Reserved for future use */
64 /* [0xc] Reserved for future use */
66 /* [0x10] Reserved for future use */
68 /* [0x14] Reserved for future use */
70 /* [0x18] General timer configuration */
76 * [0x0] Mailbox interrupt generator.
80 /* [0x4] Mailbox message data out */
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,rzv2h-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
[all …]
|
| H A D | renesas,r9a09g057-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
[all …]
|
| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
|
| H A D | intel,ixp4xx-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
[all …]
|
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
80 0x1AE0:0x0042
84 Change the TX queue count to 4 for the gve0 interface:
85 .D1 sysctl dev.gve.0.num_tx_queues=4
[all …]
|
| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
[all …]
|
| H A D | iflib.4 | 28 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
47 Set the number of RX queues.
48 If zero, the number of RX queues is derived from the number of cores on the
50 Defaults to 0.
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
[all …]
|
| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
48 #define VIA_VENDORID 0x1106
49 #define VIA_DEVICEID_61XX 0x3119
51 #define VGE_PAR0 0x00 /* physical address register */
52 #define VGE_PAR1 0x02
53 #define VGE_PAR2 0x04
[all …]
|
| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
35 #define PORT_0 0
44 #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
45 #define FCOE_IOS_PER_CONNECTION_SHIFT 0
47 #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
52 #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
53 #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
55 #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2e-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0 0x10000>;
20 #address-cells = <1>;
[all …]
|
| H A D | keystone-k2l-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
20 #address-cells = <1>;
[all …]
|
| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
16 linkram0 = <0x100000 0x8000>;
17 linkram1 = <0x0 0x10000>;
20 #address-cells = <1>;
[all …]
|
| H A D | keystone-k2g-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,66ak2g-navss-qm";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
15 clock-names = "nss_vclk";
17 queue-range = <0 0x80>;
[all …]
|
| /freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: ISC
16 struct mt7996_dev *dev = phy->dev; in mt7996_init_tx_queues()
17 u32 flags = 0; in mt7996_init_tx_queues()
20 ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; in mt7996_init_tx_queues()
21 idx -= MT_TXQ_ID(0); in mt7996_init_tx_queues()
23 if (phy->mt76->band_idx == MT_BAND2) in mt7996_init_tx_queues()
24 flags = MT_WED_Q_TX(0); in mt7996_init_tx_queues()
29 return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, in mt7996_init_tx_queues()
39 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
40 if (napi_complete_done(napi, 0)) in mt7996_poll_tx()
[all …]
|
| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
[all …]
|
| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
79 #define AL_ETH_DEV_ID_STANDARD 0x0001
80 #define AL_ETH_DEV_ID_ADVANCED 0x0002
81 #define AL_ETH_REV_ID_0 0 /* Alpine V1 Rev 0 */
87 #define AL_ETH_UDMA_BAR 0
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
100 AL_ETH_PROTO_ID_UNKNOWN = 0,
[all …]
|
| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_port.h | 2 * Copyright 2008-2013 Freescale Semiconductor Inc.
41 #define BMI_EBD_EN 0x80000000
43 #define BMI_PORT_CFG_EN 0x80000000
44 #define BMI_PORT_CFG_FDOVR 0x02000000
45 #define BMI_PORT_CFG_IM 0x01000000
47 #define BMI_PORT_STATUS_BSY 0x80000000
50 #define BMI_DMA_ATTR_IC_STASH_ON 0x10000000
51 #define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000
52 #define BMI_DMA_ATTR_SG_STASH_ON 0x01000000
56 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
[all …]
|
| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 * It is basically a single Ethernet port (port 0) wired internally to
39 * a 3-port store-and-forward switch connected to two independent
210 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, 0, 0);
232 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, 0, 0);
236 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, 0, 0);
237 DRIVER_MODULE(miibus, cpsw, miibus_driver, 0, 0);
245 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 };
248 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
[all …]
|
| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_hw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
66 * for the ESS core - and that includes both the EDMA (ethernet)
69 * AND, it's a placeholder for what the linux ess-edma driver
72 * ess-switch won't be initialised. In that case it defaults
77 * So, for now this is a big no-op, at least until everything
79 * this EDMA driver code to co-exist.
87 device_printf(sc->sc_dev, "%s: called, TODO!\n", __func__); in qcom_ess_edma_hw_reset()
90 * This is where the linux ess-edma driver would reset the in qcom_ess_edma_hw_reset()
95 * and here's where the linux ess-edma driver would program in qcom_ess_edma_hw_reset()
[all …]
|
| /freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/ |
| H A D | rx.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-prph.h"
12 #include "iwl-io.h"
14 #include "iwl-op-mode.h"
15 #include "pcie/iwl-context-info-v2.h"
20 * RX path functions
25 * Rx theory of operation
[all …]
|
| /freebsd/sys/dev/neta/ |
| H A D | if_mvnetareg.h | 39 #define MVNETA_SIZE 0x4000
46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
[all …]
|
| H A D | if_mvneta.c | 111 /* Rx/Tx Queue Control */
166 /* Rx Subroutines */
191 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx)
192 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx)
195 STATIC int mii_init = 0;
219 DRIVER_MODULE(miibus, mvneta, miibus_driver, 0, 0);
220 DRIVER_MODULE(mdio, mvneta, mdio_driver, 0, 0);
270 "rx_good_oct", "Good Octets Rx"},
271 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0,
272 "rx_bad_oct", "Bad Octets Rx"},
[all …]
|
| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_l2_api.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
38 ECORE_RSS_IPV4 = 0x1,
39 ECORE_RSS_IPV6 = 0x2,
40 ECORE_RSS_IPV4_TCP = 0x4,
41 ECORE_RSS_IPV6_TCP = 0x8,
42 ECORE_RSS_IPV4_UDP = 0x10,
43 ECORE_RSS_IPV6_UDP = 0x20,
107 /* Indirection table consist of rx queue handles */
179 #define ECORE_ACCEPT_NONE 0x01
180 #define ECORE_ACCEPT_UCAST_MATCHED 0x02
[all …]
|