| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| H A D | xilinx_axienet.txt | 2 --------------------------------------------------------
7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
26 specified, the TX/RX DMA interrupts should be on that node
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| H A D | sff,sfp.txt | 1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
16 module presence input gpio signal, active (module absent) high. Must
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
20 Indication input gpio signal, active (signal lost) high
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
23 Fault input gpio signal, active (fault condition) high
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
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| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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| H A D | sff,sfp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_ec_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
86 /* [0x0] Rx FIFO input controller configuration 1 */
88 /* [0x4] Rx FIFO input controller configuration 2 */
90 /* [0x8] Threshold to start reading packet from the Rx FIFO */
92 /* [0xc] Threshold to stop writing packet to the Rx FIFO */
96 /* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
119 /* [0x20] Input result vector, default values for parser inpu ... */
121 /* [0x24] Result input vector selection */
214 /* [0x38] VLAN p-bits table address */
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| H A D | al_hal_eth_mac_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
307 struct al_eth_mac_10g_stats_v3_rx rx; member
560 /* [0x18] RX ASYNC FIFO configuration */
562 /* [0x1c] RX ASYNC FIFO configuration */
564 /* [0x20] RX ASYNC FIFO configuration */
566 /* [0x24] RX ASYNC FIFO configuration */
568 /* [0x28] RX ASYNC FIFO configuration */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
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| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
192 /** Rx descriptor configurations */
193 /* Note: when selecting rx descriptor field to inner packet, then that field
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | nxp,imx8mq-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
14 NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
15 input imaging devices.
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| H A D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
5 lanes in input, and 4 different pixel streams in output.
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | atmel-usart.txt | 4 - compatible: Should be one of the following:
5 - "atmel,at91rm9200-usart"
6 - "atmel,at91sam9260-usart"
7 - "microchip,sam9x60-usart"
8 - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"
9 - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
10 - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart"
11 - reg: Should contain registers location and length
12 - interrupts: Should contain interrupt
13 - clock-names: tuple listing input clock names.
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | atmel-ssc.txt | 4 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
7 - reg: Should contain SSC registers location and length
8 - interrupts: Should contain SSC interrupt
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 Required properties for devices compatible with "atmel,at91sam9g45-ssc":
15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
16 the memory interface and SSC DMA channel ID (for tx and rx).
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| /freebsd/sys/dev/usb/serial/ |
| H A D | umcs.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
70 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt
78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
107 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 &
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
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| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | at91-sama5d27_wlsom1_ek.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
9 /dts-v1/;
10 #include "at91-sama5d27_wlsom1.dtsi"
11 #include <dt-bindings/input/input
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | azoteq,iqs7222.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/azote
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | xilinx_can.txt | 2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
15 - "can_clk", "pclk" (For CANPS),
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| /freebsd/sys/contrib/device-tree/src/arm/xilinx/ |
| H A D | zynq-zc706.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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| H A D | zynq-zc702.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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| /freebsd/sys/crypto/openssl/arm/ |
| H A D | chacha-armv4.S | 1 /* Do not modify. This file is auto-generated from chacha-armv4.pl. */
21 .long 0x61707865,0x3320646e,0x79622d32,0x6b206574 @ endian-neutral
29 .word OPENSSL_armcap_P-.LChaCha20_ctr32
32 .word -1
41 stmdb sp!,{r0,r1,r2,r4-r11,lr}
56 ldr r4,[r14,#-32]
68 sub sp,sp,#4*(16) @ off-load area
75 str r10,[sp,#4*(16+10)] @ off-load "rx"
76 str r11,[sp,#4*(16+11)] @ off-load "rx"
87 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
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| /freebsd/contrib/libpcap/msdos/ |
| H A D | pkt_rx0.asm | 21 NUM_RX_BUF = 32 ; # of RX element buffers
41 ;-------------------------------------------
52 rxBuffer db RX_BUF_SIZE dup (0) ; RX buffer
60 _pktRxBuf RX_ELEMENT NUM_RX_BUF dup (<>) ; RX structures
66 fanChars db '-\|/'
78 mov es, bx ;; r-mode segment of colour screen
79 mov di, 158 ;; upper right corner - 1
90 ;------------------------------------------------------------------------
92 ; This macro return ES:DI to tail of Rx queue
96 mov ax, _rxInOfs ;; DI = current in-offset
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | fsl-imx-uart.txt | 4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
13 respectively, and that the peripheral should invert its output/input
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
11 input. The default is D0 as input and
15 - dmas: List of DMA specifiers with the controller specific format
16 as described in the generic DMA client binding. A tx and rx
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp15xx-dhcom-drc02.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-pat
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