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Searched +full:rockchip +full:- +full:dp +full:- +full:phy (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
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H A Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
22 "#phy-cells":
26 - compatible
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H A Drockchip,rk3399-typec-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Type-C PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-typec-phy
22 clock-names:
24 - const: tcpdcore
25 - const: tcpdphy-ref
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
5 * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
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H A Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
19 #include <linux/phy/phy.h>
28 /* USBDP PHY Register Definitions */
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
129 /* vo-grf */
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
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H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
11 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
396 struct phy *phy; member
409 /* used for dp mode */
693 /* voltage swing 0, pre-emphasis 0->3 */
701 /* voltage swing 1, pre-emphasis 0->2 */
708 /* voltage swing 2, pre-emphasis 0->1 */
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H A Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
21 #include <linux/phy/phy.h>
50 * enum usb_chg_state - Different states involved in USB charger detection.
89 * struct rockchip_chg_det_reg - usb charger detect registers
94 * @idp_sink_en: open dp sink current.
98 * @vdp_src_en: open dp voltage source.
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,rk3399-cdn-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 specific extensions to the CDN Display Port
10 - Andy Yan <andy.yan@rock-chip.com>
11 - Heiko Stuebner <heiko@sntech.de>
12 - Sandy Huang <hjc@rock-chips.com>
15 - $ref: /schemas/sound/dai-common.yaml#
20 - const: rockchip,rk3399-cdn-dp
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/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
27 #include "cdn-dp-core.h"
28 #include "cdn-dp-reg.h"
51 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
63 { .compatible = "rockchip,rk3399-cdn-dp",
70 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
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H A Dcdn-dp-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 * Author: Chris Zhong <zyw@rock-chips.com>
114 /* dptx phy addr */
175 /* dp aux addr */
400 #define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
401 #define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
403 #define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
404 #define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
454 void cdn_dp_clock_reset(struct cdn_dp_device *dp);
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3528-ioc-grf
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
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H A Drk3588-firefly-itx-3588j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3588-firefly-core-3588j.dtsi"
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H A Drk3588-mnt-reform2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-firefly-icore-3588q.dtsi"
19 compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588";
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H A Drk3588-evb2-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
7 /dts-v1/;
9 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
16 model = "Rockchip RK3588 EVB2 V10 Board";
17 compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588";
25 stdout-path = "serial2:1500000n8";
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H A Drk3588-turing-rk1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Based on RK3588-EVB1 devicetree
8 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
11 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
17 compatible = "turing,rk1", "rockchip,rk3588";
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
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H A Drk3588-evb1-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
17 model = "Rockchip RK3588 EVB1 V10 Board";
18 compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
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H A Drk3588s-indiedroid-nova.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
9 #include <dt-bindings/usb/pd.h>
14 compatible = "indiedroid,nova", "rockchip,rk3588s";
16 adc-keys-0 {
17 compatible = "adc-keys";
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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