| /linux/drivers/clk/zynq/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
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| /linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
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| /linux/drivers/media/i2c/ |
| H A D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
14 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
28 Clock Provider
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| H A D | silabs,si5351.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators
10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
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| H A D | fsl,qoriq-clock-legacy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
16 Most of the bindings are from the common clock binding[1].
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
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| H A D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
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| H A D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
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| H A D | starfive,jh7110-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
11 Each PLL works in integer mode or fraction mode, with configuration
13 SYS-SYSCON node.
14 The formula for calculating frequency is
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
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| H A D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
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| H A D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
12 - reg : should contain base register location and length.
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
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| /linux/drivers/clk/tegra/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_tspll.c | 1 // SPDX-License-Identifier: GPL-2.0
49 * ice_tspll_clk_freq_str - Convert time_ref_freq to string
50 * @clk_freq: Clock frequency
52 * Return: specified TIME_REF clock frequency converted to a string.
75 * ice_tspll_default_freq - Return default frequency for a MAC type
78 * Return: default TSPLL frequency for a correct MAC type, -ERANGE otherwise.
88 return -ERANGE; in ice_tspll_default_freq()
93 * ice_tspll_check_params - Check if TSPLL params are correct
95 * @clk_freq: Clock frequency to program
96 * @clk_src: Clock source to select (TIME_REF or TCXO)
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| /linux/drivers/clk/bcm/ |
| H A D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
43 * the PLL control register
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| H A D | clk-iproc-armpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
100 * There are 4 sources that can be used to derive the output clock rate:
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| /linux/drivers/clk/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Clock support for Amlogic platforms"
56 bool "Meson8 SoC Clock controller support"
66 Support for the clock controller on AmLogic S802 (Meson8),
68 want peripherals and CPU frequency scaling to work.
71 tristate "GXBB and GXL SoC clock controllers support"
83 Support for the clock controller on AmLogic S905 devices, aka gxbb.
84 Say Y if you want peripherals and CPU frequency scaling to work.
87 tristate "AXG SoC clock controllers support"
98 Support for the clock controller on AmLogic A113D devices, aka axg.
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| /linux/drivers/iio/frequency/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Frequency
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
10 menu "Frequency Synthesizers DDS/PLL"
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
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| /linux/drivers/clk/renesas/ |
| H A D | rcar-gen4-cpg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen4 Clock Pulse Generator
17 CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */
18 CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */
19 CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */
20 CLK_TYPE_GEN4_PLL_V9_24, /* Variable fractional 9.24 PLL */
73 #define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
74 #define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
75 #define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
76 #define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
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| /linux/include/uapi/linux/ |
| H A D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
35 * Revised status codes and structures for external clock and PPS
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
63 * to discipline kernel clock oscillator
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
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| /linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
10 * Each PLL clocks work in integer mode or fraction mode by some dividers,
12 * The formula for calculating frequency is:
14 * Fref: OSC source clock rate
15 * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
16 * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
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| /linux/include/linux/clk/ |
| H A D | at91_pmc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
20 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
21 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
23 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
24 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
25 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
27 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
9 The driver require a 25MHz Oscillator to function generate clock.
10 It includes PLLs, common clock function and some vendor clock for
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
19 frequency of 25 MHz as input, which are used for Main/Fixed
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_pixpll.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 * Loongson Pixel PLL hardware structure
14 * refclk: reference frequency, 100 MHz from external oscillator
15 * outclk: output frequency desired.
19 * refclk +-----------+ +------------------+ +---------+ outclk
20 * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
21 * | +-----------+ +------------------+ +---------+ ^
27 * +---- bypass (bypass above software configurable clock if set) ----+
31 * sel_out: PLL clock output selector(enable).
33 * If sel_out == 1, then enable output clock (turn On);
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| /linux/drivers/cpufreq/ |
| H A D | pxa3xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
36 #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
37 #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
38 #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
39 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
40 #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
42 #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
43 #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
44 #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */
45 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
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