1*f39db26cSSui Jingfeng /* SPDX-License-Identifier: GPL-2.0+ */ 2*f39db26cSSui Jingfeng /* 3*f39db26cSSui Jingfeng * Copyright (C) 2023 Loongson Technology Corporation Limited 4*f39db26cSSui Jingfeng */ 5*f39db26cSSui Jingfeng 6*f39db26cSSui Jingfeng #ifndef __LSDC_PIXPLL_H__ 7*f39db26cSSui Jingfeng #define __LSDC_PIXPLL_H__ 8*f39db26cSSui Jingfeng 9*f39db26cSSui Jingfeng #include <drm/drm_device.h> 10*f39db26cSSui Jingfeng 11*f39db26cSSui Jingfeng /* 12*f39db26cSSui Jingfeng * Loongson Pixel PLL hardware structure 13*f39db26cSSui Jingfeng * 14*f39db26cSSui Jingfeng * refclk: reference frequency, 100 MHz from external oscillator 15*f39db26cSSui Jingfeng * outclk: output frequency desired. 16*f39db26cSSui Jingfeng * 17*f39db26cSSui Jingfeng * 18*f39db26cSSui Jingfeng * L1 Fref Fvco L2 19*f39db26cSSui Jingfeng * refclk +-----------+ +------------------+ +---------+ outclk 20*f39db26cSSui Jingfeng * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | --------> 21*f39db26cSSui Jingfeng * | +-----------+ +------------------+ +---------+ ^ 22*f39db26cSSui Jingfeng * | ^ ^ ^ | 23*f39db26cSSui Jingfeng * | | | | | 24*f39db26cSSui Jingfeng * | | | | | 25*f39db26cSSui Jingfeng * | div_ref loopc div_out | 26*f39db26cSSui Jingfeng * | | 27*f39db26cSSui Jingfeng * +---- bypass (bypass above software configurable clock if set) ----+ 28*f39db26cSSui Jingfeng * 29*f39db26cSSui Jingfeng * outclk = refclk / div_ref * loopc / div_out; 30*f39db26cSSui Jingfeng * 31*f39db26cSSui Jingfeng * sel_out: PLL clock output selector(enable). 32*f39db26cSSui Jingfeng * 33*f39db26cSSui Jingfeng * If sel_out == 1, then enable output clock (turn On); 34*f39db26cSSui Jingfeng * If sel_out == 0, then disable output clock (turn Off); 35*f39db26cSSui Jingfeng * 36*f39db26cSSui Jingfeng * PLL working requirements: 37*f39db26cSSui Jingfeng * 38*f39db26cSSui Jingfeng * 1) 20 MHz <= refclk / div_ref <= 40Mhz 39*f39db26cSSui Jingfeng * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz 40*f39db26cSSui Jingfeng */ 41*f39db26cSSui Jingfeng 42*f39db26cSSui Jingfeng struct lsdc_pixpll_parms { 43*f39db26cSSui Jingfeng unsigned int ref_clock; 44*f39db26cSSui Jingfeng unsigned int div_ref; 45*f39db26cSSui Jingfeng unsigned int loopc; 46*f39db26cSSui Jingfeng unsigned int div_out; 47*f39db26cSSui Jingfeng }; 48*f39db26cSSui Jingfeng 49*f39db26cSSui Jingfeng struct lsdc_pixpll; 50*f39db26cSSui Jingfeng 51*f39db26cSSui Jingfeng struct lsdc_pixpll_funcs { 52*f39db26cSSui Jingfeng int (*setup)(struct lsdc_pixpll * const this); 53*f39db26cSSui Jingfeng 54*f39db26cSSui Jingfeng int (*compute)(struct lsdc_pixpll * const this, 55*f39db26cSSui Jingfeng unsigned int clock, 56*f39db26cSSui Jingfeng struct lsdc_pixpll_parms *pout); 57*f39db26cSSui Jingfeng 58*f39db26cSSui Jingfeng int (*update)(struct lsdc_pixpll * const this, 59*f39db26cSSui Jingfeng struct lsdc_pixpll_parms const *pin); 60*f39db26cSSui Jingfeng 61*f39db26cSSui Jingfeng unsigned int (*get_rate)(struct lsdc_pixpll * const this); 62*f39db26cSSui Jingfeng 63*f39db26cSSui Jingfeng void (*print)(struct lsdc_pixpll * const this, 64*f39db26cSSui Jingfeng struct drm_printer *printer); 65*f39db26cSSui Jingfeng }; 66*f39db26cSSui Jingfeng 67*f39db26cSSui Jingfeng struct lsdc_pixpll { 68*f39db26cSSui Jingfeng const struct lsdc_pixpll_funcs *funcs; 69*f39db26cSSui Jingfeng 70*f39db26cSSui Jingfeng struct drm_device *ddev; 71*f39db26cSSui Jingfeng 72*f39db26cSSui Jingfeng /* PLL register offset */ 73*f39db26cSSui Jingfeng u32 reg_base; 74*f39db26cSSui Jingfeng /* PLL register size in bytes */ 75*f39db26cSSui Jingfeng u32 reg_size; 76*f39db26cSSui Jingfeng 77*f39db26cSSui Jingfeng void __iomem *mmio; 78*f39db26cSSui Jingfeng 79*f39db26cSSui Jingfeng struct lsdc_pixpll_parms *priv; 80*f39db26cSSui Jingfeng }; 81*f39db26cSSui Jingfeng 82*f39db26cSSui Jingfeng int lsdc_pixpll_init(struct lsdc_pixpll * const this, 83*f39db26cSSui Jingfeng struct drm_device *ddev, 84*f39db26cSSui Jingfeng unsigned int index); 85*f39db26cSSui Jingfeng 86*f39db26cSSui Jingfeng #endif 87