Lines Matching +full:pll +full:- +full:clock +full:- +full:frequency

1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29  * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36  * Some PLLs require the PLL SW override bit to be set before changes can be
37  * applied to the PLL
42  * Some PLLs use a different way to control clock power, via the PWRDWN bit in
43  * the PLL control register
54  * Some PLLs have an additional divide by 2 in master clock calculation;
61  * Some PLLs provide a look up table for the leaf clock frequencies and
62  * auto calculates VCO frequency parameters based on the provided leaf
63  * clock frequencies. They have a user mode that allows the divider
74  * Calculate the PLL parameters are runtime, instead of using table
79  * Parameters for VCO frequency configuration
81  * VCO frequency =
82  * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency  / pdiv)
98  * Clock gating control at the top ASIU level
106  * Control of powering on/off of a PLL
108  * Before powering off a PLL, input isolation (ISO) needs to be enabled
118  * Control of the PLL reset
140  * To enable SW control of the PLL
153  * Main PLL control parameters
171  * Controls enabling/disabling a PLL derived clock
181  * Main clock control parameters for clocks derived from the PLLs