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/linux/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
11 PHYlink models the link between the PHY and MAC, allowing fixed
16 tristate "PHY Device support and infrastructure"
19 Ethernet controllers are usually attached to PHY
21 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
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H A Dadin1100.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Driver for Analog Devices Industrial Ethernet T1L PHYs
14 #include <linux/phy.h>
37 #define ADIN_IS_CFG_SLV BIT(2)
65 * struct adin_priv - ADIN PHY driver private data
66 * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
67 * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)
89 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in adin_read_status()
92 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in adin_read_status()
99 struct adin_priv *priv = phydev->priv; in adin_config_aneg()
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H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
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H A Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TD510 PHY
10 #include <linux/phy.h>
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
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/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin1110.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
14 PHY designed for industrial Ethernet applications. It integrates
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
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/linux/drivers/net/ethernet/adi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
21 tristate "Analog Devices ADIN1110 MAC-PHY"
27 Low Power 10BASE-T1L Ethernet MAC-PHY.
H A Dadin1110.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 /* ADIN1110 Low Power 10BASE-T1L Ethernet MAC-PHY
3 * ADIN2111 2-Port Ethernet Switch with Integrated 10BASE-T1L PHY
23 #include <linux/phy.h>
43 #define ADIN1110_FWD_UNK2HOST BIT(2)
49 #define ADIN1110_SPI_ERR BIT(10)
54 #define ADIN1110_SPI_ERR_IRQ BIT(10)
98 #define ADIN1110_WR_HEADER_LEN 2
99 #define ADIN1110_FRAME_HEADER_LEN 2
100 #define ADIN1110_INTERNAL_SIZE_HEADER_LEN 2
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/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/phy.h>
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
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/linux/Documentation/networking/
H A Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
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/linux/drivers/net/usb/
H A Dsmsc95xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2007-2008 SMSC
24 #include <linux/phy.h>
59 #define PHY_HWIRQ (SMSC95XX_NR_IRQS - 1)
88 struct smsc95xx_priv *pdata = dev->driver_priv; in smsc95xx_read_reg()
93 if (current != pdata->pm_task) in smsc95xx_read_reg()
102 ret = ret < 0 ? ret : -ENODATA; in smsc95xx_read_reg()
104 if (ret != -ENODEV) in smsc95xx_read_reg()
105 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n", in smsc95xx_read_reg()
119 struct smsc95xx_priv *pdata = dev->driver_priv; in smsc95xx_write_reg()
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