17eaf9132SAlexandru Ardelean // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
27eaf9132SAlexandru Ardelean /*
37eaf9132SAlexandru Ardelean * Driver for Analog Devices Industrial Ethernet T1L PHYs
47eaf9132SAlexandru Ardelean *
57eaf9132SAlexandru Ardelean * Copyright 2020 Analog Devices Inc.
67eaf9132SAlexandru Ardelean */
77eaf9132SAlexandru Ardelean #include <linux/kernel.h>
87eaf9132SAlexandru Ardelean #include <linux/bitfield.h>
97eaf9132SAlexandru Ardelean #include <linux/delay.h>
107eaf9132SAlexandru Ardelean #include <linux/errno.h>
117eaf9132SAlexandru Ardelean #include <linux/init.h>
127eaf9132SAlexandru Ardelean #include <linux/module.h>
137eaf9132SAlexandru Ardelean #include <linux/mii.h>
147eaf9132SAlexandru Ardelean #include <linux/phy.h>
157eaf9132SAlexandru Ardelean #include <linux/property.h>
167eaf9132SAlexandru Ardelean
177eaf9132SAlexandru Ardelean #define PHY_ID_ADIN1100 0x0283bc81
18875b718aSAlexandru Tachici #define PHY_ID_ADIN1110 0x0283bc91
19875b718aSAlexandru Tachici #define PHY_ID_ADIN2111 0x0283bca1
207eaf9132SAlexandru Ardelean
21*08b47dfdSAndre Werner #define ADIN_PHY_SUBSYS_IRQ_MASK 0x0021
22*08b47dfdSAndre Werner #define ADIN_LINK_STAT_CHNG_IRQ_EN BIT(1)
23*08b47dfdSAndre Werner
24*08b47dfdSAndre Werner #define ADIN_PHY_SUBSYS_IRQ_STATUS 0x0011
25*08b47dfdSAndre Werner #define ADIN_LINK_STAT_CHNG BIT(1)
26*08b47dfdSAndre Werner
277eaf9132SAlexandru Ardelean #define ADIN_FORCED_MODE 0x8000
287eaf9132SAlexandru Ardelean #define ADIN_FORCED_MODE_EN BIT(0)
297eaf9132SAlexandru Ardelean
307eaf9132SAlexandru Ardelean #define ADIN_CRSM_SFT_RST 0x8810
317eaf9132SAlexandru Ardelean #define ADIN_CRSM_SFT_RST_EN BIT(0)
327eaf9132SAlexandru Ardelean
337eaf9132SAlexandru Ardelean #define ADIN_CRSM_SFT_PD_CNTRL 0x8812
347eaf9132SAlexandru Ardelean #define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
357eaf9132SAlexandru Ardelean
367eaf9132SAlexandru Ardelean #define ADIN_AN_PHY_INST_STATUS 0x8030
377eaf9132SAlexandru Ardelean #define ADIN_IS_CFG_SLV BIT(2)
387eaf9132SAlexandru Ardelean #define ADIN_IS_CFG_MST BIT(3)
397eaf9132SAlexandru Ardelean
407eaf9132SAlexandru Ardelean #define ADIN_CRSM_STAT 0x8818
417eaf9132SAlexandru Ardelean #define ADIN_CRSM_SFT_PD_RDY BIT(1)
427eaf9132SAlexandru Ardelean #define ADIN_CRSM_SYS_RDY BIT(0)
437eaf9132SAlexandru Ardelean
4448f20f90SAlexandru Tachici #define ADIN_MSE_VAL 0x830B
4548f20f90SAlexandru Tachici
4648f20f90SAlexandru Tachici #define ADIN_SQI_MAX 7
4748f20f90SAlexandru Tachici
4848f20f90SAlexandru Tachici struct adin_mse_sqi_range {
4948f20f90SAlexandru Tachici u16 start;
5048f20f90SAlexandru Tachici u16 end;
5148f20f90SAlexandru Tachici };
5248f20f90SAlexandru Tachici
5348f20f90SAlexandru Tachici static const struct adin_mse_sqi_range adin_mse_sqi_map[] = {
5448f20f90SAlexandru Tachici { 0x0A74, 0xFFFF },
5548f20f90SAlexandru Tachici { 0x084E, 0x0A74 },
5648f20f90SAlexandru Tachici { 0x0698, 0x084E },
5748f20f90SAlexandru Tachici { 0x053D, 0x0698 },
5848f20f90SAlexandru Tachici { 0x0429, 0x053D },
5948f20f90SAlexandru Tachici { 0x034E, 0x0429 },
6048f20f90SAlexandru Tachici { 0x02A0, 0x034E },
6148f20f90SAlexandru Tachici { 0x0000, 0x02A0 },
6248f20f90SAlexandru Tachici };
6348f20f90SAlexandru Tachici
647eaf9132SAlexandru Ardelean /**
657eaf9132SAlexandru Ardelean * struct adin_priv - ADIN PHY driver private data
667eaf9132SAlexandru Ardelean * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
677eaf9132SAlexandru Ardelean * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)
687eaf9132SAlexandru Ardelean * @tx_level_prop_present: set if the TX level is specified in DT
697eaf9132SAlexandru Ardelean */
707eaf9132SAlexandru Ardelean struct adin_priv {
717eaf9132SAlexandru Ardelean unsigned int tx_level_2v4_able:1;
727eaf9132SAlexandru Ardelean unsigned int tx_level_2v4:1;
737eaf9132SAlexandru Ardelean unsigned int tx_level_prop_present:1;
747eaf9132SAlexandru Ardelean };
757eaf9132SAlexandru Ardelean
adin_read_status(struct phy_device * phydev)767eaf9132SAlexandru Ardelean static int adin_read_status(struct phy_device *phydev)
777eaf9132SAlexandru Ardelean {
787eaf9132SAlexandru Ardelean int ret;
797eaf9132SAlexandru Ardelean
807eaf9132SAlexandru Ardelean ret = genphy_c45_read_status(phydev);
817eaf9132SAlexandru Ardelean if (ret)
827eaf9132SAlexandru Ardelean return ret;
837eaf9132SAlexandru Ardelean
847eaf9132SAlexandru Ardelean ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
857eaf9132SAlexandru Ardelean if (ret < 0)
867eaf9132SAlexandru Ardelean return ret;
877eaf9132SAlexandru Ardelean
887eaf9132SAlexandru Ardelean if (ret & ADIN_IS_CFG_SLV)
897eaf9132SAlexandru Ardelean phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
907eaf9132SAlexandru Ardelean
917eaf9132SAlexandru Ardelean if (ret & ADIN_IS_CFG_MST)
927eaf9132SAlexandru Ardelean phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
937eaf9132SAlexandru Ardelean
947eaf9132SAlexandru Ardelean return 0;
957eaf9132SAlexandru Ardelean }
967eaf9132SAlexandru Ardelean
adin_config_aneg(struct phy_device * phydev)977eaf9132SAlexandru Ardelean static int adin_config_aneg(struct phy_device *phydev)
987eaf9132SAlexandru Ardelean {
997eaf9132SAlexandru Ardelean struct adin_priv *priv = phydev->priv;
1007eaf9132SAlexandru Ardelean int ret;
1017eaf9132SAlexandru Ardelean
1027eaf9132SAlexandru Ardelean if (phydev->autoneg == AUTONEG_DISABLE) {
1037eaf9132SAlexandru Ardelean ret = genphy_c45_pma_setup_forced(phydev);
1047eaf9132SAlexandru Ardelean if (ret < 0)
1057eaf9132SAlexandru Ardelean return ret;
1067eaf9132SAlexandru Ardelean
1077eaf9132SAlexandru Ardelean if (priv->tx_level_prop_present && priv->tx_level_2v4)
1087eaf9132SAlexandru Ardelean ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
1097eaf9132SAlexandru Ardelean MDIO_PMA_10T1L_CTRL_2V4_EN);
1107eaf9132SAlexandru Ardelean else
1117eaf9132SAlexandru Ardelean ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
1127eaf9132SAlexandru Ardelean MDIO_PMA_10T1L_CTRL_2V4_EN);
1137eaf9132SAlexandru Ardelean if (ret < 0)
1147eaf9132SAlexandru Ardelean return ret;
1157eaf9132SAlexandru Ardelean
1167eaf9132SAlexandru Ardelean /* Force PHY to use above configurations */
1177eaf9132SAlexandru Ardelean return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
1187eaf9132SAlexandru Ardelean }
1197eaf9132SAlexandru Ardelean
1207eaf9132SAlexandru Ardelean ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
1217eaf9132SAlexandru Ardelean if (ret < 0)
1227eaf9132SAlexandru Ardelean return ret;
1237eaf9132SAlexandru Ardelean
1247eaf9132SAlexandru Ardelean /* Request increased transmit level from LP. */
1257eaf9132SAlexandru Ardelean if (priv->tx_level_prop_present && priv->tx_level_2v4) {
1267eaf9132SAlexandru Ardelean ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
1277eaf9132SAlexandru Ardelean MDIO_AN_T1_ADV_H_10L_TX_HI |
1287eaf9132SAlexandru Ardelean MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
1297eaf9132SAlexandru Ardelean if (ret < 0)
1307eaf9132SAlexandru Ardelean return ret;
1317eaf9132SAlexandru Ardelean }
1327eaf9132SAlexandru Ardelean
1337eaf9132SAlexandru Ardelean /* Disable 2.4 Vpp transmit level. */
1347eaf9132SAlexandru Ardelean if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
1357eaf9132SAlexandru Ardelean ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
1367eaf9132SAlexandru Ardelean MDIO_AN_T1_ADV_H_10L_TX_HI |
1377eaf9132SAlexandru Ardelean MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
1387eaf9132SAlexandru Ardelean if (ret < 0)
1397eaf9132SAlexandru Ardelean return ret;
1407eaf9132SAlexandru Ardelean }
1417eaf9132SAlexandru Ardelean
1427eaf9132SAlexandru Ardelean return genphy_c45_config_aneg(phydev);
1437eaf9132SAlexandru Ardelean }
1447eaf9132SAlexandru Ardelean
adin_phy_ack_intr(struct phy_device * phydev)145*08b47dfdSAndre Werner static int adin_phy_ack_intr(struct phy_device *phydev)
146*08b47dfdSAndre Werner {
147*08b47dfdSAndre Werner /* Clear pending interrupts */
148*08b47dfdSAndre Werner int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2,
149*08b47dfdSAndre Werner ADIN_PHY_SUBSYS_IRQ_STATUS);
150*08b47dfdSAndre Werner
151*08b47dfdSAndre Werner return rc < 0 ? rc : 0;
152*08b47dfdSAndre Werner }
153*08b47dfdSAndre Werner
adin_config_intr(struct phy_device * phydev)154*08b47dfdSAndre Werner static int adin_config_intr(struct phy_device *phydev)
155*08b47dfdSAndre Werner {
156*08b47dfdSAndre Werner u16 irq_mask;
157*08b47dfdSAndre Werner int ret;
158*08b47dfdSAndre Werner
159*08b47dfdSAndre Werner ret = adin_phy_ack_intr(phydev);
160*08b47dfdSAndre Werner if (ret)
161*08b47dfdSAndre Werner return ret;
162*08b47dfdSAndre Werner
163*08b47dfdSAndre Werner if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
164*08b47dfdSAndre Werner irq_mask = ADIN_LINK_STAT_CHNG_IRQ_EN;
165*08b47dfdSAndre Werner else
166*08b47dfdSAndre Werner irq_mask = 0;
167*08b47dfdSAndre Werner
168*08b47dfdSAndre Werner return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
169*08b47dfdSAndre Werner ADIN_PHY_SUBSYS_IRQ_MASK,
170*08b47dfdSAndre Werner ADIN_LINK_STAT_CHNG_IRQ_EN, irq_mask);
171*08b47dfdSAndre Werner }
172*08b47dfdSAndre Werner
adin_phy_handle_interrupt(struct phy_device * phydev)173*08b47dfdSAndre Werner static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
174*08b47dfdSAndre Werner {
175*08b47dfdSAndre Werner int irq_status;
176*08b47dfdSAndre Werner
177*08b47dfdSAndre Werner irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2,
178*08b47dfdSAndre Werner ADIN_PHY_SUBSYS_IRQ_STATUS);
179*08b47dfdSAndre Werner if (irq_status < 0) {
180*08b47dfdSAndre Werner phy_error(phydev);
181*08b47dfdSAndre Werner return IRQ_NONE;
182*08b47dfdSAndre Werner }
183*08b47dfdSAndre Werner
184*08b47dfdSAndre Werner if (!(irq_status & ADIN_LINK_STAT_CHNG))
185*08b47dfdSAndre Werner return IRQ_NONE;
186*08b47dfdSAndre Werner
187*08b47dfdSAndre Werner phy_trigger_machine(phydev);
188*08b47dfdSAndre Werner
189*08b47dfdSAndre Werner return IRQ_HANDLED;
190*08b47dfdSAndre Werner }
191*08b47dfdSAndre Werner
adin_set_powerdown_mode(struct phy_device * phydev,bool en)1927eaf9132SAlexandru Ardelean static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
1937eaf9132SAlexandru Ardelean {
1947eaf9132SAlexandru Ardelean int ret;
1957eaf9132SAlexandru Ardelean int val;
1967eaf9132SAlexandru Ardelean
1977eaf9132SAlexandru Ardelean val = en ? ADIN_CRSM_SFT_PD_CNTRL_EN : 0;
1987eaf9132SAlexandru Ardelean ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1997eaf9132SAlexandru Ardelean ADIN_CRSM_SFT_PD_CNTRL, val);
2007eaf9132SAlexandru Ardelean if (ret < 0)
2017eaf9132SAlexandru Ardelean return ret;
2027eaf9132SAlexandru Ardelean
2037eaf9132SAlexandru Ardelean return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
2047eaf9132SAlexandru Ardelean (ret & ADIN_CRSM_SFT_PD_RDY) == val,
2057eaf9132SAlexandru Ardelean 1000, 30000, true);
2067eaf9132SAlexandru Ardelean }
2077eaf9132SAlexandru Ardelean
adin_suspend(struct phy_device * phydev)2087eaf9132SAlexandru Ardelean static int adin_suspend(struct phy_device *phydev)
2097eaf9132SAlexandru Ardelean {
2107eaf9132SAlexandru Ardelean return adin_set_powerdown_mode(phydev, true);
2117eaf9132SAlexandru Ardelean }
2127eaf9132SAlexandru Ardelean
adin_resume(struct phy_device * phydev)2137eaf9132SAlexandru Ardelean static int adin_resume(struct phy_device *phydev)
2147eaf9132SAlexandru Ardelean {
2157eaf9132SAlexandru Ardelean return adin_set_powerdown_mode(phydev, false);
2167eaf9132SAlexandru Ardelean }
2177eaf9132SAlexandru Ardelean
adin_set_loopback(struct phy_device * phydev,bool enable)2187eaf9132SAlexandru Ardelean static int adin_set_loopback(struct phy_device *phydev, bool enable)
2197eaf9132SAlexandru Ardelean {
2207eaf9132SAlexandru Ardelean if (enable)
2217eaf9132SAlexandru Ardelean return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
2227eaf9132SAlexandru Ardelean BMCR_LOOPBACK);
2237eaf9132SAlexandru Ardelean
2247eaf9132SAlexandru Ardelean /* PCS loopback (according to 10BASE-T1L spec) */
2257eaf9132SAlexandru Ardelean return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
2267eaf9132SAlexandru Ardelean BMCR_LOOPBACK);
2277eaf9132SAlexandru Ardelean }
2287eaf9132SAlexandru Ardelean
adin_soft_reset(struct phy_device * phydev)2297eaf9132SAlexandru Ardelean static int adin_soft_reset(struct phy_device *phydev)
2307eaf9132SAlexandru Ardelean {
2317eaf9132SAlexandru Ardelean int ret;
2327eaf9132SAlexandru Ardelean
2337eaf9132SAlexandru Ardelean ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
2347eaf9132SAlexandru Ardelean if (ret < 0)
2357eaf9132SAlexandru Ardelean return ret;
2367eaf9132SAlexandru Ardelean
2377eaf9132SAlexandru Ardelean return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
2387eaf9132SAlexandru Ardelean (ret & ADIN_CRSM_SYS_RDY),
2397eaf9132SAlexandru Ardelean 10000, 30000, true);
2407eaf9132SAlexandru Ardelean }
2417eaf9132SAlexandru Ardelean
adin_get_features(struct phy_device * phydev)2427eaf9132SAlexandru Ardelean static int adin_get_features(struct phy_device *phydev)
2437eaf9132SAlexandru Ardelean {
2447eaf9132SAlexandru Ardelean struct adin_priv *priv = phydev->priv;
2457eaf9132SAlexandru Ardelean struct device *dev = &phydev->mdio.dev;
2467eaf9132SAlexandru Ardelean int ret;
2477eaf9132SAlexandru Ardelean u8 val;
2487eaf9132SAlexandru Ardelean
2497eaf9132SAlexandru Ardelean ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
2507eaf9132SAlexandru Ardelean if (ret < 0)
2517eaf9132SAlexandru Ardelean return ret;
2527eaf9132SAlexandru Ardelean
2537eaf9132SAlexandru Ardelean /* This depends on the voltage level from the power source */
2547eaf9132SAlexandru Ardelean priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
2557eaf9132SAlexandru Ardelean
2567eaf9132SAlexandru Ardelean phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
2577eaf9132SAlexandru Ardelean priv->tx_level_2v4_able ? "yes" : "no");
2587eaf9132SAlexandru Ardelean
2597eaf9132SAlexandru Ardelean priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");
2607eaf9132SAlexandru Ardelean if (priv->tx_level_prop_present) {
2617eaf9132SAlexandru Ardelean ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);
2627eaf9132SAlexandru Ardelean if (ret < 0)
2637eaf9132SAlexandru Ardelean return ret;
2647eaf9132SAlexandru Ardelean
2657eaf9132SAlexandru Ardelean priv->tx_level_2v4 = val;
2667eaf9132SAlexandru Ardelean if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
2677eaf9132SAlexandru Ardelean phydev_info(phydev,
2687eaf9132SAlexandru Ardelean "PHY supports 2.4V TX level, but disabled via config\n");
2697eaf9132SAlexandru Ardelean }
2707eaf9132SAlexandru Ardelean
2717eaf9132SAlexandru Ardelean linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
2727eaf9132SAlexandru Ardelean phydev->supported);
2737eaf9132SAlexandru Ardelean
2747eaf9132SAlexandru Ardelean return genphy_c45_pma_read_abilities(phydev);
2757eaf9132SAlexandru Ardelean }
2767eaf9132SAlexandru Ardelean
adin_get_sqi(struct phy_device * phydev)27748f20f90SAlexandru Tachici static int adin_get_sqi(struct phy_device *phydev)
27848f20f90SAlexandru Tachici {
27948f20f90SAlexandru Tachici u16 mse_val;
28048f20f90SAlexandru Tachici int sqi;
28148f20f90SAlexandru Tachici int ret;
28248f20f90SAlexandru Tachici
28348f20f90SAlexandru Tachici ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
28448f20f90SAlexandru Tachici if (ret < 0)
28548f20f90SAlexandru Tachici return ret;
28648f20f90SAlexandru Tachici else if (!(ret & MDIO_STAT1_LSTATUS))
28748f20f90SAlexandru Tachici return 0;
28848f20f90SAlexandru Tachici
28948f20f90SAlexandru Tachici ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);
29048f20f90SAlexandru Tachici if (ret < 0)
29148f20f90SAlexandru Tachici return ret;
29248f20f90SAlexandru Tachici
29348f20f90SAlexandru Tachici mse_val = 0xFFFF & ret;
29448f20f90SAlexandru Tachici for (sqi = 0; sqi < ARRAY_SIZE(adin_mse_sqi_map); sqi++) {
29548f20f90SAlexandru Tachici if (mse_val >= adin_mse_sqi_map[sqi].start && mse_val <= adin_mse_sqi_map[sqi].end)
29648f20f90SAlexandru Tachici return sqi;
29748f20f90SAlexandru Tachici }
29848f20f90SAlexandru Tachici
29948f20f90SAlexandru Tachici return -EINVAL;
30048f20f90SAlexandru Tachici }
30148f20f90SAlexandru Tachici
adin_get_sqi_max(struct phy_device * phydev)30248f20f90SAlexandru Tachici static int adin_get_sqi_max(struct phy_device *phydev)
30348f20f90SAlexandru Tachici {
30448f20f90SAlexandru Tachici return ADIN_SQI_MAX;
30548f20f90SAlexandru Tachici }
30648f20f90SAlexandru Tachici
adin_probe(struct phy_device * phydev)3077eaf9132SAlexandru Ardelean static int adin_probe(struct phy_device *phydev)
3087eaf9132SAlexandru Ardelean {
3097eaf9132SAlexandru Ardelean struct device *dev = &phydev->mdio.dev;
3107eaf9132SAlexandru Ardelean struct adin_priv *priv;
3117eaf9132SAlexandru Ardelean
3127eaf9132SAlexandru Ardelean priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3137eaf9132SAlexandru Ardelean if (!priv)
3147eaf9132SAlexandru Ardelean return -ENOMEM;
3157eaf9132SAlexandru Ardelean
3167eaf9132SAlexandru Ardelean phydev->priv = priv;
3177eaf9132SAlexandru Ardelean
3187eaf9132SAlexandru Ardelean return 0;
3197eaf9132SAlexandru Ardelean }
3207eaf9132SAlexandru Ardelean
3217eaf9132SAlexandru Ardelean static struct phy_driver adin_driver[] = {
3227eaf9132SAlexandru Ardelean {
323875b718aSAlexandru Tachici .phy_id = PHY_ID_ADIN1100,
324875b718aSAlexandru Tachici .phy_id_mask = 0xffffffcf,
3257eaf9132SAlexandru Ardelean .name = "ADIN1100",
3267eaf9132SAlexandru Ardelean .get_features = adin_get_features,
3277eaf9132SAlexandru Ardelean .soft_reset = adin_soft_reset,
3287eaf9132SAlexandru Ardelean .probe = adin_probe,
3297eaf9132SAlexandru Ardelean .config_aneg = adin_config_aneg,
3307eaf9132SAlexandru Ardelean .read_status = adin_read_status,
331*08b47dfdSAndre Werner .config_intr = adin_config_intr,
332*08b47dfdSAndre Werner .handle_interrupt = adin_phy_handle_interrupt,
3337eaf9132SAlexandru Ardelean .set_loopback = adin_set_loopback,
3347eaf9132SAlexandru Ardelean .suspend = adin_suspend,
3357eaf9132SAlexandru Ardelean .resume = adin_resume,
33648f20f90SAlexandru Tachici .get_sqi = adin_get_sqi,
33748f20f90SAlexandru Tachici .get_sqi_max = adin_get_sqi_max,
3387eaf9132SAlexandru Ardelean },
3397eaf9132SAlexandru Ardelean };
3407eaf9132SAlexandru Ardelean
3417eaf9132SAlexandru Ardelean module_phy_driver(adin_driver);
3427eaf9132SAlexandru Ardelean
3437eaf9132SAlexandru Ardelean static struct mdio_device_id __maybe_unused adin_tbl[] = {
3447eaf9132SAlexandru Ardelean { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
345875b718aSAlexandru Tachici { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1110) },
346875b718aSAlexandru Tachici { PHY_ID_MATCH_MODEL(PHY_ID_ADIN2111) },
3477eaf9132SAlexandru Ardelean { }
3487eaf9132SAlexandru Ardelean };
3497eaf9132SAlexandru Ardelean
3507eaf9132SAlexandru Ardelean MODULE_DEVICE_TABLE(mdio, adin_tbl);
3517eaf9132SAlexandru Ardelean MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
3527eaf9132SAlexandru Ardelean MODULE_LICENSE("Dual BSD/GPL");
353