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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-fw-isys.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2013--2024 Intel Corporation */
30 /* Single device queue for high priority commands (bypass in-order queue) */
161 * supports up to 4 virtual per physical channel
184 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */
185 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */
186 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */
187 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */
189 IPU6_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */
222 * if not, then only option is to capture it with pin type MIPI.
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
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H A Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
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H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
10 - Tony Lindgren <tony@atomide.com>
13 Some pin controller devices use a single register for one or more pins. The
14 range of pin control registers can vary from one to many for each controller
16 kind of pin controller instances.
21 - enum:
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H A Dpinctrl-rk805.txt5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
7 including the meaning of the phrase "pin configuration node".
10 --------------------------
13 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
14 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
15 <pinctrl-bindings.txt>.
17 The pin configurations are defined as child of the pinctrl states node. Each
18 sub-node have following properties:
21 ------------------
22 - #gpio-cells: Should be two. The first cell is the pin number and the
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H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
6 controlled are organized in groups, so no actual pin information is
9 A pin-controller node should contain subnodes representing the pin group
10 configurations, one per function. Each subnode has the group name and
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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/linux/include/uapi/sound/
H A Dsnd_sst_tokens.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * snd_sst_tokens.h - Intel SST tokens definition
17 * %SKL_TKN_U8_IN_PIN_TYPE: Input pin type,
20 * %SKL_TKN_U8_OUT_PIN_TYPE: Output pin type,
22 * %SKL_TKN_U8_DYN_IN_PIN: Configure Input pin dynamically
25 * %SKL_TKN_U8_DYN_OUT_PIN: Configure Output pin dynamically
65 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
96 * formats and the pin count.
99 * the pin count value.
118 * %SKL_TKN_U32_FMT_INTERLEAVE: Interleaving style which can be per
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/linux/include/linux/pinctrl/
H A Dpinconf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 * struct pinconf_ops - pin config operations, to be implemented by
21 * pin configuration capable drivers.
22 * @is_generic: for pin controllers that want to use the generic interface,
24 * @pin_config_get: get the config of a certain pin, if the requested config
25 * is not available on this controller this should return -ENOTSUPP
26 * and if it is available but disabled it should return -EINVAL
27 * @pin_config_set: configure an individual pin
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H A Dpinctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
30 * struct pingroup - provides information on pingroup
50 * struct pinctrl_pin_desc - boards/machines provide information on their
52 * @number: unique pin number from the global pin number space
53 * @name: a name for this pin
54 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
62 /* Convenience macro to define a single named or anonymous pin descriptor */
67 * struct pinctrl_gpio_range - each pin controller can provide subranges of
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/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
67 * enum - Special treatment for GPIO base in pad group
71 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
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H A Dpinctrl-lynxpoint.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
152 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
153 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
158 /* Each pin has two 32 bit config registers, starting at 0x100 */
181 * per gpio specific registers. The bitmapped registers are in chunks of
184 * per gpio specific registers consist of two 32bit registers per gpio
190 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
191 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
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/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Pin controller and GPIO driver for Amlogic Meson SoCs
20 * struct meson_pmx_group - a pinmux group
38 * struct meson_pmx_func - a pinmux function
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
78 * enum meson_pinconf_drv - value of drive-strength supported
91 * @first: first pin of the bank
92 * @last: last pin of the bank
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/linux/include/linux/
H A Dptp_clock_kernel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct ptp_clock_request - request PTP clock event
47 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
50 * @clockid: clock-base used for capturing the system timestamps
59 * struct ptp_clock_info - describes a PTP hardware clock
65 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
79 * nominal frequency in parts per million, but with a
145 * @verify: Confirm that a pin can perform a given function. The PTP
148 * assumes that every pin can perform every function. This
151 * zero if the function can be assigned to this pin, and
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dadi,adv7511.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
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/linux/arch/arm/mach-s3c/
H A Dgpio-samsung.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
58 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
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/linux/drivers/pinctrl/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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H A Dpinctrl-single.c2 * Generic device tree based pinctrl driver for one register per pin
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
84 * @conf: array of pin configurations
85 * @nconfs: number of pin configurations available
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H A Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin config portions of the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
29 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
32 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
33 dev_err(pctldev->dev, in pinconf_check_ops()
35 return -EINVAL; in pinconf_check_ops()
42 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
43 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
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/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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/linux/Documentation/devicetree/bindings/usb/
H A Dbrcm,usb-pinmap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom USB pin map Controller
10 - Al Cooper <alcooperx@gmail.com>
15 - const: brcm,usb-pinmap
22 description: Interrupt for signals mirrored to out-gpios.
24 in-gpios:
29 brcm,in-functions:
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/linux/drivers/auxdisplay/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 # see Documentation/kbuild/kconfig-language.rst.
25 This is the base system for character-based LCD displays.
67 Say Y here if you have an HD44780 or KS-0074 LCD connected to your
68 parallel port. This driver also features 4 and 6-key keypads. The LCD
88 int "Default panel profile (0-5, 0=custom)"
99 2 = 2x16 serial LCD (KS-0074), new keypad
119 2 : new 6 keys keypad, as used on the server at www.ant-computing.com
140 3 : 2x16 serial LCD (KS-0074 based)
150 int "Number of lines on the LCD (1-2)"
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/linux/Documentation/scsi/
H A Daic79xx.rst1 .. SPDX-License-Identifier: GPL-2.0
28 AIC-7901A Single Channel 64-bit PCI-X 133MHz to
30 AIC-7901B Single Channel 64-bit PCI-X 133MHz to
32 AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to
34 AIC-7902B Dual Channel 64-bit PCI-X 133MHz to
41 Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B
43 68-pin, two internal 68-pin)
44 Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B
46 68-pin, two internal 68-pin)
47 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
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/linux/Documentation/userspace-api/media/cec/
H A Dcec-ioc-dqevent.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_DQEVENT - Dequeue a CEC event
35 non-blocking mode and no event is pending, then it will return -1 and
38 The internal event queues are per-filehandle and per-event type. If
43 two :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` events with
51 .. flat-table:: struct cec_event_state_change
52 :header-rows: 0
53 :stub-columns: 0
56 * - __u16
57 - ``phys_addr``
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