Lines Matching +full:per +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
20 Up to 8 different alternate function modes exist for each single pin.
25 - const: renesas,r7s72100-ports # RZ/A1H
26 - items:
27 - const: renesas,r7s72101-ports # RZ/A1M
28 - const: renesas,r7s72100-ports # fallback
29 - const: renesas,r7s72102-ports # RZ/A1L
35 - $ref: pinctrl.yaml#
38 - compatible
39 - reg
42 "^gpio-[0-9]*$":
47 Each port of the r7s72100 pin controller hardware is itself a GPIO
49 Different SoCs have different numbers of available pins per port, but
52 Describe GPIO controllers using sub-nodes with the following properties.
55 gpio-controller: true
57 '#gpio-cells':
60 gpio-ranges:
64 - gpio-controller
65 - '#gpio-cells'
66 - gpio-ranges
71 - type: object
73 - $ref: pincfg-node.yaml#
74 - $ref: pinmux-node.yaml#
77 A pin multiplexing sub-node describes how to configure a set of (or a
78 single) pin in some desired alternate function mode.
79 A single sub-node may define several pin configurations.
80 A few alternate function require special pin configuration flags to be
82 The hardware reference manual specifies when a pin function requires
85 file to instruct the pin controller to perform the desired pin
87 The hardware reference manual specifies when a pin has to be configured
88 to work in bi-directional mode and when the IO direction has to be
89 specified by software. Bi-directional pins must be managed by the pin
96 Integer array representing pin number and pin multiplexing
98 When a pin has to be configured in alternate function mode, use
99 this property to identify the pin by its global index, and provide
104 Helper macros to ease assembling the pin index from its position
105 (port where it sits on and pin number) and alternate function
106 identifier are provided by the pin controller header file at:
107 <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
109 ((PORT * 16 + PIN) | MUX_FUNC << 16)
111 input-enable: true
112 output-enable: true
115 - pinmux
119 - type: object
124 - |
125 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
127 compatible = "renesas,r7s72100-ports";
133 * The GPIO controller base in the global pin indexing space is pin
134 * 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
135 * in the global pin indexing space.
137 port3: gpio-3 {
138 gpio-controller;
139 #gpio-cells = <2>;
140 gpio-ranges = <&pinctrl 0 48 16>;
144 * A serial communication interface with a TX output pin and an RX
145 * input pin.
146 * Pin #0 on port #3 is configured as alternate function #6.
147 * Pin #2 on port #3 is configured as alternate function #4.
155 * I2c master: both SDA and SCL pins need bi-directional operations
156 * Pin #4 on port #1 is configured as alternate function #1.
157 * Pin #5 on port #1 is configured as alternate function #1.
158 * Both need to work in bi-directional mode, the driver must manage
167 * Multi-function timer input and output compare pins.
172 * Pin #0 on port #4 is configured as alternate function #2
177 input-enable;
182 * Pin #1 on port #4 is configured as alternate function #1
187 output-enable;