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/linux/Documentation/devicetree/bindings/clock/
H A Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 clock generators providing from 3 to 12 output clocks.
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
[all …]
/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
20 * @M88DS3103_TS_SERIAL: TS output pin D0, normal
21 * @M88DS3103_TS_SERIAL_D7: TS output pin D7
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
57 * @clk_out: Clock output.
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-kukui-jacuzzi.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "mt8183-kukui.dtsi"
7 /* Must come after mt8183-kukui.dtsi to modify cros_ec */
8 #include <arm/cros-ec-keyboard.dtsi>
11 pp1200_mipibrdg: pp1200-mipibrdg {
12 compatible = "regulator-fixed";
13 regulator-name = "pp1200_mipibrdg";
14 pinctrl-names = "default";
15 pinctrl-0 = <&pp1200_mipibrdg_en>;
17 enable-active-high;
[all …]
H A Dmt8390-genio-700-evk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Author: Chris Chen <chris-qj.chen@mediatek.com>
8 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
16 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
17 #include <dt-bindings/spmi/spmi.h>
18 #include <dt-bindings/usb/pd.h>
[all …]
H A Dmt8183-kukui-kakadu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "mt8183-kukui.dtsi"
7 #include <dt-bindings/input/gpio-keys.h>
10 ppvarn_lcd: ppvarn-lcd {
11 compatible = "regulator-fixed";
12 regulator-name = "ppvarn_lcd";
13 pinctrl-names = "default";
14 pinctrl-0 = <&ppvarn_lcd_en>;
16 enable-active-high;
21 ppvarp_lcd: ppvarp-lcd {
[all …]
H A Dmt8186-corsola-steelix.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 pp1000_edpbrdg: regulator-pp1000-edpbrdg {
13 compatible = "regulator-fixed";
14 regulator-name = "pp1000_edpbrdg";
15 pinctrl-names = "default";
16 pinctrl-0 = <&en_pp1000_edpbrdg>;
[all …]
H A Dmt8183-kukui-kodama.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
11 ppvarn_lcd: ppvarn-lcd {
12 compatible = "regulator-fixed";
13 regulator-name = "ppvarn_lcd";
14 pinctrl-names = "default";
15 pinctrl-0 = <&ppvarn_lcd_en>;
17 enable-active-high;
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H A Dmt8183-kukui-krane.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "mt8183-kukui.dtsi"
7 #include "mt8183-kukui-audio-max98357a.dtsi"
10 ppvarn_lcd: ppvarn-lcd {
11 compatible = "regulator-fixed";
12 regulator-name = "ppvarn_lcd";
13 pinctrl-names = "default";
14 pinctrl-0 = <&ppvarn_lcd_en>;
16 enable-active-high;
21 ppvarp_lcd: ppvarp-lcd {
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/linux/drivers/media/platform/ti/omap3isp/
H A Disppreview.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP driver - Preview module
26 { /* RGB-RGB Matrix */
38 {-38, -75, 112},
39 {112, -94 , -18}
85 * -------------------------------------------------------------
125 * Default Gamma Correction Table - All components
146 * preview_config_luma_enhancement - Configure the Luminance Enhancement table
153 const struct omap3isp_prev_luma *yt = &params->luma; in preview_config_luma_enhancement()
159 isp_reg_writel(isp, yt->table[i], in preview_config_luma_enhancement()
[all …]
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
36 * 0 - Active high, 1 - Active low
[all …]
/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
14 individual input and output hardware signals known as triggers to and from
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
31 channels. When an input trigger becomes active, the attached channel will
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l41.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - david.rhodes@cirrus.com
19 - cirrus,cs35l40
20 - cirrus,cs35l41
28 '#sound-dai-cells':
33 reset-gpios:
36 VA-supply:
39 VP-supply:
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/linux/drivers/watchdog/
H A Dwd501p.h1 /* SPDX-License-Identifier: GPL-1.0+ */
25 #define WDT_BUZZER (io+6) /* PCI only: rd=disable, wr=enable */
31 /* inverted opto isolated reset output: */
32 #define WDT_OPTONOTRST (io+13) /* wr=enable, rd=disable */
33 /* opto isolated reset output: */
34 #define WDT_OPTORST (io+14) /* wr=enable, rd=disable */
36 #define WDT_PROGOUT (io+15) /* wr=enable, rd=disable */
39 #define WDC_SR_WCCR 1 /* Active low */ /* X X X */
40 #define WDC_SR_TGOOD 2 /* X X - */
43 #define WDC_SR_FANGOOD 16 /* X - - */
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/linux/Documentation/admin-guide/media/
H A Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
33 | 1 - FPDL3
34 | 2 - GMSL
42 PRODUCT-REVISION-SERIES-SERIAL
53 Number of deserializer output lanes.
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-tqma9352-mba93xxca.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
15 #include "imx93-tqma9352.dtsi"
18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Daptina,mt9v111.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo@jmondi.org>
13 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
16 The sensor has an active pixel array of 640x480 pixels and can output a number
17 of image resolutions and formats controllable through a simple two-wires
30 enable-gpios:
31 description: Enable signal, pin name "OE#". Active low.
34 standby-gpios:
[all …]
/linux/Documentation/devicetree/bindings/power/supply/
H A Dmaxim,max8903.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
19 dok-gpios:
21 description: Valid DC power has been detected (active low, input)
23 uok-gpios:
25 description: Valid USB power has been detected (active low, input)
27 cen-gpios:
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
[all …]
H A Dti,tps65132.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI TPS65132 Dual Output Power Regulators
10 - devicetree@vger.kernel.org
21 - ti,tps65132
26 vin-supply: true
37 enable-gpios:
40 GPIO specifier to enable the GPIO control (on/off) for regulator.
42 active-discharge-gpios:
[all …]
/linux/Documentation/trace/
H A Dintel_th.rst1 .. SPDX-License-Identifier: GPL-2.0
8 --------
11 switch and output trace data from multiple hardware and software
12 sources over several types of trace output ports encoded in System
23 - Software Trace Hub (STH), trace source, which is a System Trace
25 - Memory Storage Unit (MSU), trace output, which allows storing
26 trace hub output in system memory,
27 - Parallel Trace Interface output (PTI), trace output to an external
29 - Global Trace Hub (GTH), which is a switch and a central component
32 Common attributes for output devices are described in
[all …]
/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
69 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
71 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
80 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
[all …]
/linux/drivers/power/supply/
H A Dmax8903_charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max8903_charger.c - Maxim 8903 USB/Adapter Charger Driver
27 struct gpio_desc *cen; /* Charger Enable input */
28 struct gpio_desc *dok; /* DC (Adapter) Power OK output */
29 struct gpio_desc *uok; /* USB Power OK output */
30 struct gpio_desc *chg; /* Charger status output */
31 struct gpio_desc *flt; /* Fault output */
32 struct gpio_desc *dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
40 POWER_SUPPLY_PROP_STATUS, /* Charger status output */
53 val->intval = POWER_SUPPLY_STATUS_UNKNOWN; in max8903_get_property()
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
/linux/drivers/net/phy/
H A Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
40 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
54 #define BC_WRITE (1<<11) /* Broadcast Write Enable */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
66 #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
75 #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
76 #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
77 #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "pxa-regs.h"
12 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
13 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
15 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
17 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
18 Enable */
19 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
20 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
22 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
[all …]

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