Lines Matching +full:output +full:- +full:enable +full:- +full:active
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 clock generators providing from 3 to 12 output clocks.
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
23 1 -- OUT1
24 2 -- OUT4
26 - other parts:
27 0 -- OUT0_SEL_I2CB
28 1 -- OUT1
29 2 -- OUT2
30 3 -- OUT3
31 4 -- OUT4
33 The idt,shutdown and idt,output-enable-active properties control the
38 SH SP Output when the SD/OE pin is Low/High
40 0 0 Active/Inactive
41 0 1 Inactive/Active
42 1 0 Active/Shutdown
48 - Luca Ceresoli <luca.ceresoli@bootlin.com>
53 - idt,5p49v5923
54 - idt,5p49v5925
55 - idt,5p49v5933
56 - idt,5p49v5935
57 - idt,5p49v60
58 - idt,5p49v6901
59 - idt,5p49v6965
60 - idt,5p49v6975
66 '#clock-cells':
69 clock-names:
78 idt,xtal-load-femtofarads:
93 idt,output-enable-active:
97 If 1, this enables output when the SD/OE pin is high, and disables
98 output when the SD/OE pin is low. If 0, this disables output when
99 the SD/OE pin is high, and enables output when the SD/OE pin is
104 "^OUT[1-4]$":
107 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
113 The output drive mode. Values defined in dt-bindings/clock/versaclock.h
117 idt,voltage-microvolt:
118 description: The output drive voltage.
120 idt,slew-percent:
121 description: The Slew rate control for CMOS single-ended.
126 - compatible
127 - reg
128 - '#clock-cells'
131 - if:
135 - idt,5p49v5933
136 - idt,5p49v5935
137 - idt,5p49v6975
141 clock-names:
148 - clock-names
149 - clocks
154 - |
155 #include <dt-bindings/clock/versaclock.h>
159 compatible = "fixed-clock";
160 #clock-cells = <0>;
161 clock-frequency = <25000000>;
166 #address-cells = <1>;
167 #size-cells = <0>;
170 vc5: clock-generator@6a {
173 #clock-cells = <1>;
177 clock-names = "xin";
181 idt,output-enable-active = <0>;
185 idt,voltage-microvolt = <1800000>;
186 idt,slew-percent = <80>;