Lines Matching +full:output +full:- +full:enable +full:- +full:active
1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
40 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
54 #define BC_WRITE (1<<11) /* Broadcast Write Enable */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
66 #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
75 #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
76 #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
77 #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
78 #define EVENT_IE (1<<0) /* Event Interrupt Enable */
82 #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
84 #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
86 #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
88 #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
90 #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
92 #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
94 #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
96 #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
101 #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
107 #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit word…
137 #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
138 #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
140 #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
146 #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
147 #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
148 #define EVNT_SINGLE (1<<12) /* enable single event capture operation */
149 #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
158 #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
159 #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
160 #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
161 #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation …
162 #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
163 #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
164 #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
165 #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
166 #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
168 #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
182 #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
183 #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
184 #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
185 #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
186 #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
187 #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
188 #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
191 #define DOMAIN_EN (1<<15) /* Domain Match Enable */
194 #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
196 #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
198 #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
199 #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
200 #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
201 #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
203 #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
212 #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
217 #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
222 #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
223 #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
232 #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
233 #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
234 #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
235 #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
249 #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
251 #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */