1*ceafdaacSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */ 2*ceafdaacSMauro Carvalho Chehab /* 3*ceafdaacSMauro Carvalho Chehab * omap3isp.h 4*ceafdaacSMauro Carvalho Chehab * 5*ceafdaacSMauro Carvalho Chehab * TI OMAP3 ISP - Bus Configuration 6*ceafdaacSMauro Carvalho Chehab * 7*ceafdaacSMauro Carvalho Chehab * Copyright (C) 2011 Nokia Corporation 8*ceafdaacSMauro Carvalho Chehab * 9*ceafdaacSMauro Carvalho Chehab * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*ceafdaacSMauro Carvalho Chehab * Sakari Ailus <sakari.ailus@iki.fi> 11*ceafdaacSMauro Carvalho Chehab */ 12*ceafdaacSMauro Carvalho Chehab 13*ceafdaacSMauro Carvalho Chehab #ifndef __OMAP3ISP_H__ 14*ceafdaacSMauro Carvalho Chehab #define __OMAP3ISP_H__ 15*ceafdaacSMauro Carvalho Chehab 16*ceafdaacSMauro Carvalho Chehab enum isp_interface_type { 17*ceafdaacSMauro Carvalho Chehab ISP_INTERFACE_PARALLEL, 18*ceafdaacSMauro Carvalho Chehab ISP_INTERFACE_CSI2A_PHY2, 19*ceafdaacSMauro Carvalho Chehab ISP_INTERFACE_CCP2B_PHY1, 20*ceafdaacSMauro Carvalho Chehab ISP_INTERFACE_CCP2B_PHY2, 21*ceafdaacSMauro Carvalho Chehab ISP_INTERFACE_CSI2C_PHY1, 22*ceafdaacSMauro Carvalho Chehab }; 23*ceafdaacSMauro Carvalho Chehab 24*ceafdaacSMauro Carvalho Chehab /** 25*ceafdaacSMauro Carvalho Chehab * struct isp_parallel_cfg - Parallel interface configuration 26*ceafdaacSMauro Carvalho Chehab * @data_lane_shift: Data lane shifter 27*ceafdaacSMauro Carvalho Chehab * 0 - CAMEXT[13:0] -> CAM[13:0] 28*ceafdaacSMauro Carvalho Chehab * 2 - CAMEXT[13:2] -> CAM[11:0] 29*ceafdaacSMauro Carvalho Chehab * 4 - CAMEXT[13:4] -> CAM[9:0] 30*ceafdaacSMauro Carvalho Chehab * 6 - CAMEXT[13:6] -> CAM[7:0] 31*ceafdaacSMauro Carvalho Chehab * @clk_pol: Pixel clock polarity 32*ceafdaacSMauro Carvalho Chehab * 0 - Sample on rising edge, 1 - Sample on falling edge 33*ceafdaacSMauro Carvalho Chehab * @hs_pol: Horizontal synchronization polarity 34*ceafdaacSMauro Carvalho Chehab * 0 - Active high, 1 - Active low 35*ceafdaacSMauro Carvalho Chehab * @vs_pol: Vertical synchronization polarity 36*ceafdaacSMauro Carvalho Chehab * 0 - Active high, 1 - Active low 37*ceafdaacSMauro Carvalho Chehab * @fld_pol: Field signal polarity 38*ceafdaacSMauro Carvalho Chehab * 0 - Positive, 1 - Negative 39*ceafdaacSMauro Carvalho Chehab * @data_pol: Data polarity 40*ceafdaacSMauro Carvalho Chehab * 0 - Normal, 1 - One's complement 41*ceafdaacSMauro Carvalho Chehab * @bt656: Data contain BT.656 embedded synchronization 42*ceafdaacSMauro Carvalho Chehab */ 43*ceafdaacSMauro Carvalho Chehab struct isp_parallel_cfg { 44*ceafdaacSMauro Carvalho Chehab unsigned int data_lane_shift:3; 45*ceafdaacSMauro Carvalho Chehab unsigned int clk_pol:1; 46*ceafdaacSMauro Carvalho Chehab unsigned int hs_pol:1; 47*ceafdaacSMauro Carvalho Chehab unsigned int vs_pol:1; 48*ceafdaacSMauro Carvalho Chehab unsigned int fld_pol:1; 49*ceafdaacSMauro Carvalho Chehab unsigned int data_pol:1; 50*ceafdaacSMauro Carvalho Chehab unsigned int bt656:1; 51*ceafdaacSMauro Carvalho Chehab }; 52*ceafdaacSMauro Carvalho Chehab 53*ceafdaacSMauro Carvalho Chehab enum { 54*ceafdaacSMauro Carvalho Chehab ISP_CCP2_PHY_DATA_CLOCK = 0, 55*ceafdaacSMauro Carvalho Chehab ISP_CCP2_PHY_DATA_STROBE = 1, 56*ceafdaacSMauro Carvalho Chehab }; 57*ceafdaacSMauro Carvalho Chehab 58*ceafdaacSMauro Carvalho Chehab enum { 59*ceafdaacSMauro Carvalho Chehab ISP_CCP2_MODE_MIPI = 0, 60*ceafdaacSMauro Carvalho Chehab ISP_CCP2_MODE_CCP2 = 1, 61*ceafdaacSMauro Carvalho Chehab }; 62*ceafdaacSMauro Carvalho Chehab 63*ceafdaacSMauro Carvalho Chehab /** 64*ceafdaacSMauro Carvalho Chehab * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity 65*ceafdaacSMauro Carvalho Chehab * @pos: position of the lane 66*ceafdaacSMauro Carvalho Chehab * @pol: polarity of the lane 67*ceafdaacSMauro Carvalho Chehab */ 68*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lane { 69*ceafdaacSMauro Carvalho Chehab u8 pos; 70*ceafdaacSMauro Carvalho Chehab u8 pol; 71*ceafdaacSMauro Carvalho Chehab }; 72*ceafdaacSMauro Carvalho Chehab 73*ceafdaacSMauro Carvalho Chehab #define ISP_CSIPHY1_NUM_DATA_LANES 1 74*ceafdaacSMauro Carvalho Chehab #define ISP_CSIPHY2_NUM_DATA_LANES 2 75*ceafdaacSMauro Carvalho Chehab 76*ceafdaacSMauro Carvalho Chehab /** 77*ceafdaacSMauro Carvalho Chehab * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration 78*ceafdaacSMauro Carvalho Chehab * @data: Configuration of one or two data lanes 79*ceafdaacSMauro Carvalho Chehab * @clk: Clock lane configuration 80*ceafdaacSMauro Carvalho Chehab */ 81*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lanes_cfg { 82*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; 83*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lane clk; 84*ceafdaacSMauro Carvalho Chehab }; 85*ceafdaacSMauro Carvalho Chehab 86*ceafdaacSMauro Carvalho Chehab /** 87*ceafdaacSMauro Carvalho Chehab * struct isp_ccp2_cfg - CCP2 interface configuration 88*ceafdaacSMauro Carvalho Chehab * @strobe_clk_pol: Strobe/clock polarity 89*ceafdaacSMauro Carvalho Chehab * 0 - Non Inverted, 1 - Inverted 90*ceafdaacSMauro Carvalho Chehab * @crc: Enable the cyclic redundancy check 91*ceafdaacSMauro Carvalho Chehab * @ccp2_mode: Enable CCP2 compatibility mode 92*ceafdaacSMauro Carvalho Chehab * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode 93*ceafdaacSMauro Carvalho Chehab * ISP_CCP2_MODE_CCP2 - CCP2 mode 94*ceafdaacSMauro Carvalho Chehab * @phy_layer: Physical layer selection 95*ceafdaacSMauro Carvalho Chehab * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer 96*ceafdaacSMauro Carvalho Chehab * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer 97*ceafdaacSMauro Carvalho Chehab * @vpclk_div: Video port output clock control 98*ceafdaacSMauro Carvalho Chehab * @vp_clk_pol: Video port output clock polarity 99*ceafdaacSMauro Carvalho Chehab * @lanecfg: CCP2/CSI2 lane configuration 100*ceafdaacSMauro Carvalho Chehab */ 101*ceafdaacSMauro Carvalho Chehab struct isp_ccp2_cfg { 102*ceafdaacSMauro Carvalho Chehab unsigned int strobe_clk_pol:1; 103*ceafdaacSMauro Carvalho Chehab unsigned int crc:1; 104*ceafdaacSMauro Carvalho Chehab unsigned int ccp2_mode:1; 105*ceafdaacSMauro Carvalho Chehab unsigned int phy_layer:1; 106*ceafdaacSMauro Carvalho Chehab unsigned int vpclk_div:2; 107*ceafdaacSMauro Carvalho Chehab unsigned int vp_clk_pol:1; 108*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lanes_cfg lanecfg; 109*ceafdaacSMauro Carvalho Chehab }; 110*ceafdaacSMauro Carvalho Chehab 111*ceafdaacSMauro Carvalho Chehab /** 112*ceafdaacSMauro Carvalho Chehab * struct isp_csi2_cfg - CSI2 interface configuration 113*ceafdaacSMauro Carvalho Chehab * @crc: Enable the cyclic redundancy check 114*ceafdaacSMauro Carvalho Chehab * @lanecfg: CSI-2 lane configuration 115*ceafdaacSMauro Carvalho Chehab * @num_data_lanes: The number of data lanes in use 116*ceafdaacSMauro Carvalho Chehab */ 117*ceafdaacSMauro Carvalho Chehab struct isp_csi2_cfg { 118*ceafdaacSMauro Carvalho Chehab unsigned crc:1; 119*ceafdaacSMauro Carvalho Chehab struct isp_csiphy_lanes_cfg lanecfg; 120*ceafdaacSMauro Carvalho Chehab u8 num_data_lanes; 121*ceafdaacSMauro Carvalho Chehab }; 122*ceafdaacSMauro Carvalho Chehab 123*ceafdaacSMauro Carvalho Chehab struct isp_bus_cfg { 124*ceafdaacSMauro Carvalho Chehab enum isp_interface_type interface; 125*ceafdaacSMauro Carvalho Chehab union { 126*ceafdaacSMauro Carvalho Chehab struct isp_parallel_cfg parallel; 127*ceafdaacSMauro Carvalho Chehab struct isp_ccp2_cfg ccp2; 128*ceafdaacSMauro Carvalho Chehab struct isp_csi2_cfg csi2; 129*ceafdaacSMauro Carvalho Chehab } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ 130*ceafdaacSMauro Carvalho Chehab }; 131*ceafdaacSMauro Carvalho Chehab 132*ceafdaacSMauro Carvalho Chehab #endif /* __OMAP3ISP_H__ */ 133