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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
46 * format and data layout of the buffer, and should be the only way to describe
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
[all …]
/linux/lib/crypto/arm/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 // load the words on-demand.
62 // Execute a quarter-round of BLAKE2s by mixing two columns or two diagonals.
64 // columns/diagonals. s0-s1 are the word offsets to the message words the first
65 // column/diagonal needs, and likewise s2-s3 for the second column/diagonal.
97 // a += b + m[blake2s_sigma[r][2*i + 1]];
103 // d = ror32(d ^ a, 8);
108 add \c0, \c0, \d0, ror#8
109 add \c1, \c1, \d1, ror#8
116 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Diters.c1 // SPDX-License-Identifier: GPL-2.0
34 int *v, i = zero; /* obscure initial value of i */ in iter_err_unsafe_c_loop() local
39 while ((v = bpf_iter_num_next(&it))) { in iter_err_unsafe_c_loop()
62 "r4 = 1;" in iter_err_unsafe_asm_loop()
68 "r6 += 1;" in iter_err_unsafe_asm_loop()
96 int *v; in iter_while_loop() local
101 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop()
102 bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v); in iter_while_loop()
114 int *v; in iter_while_loop_auto_cleanup() local
119 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop_auto_cleanup()
[all …]
/linux/arch/x86/include/asm/
H A Dperf_event_p4.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * perf-MSRs are not shared and every thread has its
17 * own perf-MSRs set)
20 #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
21 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
25 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/linux/Documentation/hwmon/
H A Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
22 * gpio_input: int array (min = 1, max = 17)
23 List of GPIO pins (0-16) to program as inputs
25 * gpio_output: int array (min = 1, max = 17)
26 List of GPIO pins (0-16) to program as outputs
28 * gpio_inverted: int array (min = 1, max = 17)
29 List of GPIO pins (0-16) to program as inverted
31 * gpio_normal: int array (min = 1, max = 17)
[all …]
/linux/arch/arm64/include/asm/
H A Dio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
23 * Generic IO read/write. These perform native-endian accesses.
29 asm volatile("strb %w0, %1" : : "rZ" (val), "Qo" (*ptr)); in __raw_writeb()
36 asm volatile("strh %w0, %1" : : "rZ" (val), "Qo" (*ptr)); in __raw_writew()
43 asm volatile("str %w0, %1" : : "rZ" (val), "Qo" (*ptr)); in __raw_writel()
50 asm volatile("str %x0, %1" : : "rZ" (val), "Qo" (*ptr)); in __raw_writeq()
57 asm volatile(ALTERNATIVE("ldrb %w0, [%1]", in __raw_readb()
58 "ldarb %w0, [%1]", in __raw_readb()
69 asm volatile(ALTERNATIVE("ldrh %w0, [%1]", in __raw_readw()
[all …]
/linux/sound/ppc/
H A Dsnd_ps3_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
49 * n:0..1
66 can be cleared by writing a '1' to the corresponding bit. A new interrupt
72 31 24 23 16 15 8 7 0
73 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
75 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
77 #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))
79 #define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8)
86 #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)
95 31 24 23 16 15 8 7 0
[all …]
/linux/include/linux/usb/
H A Dpd_vdo.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
18 #define VDO_MAX_SIZE (VDO_MAX_OBJECTS + 1)
22 * ----------
24 * <15> :: VDM type ( 1b == structured, 0b == unstructured )
27 * <10:8> :: object position (1-7 valid ... used for enter/exit mode only)
28 * <7:6> :: command type (SVDM only?)
38 #define VDO_SVDM_TYPE (1 << 15)
40 #define VDO_OPOS(x) ((x) << 8)
47 #define CMDT_RSP_ACK 1
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326.c1 // SPDX-License-Identifier: GPL-2.0
2 /* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */
15 /* The egress WM value 0x01a01fff should be used only when the
17 * for disabling the T2/MAC flow-control. When the interface is
40 spin_lock_bh(&adapter->mac_lock); in vsc_read()
48 } while (((status & 1) == 0) && (i < 50)); in vsc_read()
59 ((addr&0x01fe)>>1), *val); */ in vsc_read()
60 spin_unlock_bh(&adapter->mac_lock); in vsc_read()
65 spin_lock_bh(&adapter->mac_lock); in vsc_write()
70 ((addr&0x01fe)>>1), data); */ in vsc_write()
[all …]
/linux/drivers/memory/
H A Drenesas-rpc-if-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car RPC Interface Registers Definitions
23 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
30 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
35 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) argument
37 #define RPCIF_DRCR_RBE BIT(8)
59 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) argument
60 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) argument
63 #define RPCIF_SMCR_SSLKP BIT(8)
65 #define RPCIF_SMCR_SPIWE BIT(1)
[all …]
/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
42 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
85 * bit 15:0 - read sequence number
93 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)
100 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)
105 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) argument
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dst,sta32x.txt3 The driver for this device only supports I2C.
7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
[all …]
/linux/drivers/clk/versatile/
H A Dclk-icst.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
34 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
73 * The Integrator/AP core clock can only access the low eight in vco_get()
74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
[all …]
/linux/drivers/clk/ti/
H A Dfapll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
17 #define FAPLL_MAIN_DIV_P_SHIFT 8
50 #define SYNTH_LDMDIV1 BIT(8)
55 #define SYNTH_PHASE_K 8
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass() local
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
84 return !(v & FAPLL_MAIN_BP); in ti_fapll_clock_is_bypass()
86 return !!(v & FAPLL_MAIN_BP); in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass() local
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot_devlink.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2020-2021 NXP
9 * Resource 1: Frame references tracked per source port
17 #define REF_xxxx_I (1 * OCELOT_RESOURCE_SZ)
33 * ----------------------
44 * V V v v
55 * V V v v
66 * V V v v
77 * V V v v
88 * V V v v
[all …]
/linux/include/dt-bindings/usb/
H A Dpd.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define PDO_TYPE_BATT 1
20 #define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */
21 #define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */
22 #define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */
23 #define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */
24 #define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */
25 #define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */
64 #define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
70 #define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */
[all …]
/linux/arch/arc/include/asm/
H A Dperf_event.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
6 * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
33 #define ARC_REG_PCT_CONFIG_USER (1 << 18) /* count in user mode */
34 #define ARC_REG_PCT_CONFIG_KERN (1 << 19) /* count in kernel mode */
36 #define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */
37 #define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */
41 unsigned int m:8, c:8, r:5, i:1, s:2, v:8; member
43 unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
49 unsigned int c:16, r:8, v:8; member
[all …]
/linux/Documentation/iio/
H A Dad7380.rst1 .. SPDX-License-Identifier: GPL-2.0-only
23 * `AD7380-4 <https://www.analog.com/en/products/ad7380-4.html>`_
24 * `AD7381-4 <https://www.analog.com/en/products/ad7381-4.html>`_
25 * `AD7383-4 <https://www.analog.com/en/products/ad7383-4.html>`_
26 * `AD7384-4 <https://www.analog.com/en/products/ad7384-4.html>`_
27 * `AD7386-4 <https://www.analog.com/en/products/ad7386-4.html>`_
28 * `AD7387-4 <https://www.analog.com/en/products/ad7387-4.html>`_
29 * `AD7388-4 <https://www.analog.com/en/products/ad7388-4.html>`_
30 * `AD7389-4 <https://www.analog.com/en/products/ad7389-4.html>`_
31 * `ADAQ4370-4 <https://www.analog.com/en/products/adaq4370-4.html>`_
[all …]
/linux/arch/arm/crypto/
H A Dblake2b-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 // M_0-M_3 are occasionally used for other purposes too.
48 // Tables for computing ror64(x, 24) and ror64(x, 16) using the vtbl.8
50 // rotation amounts with NEON. (On Cortex-A53 it's the same speed as
51 // vshr.u64 + vsli.u64, while on Cortex-A7 it's faster.)
53 .byte 3, 4, 5, 6, 7, 0, 1, 2
55 .byte 2, 3, 4, 5, 6, 7, 0, 1
63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack
65 // pointer points to a 32-byte aligned buffer containing a copy of q8 and q9
[all …]
/linux/arch/powerpc/kernel/
H A Dalign.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* align.c - handle alignment exceptions for the Power PC.
5 * Copyright (c) 1998-1999 TiVo, Inc.
9 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
10 * 64-bit and Power4 support
39 #define ST 1 /* store */
40 #define SE 2 /* sign-extend value, or FP ld/st as word */
48 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
49 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
50 { 8, LD }, /* 0 00 10: evldh[x] */
[all …]
/linux/sound/oss/dmasound/
H A Ddmasound_atari.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - added versioning
12 * - put in and populated the hardware_afmts field.
13 * [0.2] - put in SNDCTL_DSP_GETCAPS value.
14 * 01/02/2001 [0.3] - put in default hard/soft settings.
52 * to convert samples into the right frequency/encoding. They will only work on
61 * parameterized loop would only produce slower code. Feel free to optimize
66 * only in stereo is hardcoded in both of them!
166 count &= ~1; in ata_ct_law()
171 return -EFAULT; in ata_ct_law()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
24 three channels (RGB data only) or on the Y channel only (YCbCr only). It can
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
[all …]
/linux/sound/sparc/
H A Ddbri.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
25 * - http
215 CS4215_LO(v) global() argument
220 CS4215_RO(v) global() argument
225 CS4215_LG(v) global() argument
232 CS4215_RG(v) global() argument
233 CS4215_MA(v) global() argument
380 D_PIPE(v) global() argument
396 D_SDP_MODE(v) global() argument
411 D_DTS_PRVIN(v) global() argument
412 D_DTS_PRVOUT(v) global() argument
415 D_TS_LEN(v) global() argument
416 D_TS_CYCLE(v) global() argument
422 D_TS_MON(v) global() argument
423 D_TS_NEXT(v) global() argument
426 D_CHI_CHICM(v) global() argument
432 D_CHI_BPF(v) global() argument
445 D_NT_RLB(v) global() argument
446 D_NT_LLB(v) global() argument
451 D_CDEC_CK(v) global() argument
452 D_CDEC_FED(v) global() argument
453 D_CDEC_RED(v) global() argument
456 D_TEST_RAM(v) global() argument
457 D_TEST_SIZE(v) global() argument
497 D_INTR_GETCHAN(v) global() argument
498 D_INTR_GETCODE(v) global() argument
499 D_INTR_GETCMD(v) global() argument
500 D_INTR_GETVAL(v) global() argument
501 D_INTR_GETRVAL(v) global() argument
539 DBRI_TD_CNT(v) global() argument
543 DBRI_TD_FCNT(v) global() argument
547 DBRI_TD_STATUS(v) global() argument
556 DBRI_RD_BCNT(v) global() argument
561 DBRI_RD_STATUS(v) global() argument
562 DBRI_RD_CNT(v) global() argument
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