Lines Matching +full:only +full:- +full:1 +full:- +full:8 +full:v
1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
25 * - https://www.freesoft.org/Linux/DBRI/
26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
31 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
34 * A timeslot defines the bit-offset and no. of bits read from a serial device.
36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
37 * (the second one is a monitor/tee pipe, valid only for serial input).
40 * parameters (volume, output selection) time multiplexed in 8 byte
44 * the same CHI bus, so I thought perhaps it is possible to use the on-board
45 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
47 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
53 * dbri_* DBRI high-level stuff
54 * other DBRI low-level stuff
61 #include <linux/dma-mapping.h>
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
95 #define D_INT (1<<0)
96 #define D_GEN (1<<1)
97 #define D_CMD (1<<2)
98 #define D_MM (1<<3)
99 #define D_USR (1<<4)
100 #define D_DESC (1<<5)
128 __u8 data[4]; /* Data mode: Time slots 5-8 */
129 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
131 __u8 offset; /* Bit offset from frame sync to time slot 1 */
134 __u8 precision; /* In bits, either 8 or 16 */
135 __u8 channels; /* 1 or 2 */
142 /* Time Slot 1, Status register */
143 #define CS4215_CLB (1<<2) /* Control Latch Bit */
144 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
145 /* 0: line: 2.8V, speaker 8V */
146 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
147 #define CS4215_RSRVD_1 (1<<5)
151 #define CS4215_DFR_ULAW 1
154 #define CS4215_DFR_STEREO (1<<2)
160 { 8000, (1 << 4), (0 << 3) },
161 { 16000, (1 << 4), (1 << 3) },
162 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
163 { 32000, (1 << 4), (3 << 3) },
164 /* { NA, (1 << 4), (4 << 3) }, */
165 /* { NA, (1 << 4), (5 << 3) }, */
166 { 48000, (1 << 4), (6 << 3) },
167 { 9600, (1 << 4), (7 << 3) },
169 { 11025, (2 << 4), (1 << 3) },
179 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
181 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
184 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
185 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
187 #define CS4215_BSEL_128 (1<<2)
190 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
196 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
197 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
200 /* Read only here and the same as the in data mode */
205 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
207 /* Time Slot 8, Reserved */
212 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
215 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_LE (1<<6) /* Line Out Enable */
217 #define CS4215_HE (1<<7) /* Headphone Enable */
220 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
221 #define CS4215_SE (1<<6) /* Speaker Enable */
222 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
225 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
226 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
227 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
228 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
229 #define CS4215_PIO1 (1<<7)
231 /* Time Slot 8, Input Setting */
232 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
233 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
251 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
254 #define DBRI_PLAY 1
277 (&(((struct dbri_dma *)0)->member[elem])))
314 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
328 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
329 #define D_P (1<<15) /* Program command & queue pointer valid */
330 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
331 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
332 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
333 #define D_X (1<<7) /* Sanity Timer Disable */
334 #define D_T (1<<6) /* Permit activation of the TE interface */
335 #define D_N (1<<5) /* Permit activation of the NT interface */
336 #define D_C (1<<4) /* Permit activation of the CHI interface */
337 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
338 #define D_D (1<<2) /* Disable Master Mode */
339 #define D_H (1<<1) /* Halt for Analysis */
340 #define D_R (1<<0) /* Soft Reset */
342 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
343 #define D_LITTLE_END (1<<8) /* Byte Order */
344 #define D_BIG_END (0<<8) /* Byte Order */
345 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
346 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
347 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
348 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */
349 #define D_IR (1<<0) /* Interrupt Indicator (read only) */
351 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
352 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
353 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
354 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
355 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
357 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
358 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
359 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
360 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
380 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
384 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
387 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
388 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
395 #define D_SDP_FIXED (6<<13) /* Short only */
396 #define D_SDP_MODE(v) ((v)&(7<<13))
398 #define D_SDP_TO_SER (1<<12) /* Direction */
400 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
402 #define D_SDP_P (1<<10) /* Pointer Valid */
403 #define D_SDP_A (1<<8) /* Abort */
404 #define D_SDP_C (1<<7) /* Clear */
407 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
408 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
409 #define D_DTS_INS (1<<15) /* Insert Time Slot */
411 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
412 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
415 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
416 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
417 #define D_TS_DI (1<<13) /* Data Invert */
422 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
423 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
426 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
427 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
428 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
429 #define D_CHI_OD (1<<13) /* Open Drain Enable */
430 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
431 #define D_CHI_FD (1<<11) /* Frame Drive */
432 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
435 #define D_NT_FBIT (1<<17) /* Frame Bit */
436 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
437 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
438 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
439 #define D_NT_ISNT (1<<13) /* Configure interface as NT */
440 #define D_NT_FT (1<<12) /* Fixed Timing */
441 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
442 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
443 #define D_NT_ACT (1<<9) /* Activate Interface */
444 #define D_NT_MFE (1<<8) /* Multiframe Enable */
445 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
446 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
447 #define D_NT_FACT (1<<1) /* Force Activation */
448 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
451 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
452 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
453 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
456 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
457 #define D_TEST_SIZE(v) ((v)<<11) /* */
460 #define D_TEST_SER 0x7 /* Serial-Controller test */
463 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
464 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
468 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
469 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
470 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
471 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
472 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
473 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */
476 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
482 #define D_INTR_XCMP 8 /* Transmission of frame complete */
485 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
486 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
497 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
498 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
499 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
500 #define D_INTR_GETVAL(v) ((v) & 0xffff)
501 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
504 #define D_P_1 1 /* TE transmit anchor */
511 #define D_P_8 8 /* */
537 #define DBRI_TD_F (1 << 31) /* End of Frame */
538 #define DBRI_TD_D (1 << 30) /* Do not append CRC */
539 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
540 #define DBRI_TD_B (1 << 15) /* Final interrupt */
541 #define DBRI_TD_M (1 << 14) /* Marker interrupt */
542 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
543 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
544 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
545 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
546 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
547 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
548 /* Maximum buffer size per TD: almost 8KB */
549 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
552 #define DBRI_RD_F (1 << 31) /* End of Frame */
553 #define DBRI_RD_C (1 << 30) /* Completed buffer */
554 #define DBRI_RD_B (1 << 15) /* Final interrupt */
555 #define DBRI_RD_M (1 << 14) /* Marker interrupt */
556 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
557 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
558 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
559 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
560 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
561 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
562 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
567 (substream->stream == \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
585 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
587 case 8:
594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
595 case 1:
611 then writing the address of the first list item to DBRI register 8.
629 dbri->dma->cmd buffer. After this, the commands can be written to
645 spin_lock_irqsave(&dbri->lock, flags);
646 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
647 spin_unlock_irqrestore(&dbri->lock, flags);
648 msleep_interruptible(1);
649 spin_lock_irqsave(&dbri->lock, flags);
651 spin_unlock_irqrestore(&dbri->lock, flags);
657 MAXLOOPS - maxloops - 1);
665 u32 dvma_addr = (u32)dbri->dma_dvma;
667 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
669 spin_lock(&dbri->cmdlock);
670 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
671 return dbri->cmdptr + 2;
672 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
673 return dbri->dma->cmd;
690 u32 dvma_addr = (u32)dbri->dma_dvma;
696 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
697 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
700 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
701 *(dbri->cmdptr+1) = addr;
702 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
705 if (cmd > dbri->cmdptr) {
708 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
712 s32 *ptr = dbri->cmdptr;
717 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
724 tmp = sbus_readl(dbri->regs + REG0);
726 sbus_writel(tmp, dbri->regs + REG0);
728 dbri->cmdptr = cmd;
729 spin_unlock(&dbri->cmdlock);
738 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
739 sbus_readl(dbri->regs + REG0),
740 sbus_readl(dbri->regs + REG2),
741 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
743 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
744 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
747 /* A brute approach - DBRI falls back to working burst size by itself
749 tmp = sbus_readl(dbri->regs + REG0);
752 sbus_writel(tmp, dbri->regs + REG0);
758 u32 dvma_addr = (u32)dbri->dma_dvma;
763 scoped_guard(spinlock_irqsave, &dbri->lock) {
768 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
770 spin_lock_init(&dbri->cmdlock);
775 dbri->dma->intr[0] = dma_addr;
776 dbri->dbri_irqp = 1;
780 scoped_guard(spinlock, &dbri->cmdlock) {
781 cmd = dbri->cmdptr = dbri->dma->cmd;
785 dbri->cmdptr = cmd;
786 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
787 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
789 sbus_writel(dma_addr, dbri->regs + REG8);
812 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
817 * Called on an in-use pipe to clear anything being transmitted or received
832 sdp = dbri->pipes[pipe].sdp;
845 desc = dbri->pipes[pipe].first_desc;
848 dbri->dma->desc[desc].ba = 0;
849 dbri->dma->desc[desc].nda = 0;
850 desc = dbri->next_desc[desc];
851 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
853 dbri->pipes[pipe].desc = -1;
854 dbri->pipes[pipe].first_desc = -1;
881 dbri->pipes[pipe].sdp = sdp;
882 dbri->pipes[pipe].desc = -1;
883 dbri->pipes[pipe].first_desc = -1;
906 if (dbri->pipes[pipe].sdp == 0
907 || dbri->pipes[prevpipe].sdp == 0
908 || dbri->pipes[nextpipe].sdp == 0) {
914 dbri->pipes[prevpipe].nextpipe = pipe;
915 dbri->pipes[pipe].nextpipe = nextpipe;
916 dbri->pipes[pipe].length = length;
920 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
922 * "If transmission on edges 0 or 1 is desired, then cycle n
924 * - DBRI data sheet, page 11
927 cycle = dbri->chi_bpf;
986 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
988 * The DBRI only interrupts us when the data changes (receive pipes),
989 * or only changes the data when this function is called (transmit pipes).
990 * Only short pipes (numbers 16-31) can be used in fixed data mode.
992 * These function operate on a 32-bit field, no matter how large
994 * ordering and alignment. An 8-bit time slot will always end up
995 * in the low-order 8 bits, filled either MSB-first or LSB-first,
1009 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1015 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1016 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1020 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1028 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1029 data = reverse_bytes(data, dbri->pipes[pipe].length);
1037 scoped_guard(spinlock_irqsave, &dbri->lock) {
1053 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1055 "non-fixed pipe %d\n", pipe);
1059 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1065 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1070 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1073 * Only pipe numbers 0-15 can be used in this mode.
1086 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1087 u32 dvma_addr = (u32)dbri->dma_dvma;
1091 int first_desc = -1;
1092 int last_desc = -1;
1094 if (info->pipe < 0 || info->pipe > 15) {
1096 return -2;
1099 if (dbri->pipes[info->pipe].sdp == 0) {
1101 info->pipe);
1102 return -2;
1105 dvma_buffer = info->dvma_buffer;
1106 len = info->size;
1109 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1111 "Called on receive pipe %d\n", info->pipe);
1112 return -2;
1115 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1118 info->pipe);
1119 return -2;
1124 if (pipe_active(dbri, info->pipe)) {
1126 "Called on active pipe %d\n", info->pipe);
1127 return -2;
1135 desc = dbri->pipes[info->pipe].first_desc;
1138 dbri->dma->desc[desc].ba = 0;
1139 dbri->dma->desc[desc].nda = 0;
1140 desc = dbri->next_desc[desc];
1141 } while (desc != -1 &&
1142 desc != dbri->pipes[info->pipe].first_desc);
1144 dbri->pipes[info->pipe].desc = -1;
1145 dbri->pipes[info->pipe].first_desc = -1;
1152 if (!dbri->dma->desc[desc].ba)
1158 return -1;
1162 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1169 dbri->next_desc[desc] = -1;
1170 dbri->dma->desc[desc].ba = dvma_buffer;
1171 dbri->dma->desc[desc].nda = 0;
1174 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1175 dbri->dma->desc[desc].word4 = 0;
1176 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1178 dbri->dma->desc[desc].word1 = 0;
1179 dbri->dma->desc[desc].word4 =
1183 if (first_desc == -1)
1186 dbri->next_desc[last_desc] = desc;
1187 dbri->dma->desc[last_desc].nda =
1193 len -= mylen;
1196 if (first_desc == -1 || last_desc == -1) {
1199 return -1;
1202 dbri->dma->desc[last_desc].nda =
1204 dbri->next_desc[last_desc] = first_desc;
1205 dbri->pipes[info->pipe].first_desc = first_desc;
1206 dbri->pipes[info->pipe].desc = first_desc;
1209 for (desc = first_desc; desc != -1;) {
1212 dbri->dma->desc[desc].word1,
1213 dbri->dma->desc[desc].ba,
1214 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1215 desc = dbri->next_desc[desc];
1225 ************************** DBRI - CHI interface ****************************
1228 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1257 dbri->pipes[16].sdp = 1;
1258 dbri->pipes[16].nextpipe = 16;
1263 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1265 * CHICM = 0 (slave mode, 8 kHz frame rate)
1271 /* Setup DBRI for CHI Master - generate clock, FS
1273 * BPF = bits per 8 kHz frame
1275 * FD = 1 - drive CHIFS on rising edge of CHICK
1277 int clockrate = bits_per_frame * 8;
1288 dbri->chi_bpf = bits_per_frame;
1292 * RCE = 0 - receive on falling edge of CHICK
1293 * XCE = 1 - transmit on rising edge of CHICK
1294 * XEN = 1 - enable transmitter
1295 * REN = 1 - enable receiver
1318 scoped_guard(spinlock_irqsave, &dbri->lock) {
1321 * Pipe 4: Send timeslots 1-4 (audio data)
1322 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1323 * Pipe 6: Receive timeslots 1-4 (audio data)
1324 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1325 * interrupt, and the rest of the data (slot 5 and 8) is
1326 * not relevant for us (only for doublechecking).
1329 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1330 * Pipe 18: Receive timeslot 1 (clb).
1350 * No action, memory resetting only.
1352 * Data Time Slot 5-8
1356 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1357 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1358 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1359 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1362 * Control Time Slot 1-4
1364 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1365 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1368 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1369 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1370 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1371 mm->ctrl[3] = 0;
1373 mm->status = 0;
1374 mm->version = 0xff;
1375 mm->precision = 8; /* For ULAW */
1376 mm->channels = 1;
1384 dbri->mm.data[0] |= 63;
1385 dbri->mm.data[1] |= 63;
1386 dbri->mm.data[2] &= ~15;
1387 dbri->mm.data[3] &= ~15;
1390 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1391 int left_gain = info->left_gain & 0x3f;
1392 int right_gain = info->right_gain & 0x3f;
1394 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1395 dbri->mm.data[1] &= ~0x3f;
1396 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1397 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1400 info = &dbri->stream_info[DBRI_REC];
1401 left_gain = info->left_gain & 0xf;
1402 right_gain = info->right_gain & 0xf;
1403 dbri->mm.data[2] |= CS4215_LG(left_gain);
1404 dbri->mm.data[3] |= CS4215_RG(right_gain);
1407 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1419 dbri->mm.channels, dbri->mm.precision);
1421 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1425 cs4215_setdata(dbri, 1);
1430 * Pipe 4: Send timeslots 1-4 (audio data)
1431 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1432 * Pipe 6: Receive timeslots 1-4 (audio data)
1433 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1434 * interrupt, and the rest of the data (slot 5 and 8) is
1435 * not relevant for us (only for doublechecking).
1441 scoped_guard(spinlock_irqsave, &dbri->lock) {
1442 tmp = sbus_readl(dbri->regs + REG0);
1444 sbus_writel(tmp, dbri->regs + REG0);
1446 /* Switch CS4215 to data mode - set PIO3 to 1 */
1448 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1452 /* Note: this next doesn't work for 8-bit stereo, because the two
1453 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1456 * DBRI non-contiguous mode would be required to make this work.
1458 data_width = dbri->mm.channels * dbri->mm.precision;
1460 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1461 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1462 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1463 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1466 tmp = sbus_readl(dbri->regs + REG0);
1468 sbus_writel(tmp, dbri->regs + REG0);
1482 /* FIXME - let the CPU do something useful during these delays */
1484 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1487 cs4215_setdata(dbri, 1);
1494 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1495 sbus_writel(val, dbri->regs + REG2);
1514 * done in hardware by a TI 248 that delays the DBRI->4215
1517 scoped_guard(spinlock_irqsave, &dbri->lock) {
1518 tmp = sbus_readl(dbri->regs + REG0);
1520 sbus_writel(tmp, dbri->regs + REG0);
1526 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1527 * Pipe 18: Receive timeslot 1 (clb).
1531 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1532 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1533 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1537 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1538 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1540 scoped_guard(spinlock_irqsave, &dbri->lock) {
1541 tmp = sbus_readl(dbri->regs + REG0);
1543 sbus_writel(tmp, dbri->regs + REG0);
1546 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1547 msleep_interruptible(1);
1551 dbri->mm.status);
1552 return -1;
1560 /* Terminate CS4215 control mode - data sheet says
1561 * "Set CLB=1 and send two more frames of valid control info"
1563 dbri->mm.ctrl[0] |= CS4215_CLB;
1564 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1566 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1593 return -1;
1598 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1599 dbri->mm.precision = 8;
1602 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1603 dbri->mm.precision = 8;
1606 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1607 dbri->mm.precision = 8;
1610 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1611 dbri->mm.precision = 16;
1615 return -1;
1619 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1620 dbri->mm.ctrl[2] = CS4215_XCLK |
1623 dbri->mm.channels = channels;
1625 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1639 u32 reg2 = sbus_readl(dbri->regs + REG2);
1645 dbri->mm.onboard = 1;
1649 dbri->mm.onboard = 0;
1654 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1660 return -EIO;
1664 cs4215_init_data(&dbri->mm);
1667 recv_fixed(dbri, 18, &dbri->mm.status);
1668 recv_fixed(dbri, 19, &dbri->mm.version);
1670 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1671 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1673 dbri->mm.offset);
1674 return -EIO;
1676 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1711 dvma_addr = (u32)dbri->dma_dvma;
1712 info = &dbri->stream_info[DBRI_REC];
1713 guard(spinlock_irqsave)(&dbri->lock);
1715 if (info->pipe >= 0) {
1716 first_td = dbri->pipes[info->pipe].first_desc;
1724 dbri->pipes[info->pipe].sdp
1731 dbri->pipes[info->pipe].desc = first_td;
1735 info = &dbri->stream_info[DBRI_PLAY];
1737 if (info->pipe >= 0) {
1738 first_td = dbri->pipes[info->pipe].first_desc;
1746 dbri->pipes[info->pipe].sdp
1753 dbri->pipes[info->pipe].desc = first_td;
1774 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1775 int td = dbri->pipes[pipe].desc;
1784 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1790 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1791 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1793 td = dbri->next_desc[td];
1794 dbri->pipes[pipe].desc = td;
1798 spin_unlock(&dbri->lock);
1799 snd_pcm_period_elapsed(info->substream);
1800 spin_lock(&dbri->lock);
1806 int rd = dbri->pipes[pipe].desc;
1814 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1815 status = dbri->dma->desc[rd].word1;
1816 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1818 info = &dbri->stream_info[DBRI_REC];
1819 info->offset += DBRI_RD_CNT(status);
1827 spin_unlock(&dbri->lock);
1828 snd_pcm_period_elapsed(info->substream);
1829 spin_lock(&dbri->lock);
1843 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1863 /* UNDR - Transmission underrun
1872 int td = dbri->pipes[pipe].desc;
1874 dbri->dma->desc[td].word4 = 0;
1877 dbri->pipes[pipe].sdp
1879 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1885 /* FXDT - Fixed data change */
1886 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1887 val = reverse_bytes(val, dbri->pipes[channel].length);
1889 if (dbri->pipes[channel].recv_fixed_ptr)
1890 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1901 * right now). Non-zero words require processing and are handed off
1908 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1909 dbri->dma->intr[dbri->dbri_irqp] = 0;
1910 dbri->dbri_irqp++;
1911 if (dbri->dbri_irqp == DBRI_INT_BLK)
1912 dbri->dbri_irqp = 1;
1926 guard(spinlock)(&dbri->lock);
1931 x = sbus_readl(dbri->regs + REG1);
1952 * to be disabled, so just re-enable and try to keep going.
1954 * The only one I've seen is MRR, which will be triggered
1963 tmp = sbus_readl(dbri->regs + REG0);
1965 sbus_writel(tmp, dbri->regs + REG0);
1990 .channels_min = 1,
1993 .period_bytes_min = 1,
1995 .periods_min = 1,
2008 if (c->min > 1) {
2024 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2025 ch.min = 1;
2026 ch.max = 1;
2027 ch.integer = 1;
2036 struct snd_pcm_runtime *runtime = substream->runtime;
2040 runtime->hw = snd_dbri_pcm_hw;
2042 scoped_guard(spinlock_irqsave, &dbri->lock) {
2043 info->substream = substream;
2044 info->offset = 0;
2045 info->dvma_buffer = 0;
2046 info->pipe = -1;
2051 -1);
2055 -1);
2068 info->substream = NULL;
2069 info->offset = 0;
2077 struct snd_pcm_runtime *runtime = substream->runtime;
2090 /* hw_params can get called multiple times. Only map the DMA once.
2092 if (info->dvma_buffer == 0) {
2098 info->dvma_buffer =
2099 dma_map_single(&dbri->op->dev,
2100 runtime->dma_area,
2107 direction, info->dvma_buffer);
2119 /* hw_free can get called multiple times. Only unmap the DMA once.
2121 if (info->dvma_buffer) {
2127 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2128 substream->runtime->buffer_size, direction);
2129 info->dvma_buffer = 0;
2131 if (info->pipe != -1) {
2132 reset_pipe(dbri, info->pipe);
2133 info->pipe = -1;
2145 info->size = snd_pcm_lib_buffer_bytes(substream);
2147 info->pipe = 4; /* Send pipe */
2149 info->pipe = 6; /* Receive pipe */
2151 guard(spinlock_irq)(&dbri->lock);
2152 info->offset = 0;
2160 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2174 /* Re-submit the TDs. */
2179 reset_pipe(dbri, info->pipe);
2182 ret = -EINVAL;
2194 ret = bytes_to_frames(substream->runtime, info->offset)
2195 % substream->runtime->buffer_size;
2197 ret, substream->runtime->buffer_size);
2219 /* playback count */ 1,
2220 /* capture count */ 1, &pcm);
2227 pcm->private_data = card->private_data;
2228 pcm->info_flags = 0;
2229 strscpy(pcm->name, card->shortname);
2243 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2244 uinfo->count = 2;
2245 uinfo->value.integer.min = 0;
2246 if (kcontrol->private_value == DBRI_PLAY)
2247 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2249 uinfo->value.integer.max = DBRI_MAX_GAIN;
2260 return -EINVAL;
2261 info = &dbri->stream_info[kcontrol->private_value];
2263 ucontrol->value.integer.value[0] = info->left_gain;
2264 ucontrol->value.integer.value[1] = info->right_gain;
2273 &dbri->stream_info[kcontrol->private_value];
2277 vol[0] = ucontrol->value.integer.value[0];
2278 vol[1] = ucontrol->value.integer.value[1];
2279 if (kcontrol->private_value == DBRI_PLAY) {
2280 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2281 return -EINVAL;
2283 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2284 return -EINVAL;
2287 if (info->left_gain != vol[0]) {
2288 info->left_gain = vol[0];
2289 changed = 1;
2291 if (info->right_gain != vol[1]) {
2292 info->right_gain = vol[1];
2293 changed = 1;
2296 /* First mute outputs, and wait 1/8000 sec (125 us)
2299 cs4215_setdata(dbri, 1);
2309 int mask = (kcontrol->private_value >> 16) & 0xff;
2311 uinfo->type = (mask == 1) ?
2313 uinfo->count = 1;
2314 uinfo->value.integer.min = 0;
2315 uinfo->value.integer.max = mask;
2323 int elem = kcontrol->private_value & 0xff;
2324 int shift = (kcontrol->private_value >> 8) & 0xff;
2325 int mask = (kcontrol->private_value >> 16) & 0xff;
2326 int invert = (kcontrol->private_value >> 24) & 1;
2329 return -EINVAL;
2332 ucontrol->value.integer.value[0] =
2333 (dbri->mm.data[elem] >> shift) & mask;
2335 ucontrol->value.integer.value[0] =
2336 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2338 if (invert == 1)
2339 ucontrol->value.integer.value[0] =
2340 mask - ucontrol->value.integer.value[0];
2348 int elem = kcontrol->private_value & 0xff;
2349 int shift = (kcontrol->private_value >> 8) & 0xff;
2350 int mask = (kcontrol->private_value >> 16) & 0xff;
2351 int invert = (kcontrol->private_value >> 24) & 1;
2356 return -EINVAL;
2358 val = (ucontrol->value.integer.value[0] & mask);
2359 if (invert == 1)
2360 val = mask - val;
2364 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2366 changed = (val != dbri->mm.data[elem]);
2368 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2370 changed = (val != dbri->mm.ctrl[elem - 4]);
2374 "mixer-value=%ld, mm-value=0x%x\n",
2375 mask, changed, ucontrol->value.integer.value[0],
2376 dbri->mm.data[elem & 3]);
2379 /* First mute outputs, and wait 1/8000 sec (125 us)
2382 cs4215_setdata(dbri, 1);
2389 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2397 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2409 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2410 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2411 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2421 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2422 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2423 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2424 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2432 if (snd_BUG_ON(!card || !card->private_data))
2433 return -EINVAL;
2434 dbri = card->private_data;
2436 strscpy(card->mixername, card->shortname);
2446 dbri->stream_info[idx].left_gain = 0;
2447 dbri->stream_info[idx].right_gain = 0;
2459 struct snd_dbri *dbri = entry->private_data;
2461 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2462 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2463 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2464 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2471 struct snd_dbri *dbri = entry->private_data;
2477 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2482 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2484 pptr->sdp, pptr->desc,
2485 pptr->length, pptr->nextpipe);
2493 struct snd_dbri *dbri = card->private_data;
2512 struct snd_dbri *dbri = card->private_data;
2515 spin_lock_init(&dbri->lock);
2516 dbri->op = op;
2517 dbri->irq = irq;
2519 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2520 &dbri->dma_dvma, GFP_KERNEL);
2521 if (!dbri->dma)
2522 return -ENOMEM;
2525 dbri->dma, dbri->dma_dvma);
2528 dbri->regs_size = resource_size(&op->resource[0]);
2529 dbri->regs = of_ioremap(&op->resource[0], 0,
2530 dbri->regs_size, "DBRI Registers");
2531 if (!dbri->regs) {
2533 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2534 (void *)dbri->dma, dbri->dma_dvma);
2535 return -EIO;
2538 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2541 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2542 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2543 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2544 (void *)dbri->dma, dbri->dma_dvma);
2564 if (dbri->irq)
2565 free_irq(dbri->irq, dbri);
2567 if (dbri->regs)
2568 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2570 if (dbri->dma)
2571 dma_free_coherent(&dbri->op->dev,
2573 (void *)dbri->dma, dbri->dma_dvma);
2586 return -ENODEV;
2589 return -ENOENT;
2592 irq = op->archdata.irqs[0];
2594 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2595 return -ENODEV;
2598 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2603 strscpy(card->driver, "DBRI");
2604 strscpy(card->shortname, "Sun DBRI");
2605 rp = &op->resource[0];
2606 sprintf(card->longname, "%s at 0x%02lx:0x%016llx, irq %d",
2607 card->shortname,
2608 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2616 dbri = card->private_data;
2627 dev_set_drvdata(&op->dev, card);
2634 dev, dbri->regs,
2635 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2648 struct snd_card *card = dev_get_drvdata(&op->dev);
2650 snd_dbri_free(card->private_data);