xref: /linux/arch/x86/include/asm/perf_event_p4.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a072738eSCyrill Gorcunov /*
30d2eb44fSLucas De Marchi  * Netburst Performance Events (P4, old Xeon)
4a072738eSCyrill Gorcunov  */
5a072738eSCyrill Gorcunov 
6a072738eSCyrill Gorcunov #ifndef PERF_EVENT_P4_H
7a072738eSCyrill Gorcunov #define PERF_EVENT_P4_H
8a072738eSCyrill Gorcunov 
9a072738eSCyrill Gorcunov #include <linux/cpu.h>
10a072738eSCyrill Gorcunov #include <linux/bitops.h>
11a072738eSCyrill Gorcunov 
12a072738eSCyrill Gorcunov /*
130d2eb44fSLucas De Marchi  * NetBurst has performance MSRs shared between
14a072738eSCyrill Gorcunov  * threads if HT is turned on, ie for both logical
15a072738eSCyrill Gorcunov  * processors (mem: in turn in Atom with HT support
16a072738eSCyrill Gorcunov  * perf-MSRs are not shared and every thread has its
17a072738eSCyrill Gorcunov  * own perf-MSRs set)
18a072738eSCyrill Gorcunov  */
19a072738eSCyrill Gorcunov #define ARCH_P4_TOTAL_ESCR	(46)
20a072738eSCyrill Gorcunov #define ARCH_P4_RESERVED_ESCR	(2) /* IQ_ESCR(0,1) not always present */
21a072738eSCyrill Gorcunov #define ARCH_P4_MAX_ESCR	(ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
22a072738eSCyrill Gorcunov #define ARCH_P4_MAX_CCCR	(18)
23a072738eSCyrill Gorcunov 
24047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_BITS	(40)
25047a3772SCyrill Gorcunov #define ARCH_P4_CNTRVAL_MASK	((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
267d44ec19SCyrill Gorcunov #define ARCH_P4_UNFLAGGED_BIT	((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
27047a3772SCyrill Gorcunov 
285ac2b5c2SIngo Molnar #define P4_ESCR_EVENT_MASK	0x7e000000ULL
29d814f301SCyrill Gorcunov #define P4_ESCR_EVENT_SHIFT	25
305ac2b5c2SIngo Molnar #define P4_ESCR_EVENTMASK_MASK	0x01fffe00ULL
31d814f301SCyrill Gorcunov #define P4_ESCR_EVENTMASK_SHIFT	9
325ac2b5c2SIngo Molnar #define P4_ESCR_TAG_MASK	0x000001e0ULL
33d814f301SCyrill Gorcunov #define P4_ESCR_TAG_SHIFT	5
345ac2b5c2SIngo Molnar #define P4_ESCR_TAG_ENABLE	0x00000010ULL
355ac2b5c2SIngo Molnar #define P4_ESCR_T0_OS		0x00000008ULL
365ac2b5c2SIngo Molnar #define P4_ESCR_T0_USR		0x00000004ULL
375ac2b5c2SIngo Molnar #define P4_ESCR_T1_OS		0x00000002ULL
385ac2b5c2SIngo Molnar #define P4_ESCR_T1_USR		0x00000001ULL
39d814f301SCyrill Gorcunov 
40d814f301SCyrill Gorcunov #define P4_ESCR_EVENT(v)	((v) << P4_ESCR_EVENT_SHIFT)
41d814f301SCyrill Gorcunov #define P4_ESCR_EMASK(v)	((v) << P4_ESCR_EVENTMASK_SHIFT)
42d814f301SCyrill Gorcunov #define P4_ESCR_TAG(v)		((v) << P4_ESCR_TAG_SHIFT)
43a072738eSCyrill Gorcunov 
445ac2b5c2SIngo Molnar #define P4_CCCR_OVF			0x80000000ULL
455ac2b5c2SIngo Molnar #define P4_CCCR_CASCADE			0x40000000ULL
465ac2b5c2SIngo Molnar #define P4_CCCR_OVF_PMI_T0		0x04000000ULL
475ac2b5c2SIngo Molnar #define P4_CCCR_OVF_PMI_T1		0x08000000ULL
485ac2b5c2SIngo Molnar #define P4_CCCR_FORCE_OVF		0x02000000ULL
495ac2b5c2SIngo Molnar #define P4_CCCR_EDGE			0x01000000ULL
505ac2b5c2SIngo Molnar #define P4_CCCR_THRESHOLD_MASK		0x00f00000ULL
51a072738eSCyrill Gorcunov #define P4_CCCR_THRESHOLD_SHIFT		20
525ac2b5c2SIngo Molnar #define P4_CCCR_COMPLEMENT		0x00080000ULL
535ac2b5c2SIngo Molnar #define P4_CCCR_COMPARE			0x00040000ULL
545ac2b5c2SIngo Molnar #define P4_CCCR_ESCR_SELECT_MASK	0x0000e000ULL
55a072738eSCyrill Gorcunov #define P4_CCCR_ESCR_SELECT_SHIFT	13
565ac2b5c2SIngo Molnar #define P4_CCCR_ENABLE			0x00001000ULL
575ac2b5c2SIngo Molnar #define P4_CCCR_THREAD_SINGLE		0x00010000ULL
585ac2b5c2SIngo Molnar #define P4_CCCR_THREAD_BOTH		0x00020000ULL
595ac2b5c2SIngo Molnar #define P4_CCCR_THREAD_ANY		0x00030000ULL
605ac2b5c2SIngo Molnar #define P4_CCCR_RESERVED		0x00000fffULL
61a072738eSCyrill Gorcunov 
62d814f301SCyrill Gorcunov #define P4_CCCR_THRESHOLD(v)		((v) << P4_CCCR_THRESHOLD_SHIFT)
63d814f301SCyrill Gorcunov #define P4_CCCR_ESEL(v)			((v) << P4_CCCR_ESCR_SELECT_SHIFT)
64d814f301SCyrill Gorcunov 
65d814f301SCyrill Gorcunov #define P4_GEN_ESCR_EMASK(class, name, bit)	\
665ac2b5c2SIngo Molnar 	class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
67d814f301SCyrill Gorcunov #define P4_ESCR_EMASK_BIT(class, name)		class##__##name
68a072738eSCyrill Gorcunov 
69a072738eSCyrill Gorcunov /*
70a072738eSCyrill Gorcunov  * config field is 64bit width and consists of
71a072738eSCyrill Gorcunov  * HT << 63 | ESCR << 32 | CCCR
72a072738eSCyrill Gorcunov  * where HT is HyperThreading bit (since ESCR
73a072738eSCyrill Gorcunov  * has it reserved we may use it for own purpose)
74a072738eSCyrill Gorcunov  *
75a072738eSCyrill Gorcunov  * note that this is NOT the addresses of respective
76a072738eSCyrill Gorcunov  * ESCR and CCCR but rather an only packed value should
77a072738eSCyrill Gorcunov  * be unpacked and written to a proper addresses
78a072738eSCyrill Gorcunov  *
7939ef13a4SCyrill Gorcunov  * the base idea is to pack as much info as possible
80a072738eSCyrill Gorcunov  */
81a072738eSCyrill Gorcunov #define p4_config_pack_escr(v)		(((u64)(v)) << 32)
82a072738eSCyrill Gorcunov #define p4_config_pack_cccr(v)		(((u64)(v)) & 0xffffffffULL)
83a072738eSCyrill Gorcunov #define p4_config_unpack_escr(v)	(((u64)(v)) >> 32)
84d814f301SCyrill Gorcunov #define p4_config_unpack_cccr(v)	(((u64)(v)) & 0xffffffffULL)
85a072738eSCyrill Gorcunov 
86a072738eSCyrill Gorcunov #define p4_config_unpack_emask(v)			\
87a072738eSCyrill Gorcunov 	({						\
88a072738eSCyrill Gorcunov 		u32 t = p4_config_unpack_escr((v));	\
89d814f301SCyrill Gorcunov 		t = t &  P4_ESCR_EVENTMASK_MASK;	\
90d814f301SCyrill Gorcunov 		t = t >> P4_ESCR_EVENTMASK_SHIFT;	\
91a072738eSCyrill Gorcunov 		t;					\
92a072738eSCyrill Gorcunov 	})
93a072738eSCyrill Gorcunov 
94d814f301SCyrill Gorcunov #define p4_config_unpack_event(v)			\
95d814f301SCyrill Gorcunov 	({						\
96d814f301SCyrill Gorcunov 		u32 t = p4_config_unpack_escr((v));	\
97d814f301SCyrill Gorcunov 		t = t &  P4_ESCR_EVENT_MASK;		\
98d814f301SCyrill Gorcunov 		t = t >> P4_ESCR_EVENT_SHIFT;		\
99d814f301SCyrill Gorcunov 		t;					\
100d814f301SCyrill Gorcunov 	})
101d814f301SCyrill Gorcunov 
102a072738eSCyrill Gorcunov #define P4_CONFIG_HT_SHIFT		63
103a072738eSCyrill Gorcunov #define P4_CONFIG_HT			(1ULL << P4_CONFIG_HT_SHIFT)
104a072738eSCyrill Gorcunov 
105c9cf4a01SCyrill Gorcunov /*
106f9129870SCyrill Gorcunov  * If an event has alias it should be marked
107f9129870SCyrill Gorcunov  * with a special bit. (Don't forget to check
108f9129870SCyrill Gorcunov  * P4_PEBS_CONFIG_MASK and related bits on
109f9129870SCyrill Gorcunov  * modification.)
110f9129870SCyrill Gorcunov  */
1115ac2b5c2SIngo Molnar #define P4_CONFIG_ALIASABLE		(1ULL << 9)
112f9129870SCyrill Gorcunov 
113f9129870SCyrill Gorcunov /*
114c9cf4a01SCyrill Gorcunov  * The bits we allow to pass for RAW events
115c9cf4a01SCyrill Gorcunov  */
116c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_ESCR		\
117c9cf4a01SCyrill Gorcunov 	P4_ESCR_EVENT_MASK	|	\
118c9cf4a01SCyrill Gorcunov 	P4_ESCR_EVENTMASK_MASK	|	\
119c9cf4a01SCyrill Gorcunov 	P4_ESCR_TAG_MASK	|	\
120c9cf4a01SCyrill Gorcunov 	P4_ESCR_TAG_ENABLE
121c9cf4a01SCyrill Gorcunov 
122c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK_CCCR		\
123c9cf4a01SCyrill Gorcunov 	P4_CCCR_EDGE		|	\
124c9cf4a01SCyrill Gorcunov 	P4_CCCR_THRESHOLD_MASK	|	\
125c9cf4a01SCyrill Gorcunov 	P4_CCCR_COMPLEMENT	|	\
126c9cf4a01SCyrill Gorcunov 	P4_CCCR_COMPARE		|	\
127c9cf4a01SCyrill Gorcunov 	P4_CCCR_THREAD_ANY	|	\
128c9cf4a01SCyrill Gorcunov 	P4_CCCR_RESERVED
129c9cf4a01SCyrill Gorcunov 
130c9cf4a01SCyrill Gorcunov /* some dangerous bits are reserved for kernel internals */
131c9cf4a01SCyrill Gorcunov #define P4_CONFIG_MASK				  	  \
132c9cf4a01SCyrill Gorcunov 	(p4_config_pack_escr(P4_CONFIG_MASK_ESCR))	| \
133c9cf4a01SCyrill Gorcunov 	(p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
134c9cf4a01SCyrill Gorcunov 
135f9129870SCyrill Gorcunov /*
136f9129870SCyrill Gorcunov  * In case of event aliasing we need to preserve some
137f53173e4SCyrill Gorcunov  * caller bits, otherwise the mapping won't be complete.
138f9129870SCyrill Gorcunov  */
139f9129870SCyrill Gorcunov #define P4_CONFIG_EVENT_ALIAS_MASK			  \
140f9129870SCyrill Gorcunov 	(p4_config_pack_escr(P4_CONFIG_MASK_ESCR)	| \
141f9129870SCyrill Gorcunov 	 p4_config_pack_cccr(P4_CCCR_EDGE		| \
142f9129870SCyrill Gorcunov 			     P4_CCCR_THRESHOLD_MASK	| \
143f9129870SCyrill Gorcunov 			     P4_CCCR_COMPLEMENT		| \
144f9129870SCyrill Gorcunov 			     P4_CCCR_COMPARE))
145f9129870SCyrill Gorcunov 
146f9129870SCyrill Gorcunov #define  P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS		  \
147f9129870SCyrill Gorcunov 	((P4_CONFIG_HT)					| \
148f9129870SCyrill Gorcunov 	 p4_config_pack_escr(P4_ESCR_T0_OS		| \
149f9129870SCyrill Gorcunov 			     P4_ESCR_T0_USR		| \
150f9129870SCyrill Gorcunov 			     P4_ESCR_T1_OS		| \
151f9129870SCyrill Gorcunov 			     P4_ESCR_T1_USR)		| \
152f9129870SCyrill Gorcunov 	 p4_config_pack_cccr(P4_CCCR_OVF		| \
153f9129870SCyrill Gorcunov 			     P4_CCCR_CASCADE		| \
154f9129870SCyrill Gorcunov 			     P4_CCCR_FORCE_OVF		| \
155f9129870SCyrill Gorcunov 			     P4_CCCR_THREAD_ANY		| \
156f9129870SCyrill Gorcunov 			     P4_CCCR_OVF_PMI_T0		| \
157f9129870SCyrill Gorcunov 			     P4_CCCR_OVF_PMI_T1		| \
158f9129870SCyrill Gorcunov 			     P4_CONFIG_ALIASABLE))
159f9129870SCyrill Gorcunov 
p4_is_event_cascaded(u64 config)160a072738eSCyrill Gorcunov static inline bool p4_is_event_cascaded(u64 config)
161a072738eSCyrill Gorcunov {
162a072738eSCyrill Gorcunov 	u32 cccr = p4_config_unpack_cccr(config);
163a072738eSCyrill Gorcunov 	return !!(cccr & P4_CCCR_CASCADE);
164a072738eSCyrill Gorcunov }
165a072738eSCyrill Gorcunov 
p4_ht_config_thread(u64 config)166a072738eSCyrill Gorcunov static inline int p4_ht_config_thread(u64 config)
167a072738eSCyrill Gorcunov {
168a072738eSCyrill Gorcunov 	return !!(config & P4_CONFIG_HT);
169a072738eSCyrill Gorcunov }
170a072738eSCyrill Gorcunov 
p4_set_ht_bit(u64 config)171a072738eSCyrill Gorcunov static inline u64 p4_set_ht_bit(u64 config)
172a072738eSCyrill Gorcunov {
173a072738eSCyrill Gorcunov 	return config | P4_CONFIG_HT;
174a072738eSCyrill Gorcunov }
175a072738eSCyrill Gorcunov 
p4_clear_ht_bit(u64 config)176a072738eSCyrill Gorcunov static inline u64 p4_clear_ht_bit(u64 config)
177a072738eSCyrill Gorcunov {
178a072738eSCyrill Gorcunov 	return config & ~P4_CONFIG_HT;
179a072738eSCyrill Gorcunov }
180a072738eSCyrill Gorcunov 
p4_ht_active(void)181a072738eSCyrill Gorcunov static inline int p4_ht_active(void)
182a072738eSCyrill Gorcunov {
183a072738eSCyrill Gorcunov #ifdef CONFIG_SMP
184*8078f4d6SThomas Gleixner 	return __max_threads_per_core > 1;
185a072738eSCyrill Gorcunov #endif
186a072738eSCyrill Gorcunov 	return 0;
187a072738eSCyrill Gorcunov }
188a072738eSCyrill Gorcunov 
p4_ht_thread(int cpu)189a072738eSCyrill Gorcunov static inline int p4_ht_thread(int cpu)
190a072738eSCyrill Gorcunov {
191a072738eSCyrill Gorcunov #ifdef CONFIG_SMP
192*8078f4d6SThomas Gleixner 	if (__max_threads_per_core == 2)
1934ba29684SChristoph Lameter 		return cpu != cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map));
194a072738eSCyrill Gorcunov #endif
195a072738eSCyrill Gorcunov 	return 0;
196a072738eSCyrill Gorcunov }
197a072738eSCyrill Gorcunov 
p4_should_swap_ts(u64 config,int cpu)198a072738eSCyrill Gorcunov static inline int p4_should_swap_ts(u64 config, int cpu)
199a072738eSCyrill Gorcunov {
200a072738eSCyrill Gorcunov 	return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
201a072738eSCyrill Gorcunov }
202a072738eSCyrill Gorcunov 
p4_default_cccr_conf(int cpu)203a072738eSCyrill Gorcunov static inline u32 p4_default_cccr_conf(int cpu)
204a072738eSCyrill Gorcunov {
205a072738eSCyrill Gorcunov 	/*
206a072738eSCyrill Gorcunov 	 * Note that P4_CCCR_THREAD_ANY is "required" on
207a072738eSCyrill Gorcunov 	 * non-HT machines (on HT machines we count TS events
208a072738eSCyrill Gorcunov 	 * regardless the state of second logical processor
209a072738eSCyrill Gorcunov 	 */
210a072738eSCyrill Gorcunov 	u32 cccr = P4_CCCR_THREAD_ANY;
211a072738eSCyrill Gorcunov 
212a072738eSCyrill Gorcunov 	if (!p4_ht_thread(cpu))
213a072738eSCyrill Gorcunov 		cccr |= P4_CCCR_OVF_PMI_T0;
214a072738eSCyrill Gorcunov 	else
215a072738eSCyrill Gorcunov 		cccr |= P4_CCCR_OVF_PMI_T1;
216a072738eSCyrill Gorcunov 
217a072738eSCyrill Gorcunov 	return cccr;
218a072738eSCyrill Gorcunov }
219a072738eSCyrill Gorcunov 
p4_default_escr_conf(int cpu,int exclude_os,int exclude_usr)220a072738eSCyrill Gorcunov static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
221a072738eSCyrill Gorcunov {
222a072738eSCyrill Gorcunov 	u32 escr = 0;
223a072738eSCyrill Gorcunov 
224a072738eSCyrill Gorcunov 	if (!p4_ht_thread(cpu)) {
225a072738eSCyrill Gorcunov 		if (!exclude_os)
226d814f301SCyrill Gorcunov 			escr |= P4_ESCR_T0_OS;
227a072738eSCyrill Gorcunov 		if (!exclude_usr)
228d814f301SCyrill Gorcunov 			escr |= P4_ESCR_T0_USR;
229a072738eSCyrill Gorcunov 	} else {
230a072738eSCyrill Gorcunov 		if (!exclude_os)
231d814f301SCyrill Gorcunov 			escr |= P4_ESCR_T1_OS;
232a072738eSCyrill Gorcunov 		if (!exclude_usr)
233d814f301SCyrill Gorcunov 			escr |= P4_ESCR_T1_USR;
234a072738eSCyrill Gorcunov 	}
235a072738eSCyrill Gorcunov 
236a072738eSCyrill Gorcunov 	return escr;
237a072738eSCyrill Gorcunov }
238a072738eSCyrill Gorcunov 
23939ef13a4SCyrill Gorcunov /*
24039ef13a4SCyrill Gorcunov  * This are the events which should be used in "Event Select"
24139ef13a4SCyrill Gorcunov  * field of ESCR register, they are like unique keys which allow
24239ef13a4SCyrill Gorcunov  * the kernel to determinate which CCCR and COUNTER should be
24339ef13a4SCyrill Gorcunov  * used to track an event
24439ef13a4SCyrill Gorcunov  */
245d814f301SCyrill Gorcunov enum P4_EVENTS {
246d814f301SCyrill Gorcunov 	P4_EVENT_TC_DELIVER_MODE,
247d814f301SCyrill Gorcunov 	P4_EVENT_BPU_FETCH_REQUEST,
248d814f301SCyrill Gorcunov 	P4_EVENT_ITLB_REFERENCE,
249d814f301SCyrill Gorcunov 	P4_EVENT_MEMORY_CANCEL,
250d814f301SCyrill Gorcunov 	P4_EVENT_MEMORY_COMPLETE,
251d814f301SCyrill Gorcunov 	P4_EVENT_LOAD_PORT_REPLAY,
252d814f301SCyrill Gorcunov 	P4_EVENT_STORE_PORT_REPLAY,
253d814f301SCyrill Gorcunov 	P4_EVENT_MOB_LOAD_REPLAY,
254d814f301SCyrill Gorcunov 	P4_EVENT_PAGE_WALK_TYPE,
255d814f301SCyrill Gorcunov 	P4_EVENT_BSQ_CACHE_REFERENCE,
256d814f301SCyrill Gorcunov 	P4_EVENT_IOQ_ALLOCATION,
257d814f301SCyrill Gorcunov 	P4_EVENT_IOQ_ACTIVE_ENTRIES,
258d814f301SCyrill Gorcunov 	P4_EVENT_FSB_DATA_ACTIVITY,
259d814f301SCyrill Gorcunov 	P4_EVENT_BSQ_ALLOCATION,
260d814f301SCyrill Gorcunov 	P4_EVENT_BSQ_ACTIVE_ENTRIES,
261d814f301SCyrill Gorcunov 	P4_EVENT_SSE_INPUT_ASSIST,
262d814f301SCyrill Gorcunov 	P4_EVENT_PACKED_SP_UOP,
263d814f301SCyrill Gorcunov 	P4_EVENT_PACKED_DP_UOP,
264d814f301SCyrill Gorcunov 	P4_EVENT_SCALAR_SP_UOP,
265d814f301SCyrill Gorcunov 	P4_EVENT_SCALAR_DP_UOP,
266d814f301SCyrill Gorcunov 	P4_EVENT_64BIT_MMX_UOP,
267d814f301SCyrill Gorcunov 	P4_EVENT_128BIT_MMX_UOP,
268d814f301SCyrill Gorcunov 	P4_EVENT_X87_FP_UOP,
269d814f301SCyrill Gorcunov 	P4_EVENT_TC_MISC,
270d814f301SCyrill Gorcunov 	P4_EVENT_GLOBAL_POWER_EVENTS,
271d814f301SCyrill Gorcunov 	P4_EVENT_TC_MS_XFER,
272d814f301SCyrill Gorcunov 	P4_EVENT_UOP_QUEUE_WRITES,
273d814f301SCyrill Gorcunov 	P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
274d814f301SCyrill Gorcunov 	P4_EVENT_RETIRED_BRANCH_TYPE,
275d814f301SCyrill Gorcunov 	P4_EVENT_RESOURCE_STALL,
276d814f301SCyrill Gorcunov 	P4_EVENT_WC_BUFFER,
277d814f301SCyrill Gorcunov 	P4_EVENT_B2B_CYCLES,
278d814f301SCyrill Gorcunov 	P4_EVENT_BNR,
279d814f301SCyrill Gorcunov 	P4_EVENT_SNOOP,
280d814f301SCyrill Gorcunov 	P4_EVENT_RESPONSE,
281d814f301SCyrill Gorcunov 	P4_EVENT_FRONT_END_EVENT,
282d814f301SCyrill Gorcunov 	P4_EVENT_EXECUTION_EVENT,
283d814f301SCyrill Gorcunov 	P4_EVENT_REPLAY_EVENT,
284d814f301SCyrill Gorcunov 	P4_EVENT_INSTR_RETIRED,
285d814f301SCyrill Gorcunov 	P4_EVENT_UOPS_RETIRED,
286d814f301SCyrill Gorcunov 	P4_EVENT_UOP_TYPE,
287d814f301SCyrill Gorcunov 	P4_EVENT_BRANCH_RETIRED,
288d814f301SCyrill Gorcunov 	P4_EVENT_MISPRED_BRANCH_RETIRED,
289d814f301SCyrill Gorcunov 	P4_EVENT_X87_ASSIST,
290d814f301SCyrill Gorcunov 	P4_EVENT_MACHINE_CLEAR,
291d814f301SCyrill Gorcunov 	P4_EVENT_INSTR_COMPLETED,
292d814f301SCyrill Gorcunov };
293d814f301SCyrill Gorcunov 
294d814f301SCyrill Gorcunov #define P4_OPCODE(event)		event##_OPCODE
295d814f301SCyrill Gorcunov #define P4_OPCODE_ESEL(opcode)		((opcode & 0x00ff) >> 0)
296d814f301SCyrill Gorcunov #define P4_OPCODE_EVNT(opcode)		((opcode & 0xff00) >> 8)
297d814f301SCyrill Gorcunov #define P4_OPCODE_PACK(event, sel)	(((event) << 8) | sel)
298d814f301SCyrill Gorcunov 
299a072738eSCyrill Gorcunov /*
300a072738eSCyrill Gorcunov  * Comments below the event represent ESCR restriction
301a072738eSCyrill Gorcunov  * for this event and counter index per ESCR
302a072738eSCyrill Gorcunov  *
303a072738eSCyrill Gorcunov  * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
304a072738eSCyrill Gorcunov  * processor builds (family 0FH, models 01H-02H). These MSRs
305a072738eSCyrill Gorcunov  * are not available on later versions, so that we don't use
306a072738eSCyrill Gorcunov  * them completely
307a072738eSCyrill Gorcunov  *
308a072738eSCyrill Gorcunov  * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
309a072738eSCyrill Gorcunov  * working so that we should not use this CCCR and respective
310a072738eSCyrill Gorcunov  * counter as result
311a072738eSCyrill Gorcunov  */
312d814f301SCyrill Gorcunov enum P4_EVENT_OPCODES {
313d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_TC_DELIVER_MODE)		= P4_OPCODE_PACK(0x01, 0x01),
314a072738eSCyrill Gorcunov 	/*
315a072738eSCyrill Gorcunov 	 * MSR_P4_TC_ESCR0:	4, 5
316a072738eSCyrill Gorcunov 	 * MSR_P4_TC_ESCR1:	6, 7
317a072738eSCyrill Gorcunov 	 */
318a072738eSCyrill Gorcunov 
319d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST)		= P4_OPCODE_PACK(0x03, 0x00),
320a072738eSCyrill Gorcunov 	/*
321a072738eSCyrill Gorcunov 	 * MSR_P4_BPU_ESCR0:	0, 1
322a072738eSCyrill Gorcunov 	 * MSR_P4_BPU_ESCR1:	2, 3
323a072738eSCyrill Gorcunov 	 */
324a072738eSCyrill Gorcunov 
325d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_ITLB_REFERENCE)		= P4_OPCODE_PACK(0x18, 0x03),
326a072738eSCyrill Gorcunov 	/*
327a072738eSCyrill Gorcunov 	 * MSR_P4_ITLB_ESCR0:	0, 1
328a072738eSCyrill Gorcunov 	 * MSR_P4_ITLB_ESCR1:	2, 3
329a072738eSCyrill Gorcunov 	 */
330a072738eSCyrill Gorcunov 
331d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_MEMORY_CANCEL)		= P4_OPCODE_PACK(0x02, 0x05),
332a072738eSCyrill Gorcunov 	/*
333a072738eSCyrill Gorcunov 	 * MSR_P4_DAC_ESCR0:	8, 9
334a072738eSCyrill Gorcunov 	 * MSR_P4_DAC_ESCR1:	10, 11
335a072738eSCyrill Gorcunov 	 */
336a072738eSCyrill Gorcunov 
337d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_MEMORY_COMPLETE)		= P4_OPCODE_PACK(0x08, 0x02),
338a072738eSCyrill Gorcunov 	/*
339a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR0:	8, 9
340a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR1:	10, 11
341a072738eSCyrill Gorcunov 	 */
342a072738eSCyrill Gorcunov 
343d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY)		= P4_OPCODE_PACK(0x04, 0x02),
344a072738eSCyrill Gorcunov 	/*
345a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR0:	8, 9
346a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR1:	10, 11
347a072738eSCyrill Gorcunov 	 */
348a072738eSCyrill Gorcunov 
349d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY)		= P4_OPCODE_PACK(0x05, 0x02),
350a072738eSCyrill Gorcunov 	/*
351a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR0:	8, 9
352a072738eSCyrill Gorcunov 	 * MSR_P4_SAAT_ESCR1:	10, 11
353a072738eSCyrill Gorcunov 	 */
354a072738eSCyrill Gorcunov 
355d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY)		= P4_OPCODE_PACK(0x03, 0x02),
356a072738eSCyrill Gorcunov 	/*
357a072738eSCyrill Gorcunov 	 * MSR_P4_MOB_ESCR0:	0, 1
358a072738eSCyrill Gorcunov 	 * MSR_P4_MOB_ESCR1:	2, 3
359a072738eSCyrill Gorcunov 	 */
360a072738eSCyrill Gorcunov 
361d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE)		= P4_OPCODE_PACK(0x01, 0x04),
362a072738eSCyrill Gorcunov 	/*
363a072738eSCyrill Gorcunov 	 * MSR_P4_PMH_ESCR0:	0, 1
364a072738eSCyrill Gorcunov 	 * MSR_P4_PMH_ESCR1:	2, 3
365a072738eSCyrill Gorcunov 	 */
366a072738eSCyrill Gorcunov 
367d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE)		= P4_OPCODE_PACK(0x0c, 0x07),
368a072738eSCyrill Gorcunov 	/*
369a072738eSCyrill Gorcunov 	 * MSR_P4_BSU_ESCR0:	0, 1
370a072738eSCyrill Gorcunov 	 * MSR_P4_BSU_ESCR1:	2, 3
371a072738eSCyrill Gorcunov 	 */
372a072738eSCyrill Gorcunov 
373d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_IOQ_ALLOCATION)		= P4_OPCODE_PACK(0x03, 0x06),
374a072738eSCyrill Gorcunov 	/*
375a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
376a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
377a072738eSCyrill Gorcunov 	 */
378a072738eSCyrill Gorcunov 
379d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES)		= P4_OPCODE_PACK(0x1a, 0x06),
380a072738eSCyrill Gorcunov 	/*
381a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
382a072738eSCyrill Gorcunov 	 */
383a072738eSCyrill Gorcunov 
384d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY)		= P4_OPCODE_PACK(0x17, 0x06),
385a072738eSCyrill Gorcunov 	/*
386a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
387a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
388a072738eSCyrill Gorcunov 	 */
389a072738eSCyrill Gorcunov 
390d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BSQ_ALLOCATION)		= P4_OPCODE_PACK(0x05, 0x07),
391a072738eSCyrill Gorcunov 	/*
392a072738eSCyrill Gorcunov 	 * MSR_P4_BSU_ESCR0:	0, 1
393a072738eSCyrill Gorcunov 	 */
394a072738eSCyrill Gorcunov 
395d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES)		= P4_OPCODE_PACK(0x06, 0x07),
396a072738eSCyrill Gorcunov 	/*
3978ea7f544SLin Ming 	 * NOTE: no ESCR name in docs, it's guessed
398a072738eSCyrill Gorcunov 	 * MSR_P4_BSU_ESCR1:	2, 3
399a072738eSCyrill Gorcunov 	 */
400a072738eSCyrill Gorcunov 
401d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST)		= P4_OPCODE_PACK(0x34, 0x01),
402a072738eSCyrill Gorcunov 	/*
403e4495262SCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
404e4495262SCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
405a072738eSCyrill Gorcunov 	 */
406a072738eSCyrill Gorcunov 
407d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_PACKED_SP_UOP)		= P4_OPCODE_PACK(0x08, 0x01),
408a072738eSCyrill Gorcunov 	/*
409a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
410a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
411a072738eSCyrill Gorcunov 	 */
412a072738eSCyrill Gorcunov 
413d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_PACKED_DP_UOP)		= P4_OPCODE_PACK(0x0c, 0x01),
414a072738eSCyrill Gorcunov 	/*
415a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
416a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
417a072738eSCyrill Gorcunov 	 */
418a072738eSCyrill Gorcunov 
419d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_SCALAR_SP_UOP)		= P4_OPCODE_PACK(0x0a, 0x01),
420a072738eSCyrill Gorcunov 	/*
421a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
422a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
423a072738eSCyrill Gorcunov 	 */
424a072738eSCyrill Gorcunov 
425d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_SCALAR_DP_UOP)		= P4_OPCODE_PACK(0x0e, 0x01),
426a072738eSCyrill Gorcunov 	/*
427a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
428a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
429a072738eSCyrill Gorcunov 	 */
430a072738eSCyrill Gorcunov 
431d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_64BIT_MMX_UOP)		= P4_OPCODE_PACK(0x02, 0x01),
432a072738eSCyrill Gorcunov 	/*
433a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
434a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
435a072738eSCyrill Gorcunov 	 */
436a072738eSCyrill Gorcunov 
437d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_128BIT_MMX_UOP)		= P4_OPCODE_PACK(0x1a, 0x01),
438a072738eSCyrill Gorcunov 	/*
439a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
440a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
441a072738eSCyrill Gorcunov 	 */
442a072738eSCyrill Gorcunov 
443d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_X87_FP_UOP)			= P4_OPCODE_PACK(0x04, 0x01),
444a072738eSCyrill Gorcunov 	/*
445a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR0:	8, 9
446a072738eSCyrill Gorcunov 	 * MSR_P4_FIRM_ESCR1:	10, 11
447a072738eSCyrill Gorcunov 	 */
448a072738eSCyrill Gorcunov 
449d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_TC_MISC)			= P4_OPCODE_PACK(0x06, 0x01),
450a072738eSCyrill Gorcunov 	/*
451a072738eSCyrill Gorcunov 	 * MSR_P4_TC_ESCR0:	4, 5
452a072738eSCyrill Gorcunov 	 * MSR_P4_TC_ESCR1:	6, 7
453a072738eSCyrill Gorcunov 	 */
454a072738eSCyrill Gorcunov 
455d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS)		= P4_OPCODE_PACK(0x13, 0x06),
456a072738eSCyrill Gorcunov 	/*
457a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
458a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
459a072738eSCyrill Gorcunov 	 */
460a072738eSCyrill Gorcunov 
461d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_TC_MS_XFER)			= P4_OPCODE_PACK(0x05, 0x00),
462a072738eSCyrill Gorcunov 	/*
463a072738eSCyrill Gorcunov 	 * MSR_P4_MS_ESCR0:	4, 5
464a072738eSCyrill Gorcunov 	 * MSR_P4_MS_ESCR1:	6, 7
465a072738eSCyrill Gorcunov 	 */
466a072738eSCyrill Gorcunov 
467d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES)		= P4_OPCODE_PACK(0x09, 0x00),
468a072738eSCyrill Gorcunov 	/*
469a072738eSCyrill Gorcunov 	 * MSR_P4_MS_ESCR0:	4, 5
470a072738eSCyrill Gorcunov 	 * MSR_P4_MS_ESCR1:	6, 7
471a072738eSCyrill Gorcunov 	 */
472a072738eSCyrill Gorcunov 
473d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE)	= P4_OPCODE_PACK(0x05, 0x02),
474a072738eSCyrill Gorcunov 	/*
475a072738eSCyrill Gorcunov 	 * MSR_P4_TBPU_ESCR0:	4, 5
4769c8c6badSCyrill Gorcunov 	 * MSR_P4_TBPU_ESCR1:	6, 7
477a072738eSCyrill Gorcunov 	 */
478a072738eSCyrill Gorcunov 
479d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE)		= P4_OPCODE_PACK(0x04, 0x02),
480a072738eSCyrill Gorcunov 	/*
481a072738eSCyrill Gorcunov 	 * MSR_P4_TBPU_ESCR0:	4, 5
4829c8c6badSCyrill Gorcunov 	 * MSR_P4_TBPU_ESCR1:	6, 7
483a072738eSCyrill Gorcunov 	 */
484a072738eSCyrill Gorcunov 
485d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_RESOURCE_STALL)		= P4_OPCODE_PACK(0x01, 0x01),
486a072738eSCyrill Gorcunov 	/*
487a072738eSCyrill Gorcunov 	 * MSR_P4_ALF_ESCR0:	12, 13, 16
488a072738eSCyrill Gorcunov 	 * MSR_P4_ALF_ESCR1:	14, 15, 17
489a072738eSCyrill Gorcunov 	 */
490a072738eSCyrill Gorcunov 
491d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_WC_BUFFER)			= P4_OPCODE_PACK(0x05, 0x05),
492a072738eSCyrill Gorcunov 	/*
493a072738eSCyrill Gorcunov 	 * MSR_P4_DAC_ESCR0:	8, 9
494a072738eSCyrill Gorcunov 	 * MSR_P4_DAC_ESCR1:	10, 11
495a072738eSCyrill Gorcunov 	 */
496a072738eSCyrill Gorcunov 
497d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_B2B_CYCLES)			= P4_OPCODE_PACK(0x16, 0x03),
498a072738eSCyrill Gorcunov 	/*
499a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
500a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
501a072738eSCyrill Gorcunov 	 */
502a072738eSCyrill Gorcunov 
503d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BNR)				= P4_OPCODE_PACK(0x08, 0x03),
504a072738eSCyrill Gorcunov 	/*
505a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
506a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
507a072738eSCyrill Gorcunov 	 */
508a072738eSCyrill Gorcunov 
509d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_SNOOP)			= P4_OPCODE_PACK(0x06, 0x03),
510a072738eSCyrill Gorcunov 	/*
511a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
512a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
513a072738eSCyrill Gorcunov 	 */
514a072738eSCyrill Gorcunov 
515d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_RESPONSE)			= P4_OPCODE_PACK(0x04, 0x03),
516a072738eSCyrill Gorcunov 	/*
517a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR0:	0, 1
518a072738eSCyrill Gorcunov 	 * MSR_P4_FSB_ESCR1:	2, 3
519a072738eSCyrill Gorcunov 	 */
520a072738eSCyrill Gorcunov 
521d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_FRONT_END_EVENT)		= P4_OPCODE_PACK(0x08, 0x05),
522a072738eSCyrill Gorcunov 	/*
523a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
524a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
525a072738eSCyrill Gorcunov 	 */
526a072738eSCyrill Gorcunov 
527d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_EXECUTION_EVENT)		= P4_OPCODE_PACK(0x0c, 0x05),
528a072738eSCyrill Gorcunov 	/*
529a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
530a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
531a072738eSCyrill Gorcunov 	 */
532a072738eSCyrill Gorcunov 
533d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_REPLAY_EVENT)		= P4_OPCODE_PACK(0x09, 0x05),
534a072738eSCyrill Gorcunov 	/*
535a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
536a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
537a072738eSCyrill Gorcunov 	 */
538a072738eSCyrill Gorcunov 
539d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_INSTR_RETIRED)		= P4_OPCODE_PACK(0x02, 0x04),
540a072738eSCyrill Gorcunov 	/*
541e4495262SCyrill Gorcunov 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
542e4495262SCyrill Gorcunov 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
543a072738eSCyrill Gorcunov 	 */
544a072738eSCyrill Gorcunov 
545d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_UOPS_RETIRED)		= P4_OPCODE_PACK(0x01, 0x04),
546a072738eSCyrill Gorcunov 	/*
5478ea7f544SLin Ming 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
5488ea7f544SLin Ming 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
549a072738eSCyrill Gorcunov 	 */
550a072738eSCyrill Gorcunov 
551d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_UOP_TYPE)			= P4_OPCODE_PACK(0x02, 0x02),
552a072738eSCyrill Gorcunov 	/*
553a072738eSCyrill Gorcunov 	 * MSR_P4_RAT_ESCR0:	12, 13, 16
554a072738eSCyrill Gorcunov 	 * MSR_P4_RAT_ESCR1:	14, 15, 17
555a072738eSCyrill Gorcunov 	 */
556a072738eSCyrill Gorcunov 
557d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_BRANCH_RETIRED)		= P4_OPCODE_PACK(0x06, 0x05),
558a072738eSCyrill Gorcunov 	/*
559a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
560a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
561a072738eSCyrill Gorcunov 	 */
562a072738eSCyrill Gorcunov 
563d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED)	= P4_OPCODE_PACK(0x03, 0x04),
564a072738eSCyrill Gorcunov 	/*
565a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
566a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
567a072738eSCyrill Gorcunov 	 */
568a072738eSCyrill Gorcunov 
569d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_X87_ASSIST)			= P4_OPCODE_PACK(0x03, 0x05),
570a072738eSCyrill Gorcunov 	/*
571a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
572a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
573a072738eSCyrill Gorcunov 	 */
574a072738eSCyrill Gorcunov 
575d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_MACHINE_CLEAR)		= P4_OPCODE_PACK(0x02, 0x05),
576a072738eSCyrill Gorcunov 	/*
577a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
578a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
579a072738eSCyrill Gorcunov 	 */
580a072738eSCyrill Gorcunov 
581d814f301SCyrill Gorcunov 	P4_OPCODE(P4_EVENT_INSTR_COMPLETED)		= P4_OPCODE_PACK(0x07, 0x04),
582a072738eSCyrill Gorcunov 	/*
583a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
584a072738eSCyrill Gorcunov 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
585a072738eSCyrill Gorcunov 	 */
586a072738eSCyrill Gorcunov };
587a072738eSCyrill Gorcunov 
588d814f301SCyrill Gorcunov /*
589d814f301SCyrill Gorcunov  * a caller should use P4_ESCR_EMASK_NAME helper to
590d814f301SCyrill Gorcunov  * pick the EventMask needed, for example
591d814f301SCyrill Gorcunov  *
59239ef13a4SCyrill Gorcunov  *	P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD)
593d814f301SCyrill Gorcunov  */
594d814f301SCyrill Gorcunov enum P4_ESCR_EMASKS {
595d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
596d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
597d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
598d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
599d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
600d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
601d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
602d814f301SCyrill Gorcunov 
603d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
604d814f301SCyrill Gorcunov 
605d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
606d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
607d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
608d814f301SCyrill Gorcunov 
609d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
610d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
611d814f301SCyrill Gorcunov 
612d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
613d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
614d814f301SCyrill Gorcunov 
615d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
616d814f301SCyrill Gorcunov 
617d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
618d814f301SCyrill Gorcunov 
619d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
620d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
621d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
622d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
623d814f301SCyrill Gorcunov 
624d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
625d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
626d814f301SCyrill Gorcunov 
627d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
628d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
629d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
630d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
631d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
632d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
633d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
634d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
635d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
636d814f301SCyrill Gorcunov 
637d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
638d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
639d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
640d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
641d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
642d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
643d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
644d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
645d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
646d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
647d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
648d814f301SCyrill Gorcunov 
649d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
650d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
651d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
652d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
653d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
654d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
655d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
656d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
657d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
658d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
659d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
660d814f301SCyrill Gorcunov 
661d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
662d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
663d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
664d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
665d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
666d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
667d814f301SCyrill Gorcunov 
668d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
669d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
670d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
671d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
672d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
673d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
674d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
675d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
676d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
677d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
678d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
679d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
680d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
681d814f301SCyrill Gorcunov 
682d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
683d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
684d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
685d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
686d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
687d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
688d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
689d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
690d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
691d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
692d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
693d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
694d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
695d814f301SCyrill Gorcunov 
696d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
697d814f301SCyrill Gorcunov 
698d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
699d814f301SCyrill Gorcunov 
700d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
701d814f301SCyrill Gorcunov 
702d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
703d814f301SCyrill Gorcunov 
704d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
705d814f301SCyrill Gorcunov 
706d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
707d814f301SCyrill Gorcunov 
708d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
709d814f301SCyrill Gorcunov 
710d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
711d814f301SCyrill Gorcunov 
712d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
713d814f301SCyrill Gorcunov 
714d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
715d814f301SCyrill Gorcunov 
716d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
717d814f301SCyrill Gorcunov 
718d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
719d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
720d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
721d814f301SCyrill Gorcunov 
722d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
723d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
724d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
725d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
726d814f301SCyrill Gorcunov 
727d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
728d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
729d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
730d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
731d814f301SCyrill Gorcunov 
732d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
733d814f301SCyrill Gorcunov 
734d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
735d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
736d814f301SCyrill Gorcunov 
737d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
738d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
739d814f301SCyrill Gorcunov 
740d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
741d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
742d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
743d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
744d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
745d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
746d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
747d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
748d814f301SCyrill Gorcunov 
749d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
750d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
751d814f301SCyrill Gorcunov 
752d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
753d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
754d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
755d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
756d814f301SCyrill Gorcunov 
757d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
758d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
759d814f301SCyrill Gorcunov 
760d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
761d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
762d814f301SCyrill Gorcunov 
763d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
764d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
765d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
766d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
767d814f301SCyrill Gorcunov 
768d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
769d814f301SCyrill Gorcunov 
770d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
771d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
772d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
773d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
774d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
775d814f301SCyrill Gorcunov 
776d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
777d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
778d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
779d814f301SCyrill Gorcunov 
780d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
781d814f301SCyrill Gorcunov 	P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
782d814f301SCyrill Gorcunov };
783d814f301SCyrill Gorcunov 
78439ef13a4SCyrill Gorcunov /*
78539ef13a4SCyrill Gorcunov  * Note we have UOP and PEBS bits reserved for now
78639ef13a4SCyrill Gorcunov  * just in case if we will need them once
78739ef13a4SCyrill Gorcunov  */
7885ac2b5c2SIngo Molnar #define P4_PEBS_CONFIG_ENABLE		(1ULL << 7)
7895ac2b5c2SIngo Molnar #define P4_PEBS_CONFIG_UOP_TAG		(1ULL << 8)
7905ac2b5c2SIngo Molnar #define P4_PEBS_CONFIG_METRIC_MASK	0x3FLL
7915ac2b5c2SIngo Molnar #define P4_PEBS_CONFIG_MASK		0xFFLL
79239ef13a4SCyrill Gorcunov 
79339ef13a4SCyrill Gorcunov /*
79439ef13a4SCyrill Gorcunov  * mem: Only counters MSR_IQ_COUNTER4 (16) and
79539ef13a4SCyrill Gorcunov  * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
79639ef13a4SCyrill Gorcunov  */
7975ac2b5c2SIngo Molnar #define P4_PEBS_ENABLE			0x02000000ULL
7985ac2b5c2SIngo Molnar #define P4_PEBS_ENABLE_UOP_TAG		0x01000000ULL
799d814f301SCyrill Gorcunov 
80039ef13a4SCyrill Gorcunov #define p4_config_unpack_metric(v)	(((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
80139ef13a4SCyrill Gorcunov #define p4_config_unpack_pebs(v)	(((u64)(v)) & P4_PEBS_CONFIG_MASK)
802d814f301SCyrill Gorcunov 
80339ef13a4SCyrill Gorcunov #define p4_config_pebs_has(v, mask)	(p4_config_unpack_pebs(v) & (mask))
804d814f301SCyrill Gorcunov 
80539ef13a4SCyrill Gorcunov enum P4_PEBS_METRIC {
80639ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__none,
807d814f301SCyrill Gorcunov 
80839ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__1stl_cache_load_miss_retired,
80939ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__2ndl_cache_load_miss_retired,
81039ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__dtlb_load_miss_retired,
81139ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__dtlb_store_miss_retired,
81239ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__dtlb_all_miss_retired,
81339ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__tagged_mispred_branch,
81439ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__mob_load_replay_retired,
81539ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__split_load_retired,
81639ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__split_store_retired,
817d814f301SCyrill Gorcunov 
81839ef13a4SCyrill Gorcunov 	P4_PEBS_METRIC__max
819cb7d6b50SLin Ming };
820cb7d6b50SLin Ming 
821af86da53SCyrill Gorcunov /*
822af86da53SCyrill Gorcunov  * Notes on internal configuration of ESCR+CCCR tuples
823af86da53SCyrill Gorcunov  *
824af86da53SCyrill Gorcunov  * Since P4 has quite the different architecture of
825af86da53SCyrill Gorcunov  * performance registers in compare with "architectural"
826af86da53SCyrill Gorcunov  * once and we have on 64 bits to keep configuration
827af86da53SCyrill Gorcunov  * of performance event, the following trick is used.
828af86da53SCyrill Gorcunov  *
829af86da53SCyrill Gorcunov  * 1) Since both ESCR and CCCR registers have only low
830af86da53SCyrill Gorcunov  *    32 bits valuable, we pack them into a single 64 bit
831af86da53SCyrill Gorcunov  *    configuration. Low 32 bits of such config correspond
832af86da53SCyrill Gorcunov  *    to low 32 bits of CCCR register and high 32 bits
833af86da53SCyrill Gorcunov  *    correspond to low 32 bits of ESCR register.
834af86da53SCyrill Gorcunov  *
835af86da53SCyrill Gorcunov  * 2) The meaning of every bit of such config field can
836af86da53SCyrill Gorcunov  *    be found in Intel SDM but it should be noted that
837af86da53SCyrill Gorcunov  *    we "borrow" some reserved bits for own usage and
838af86da53SCyrill Gorcunov  *    clean them or set to a proper value when we do
839af86da53SCyrill Gorcunov  *    a real write to hardware registers.
840af86da53SCyrill Gorcunov  *
841af86da53SCyrill Gorcunov  * 3) The format of bits of config is the following
842af86da53SCyrill Gorcunov  *    and should be either 0 or set to some predefined
843af86da53SCyrill Gorcunov  *    values:
844af86da53SCyrill Gorcunov  *
845af86da53SCyrill Gorcunov  *    Low 32 bits
846af86da53SCyrill Gorcunov  *    -----------
847af86da53SCyrill Gorcunov  *      0-6: P4_PEBS_METRIC enum
848af86da53SCyrill Gorcunov  *     7-11:                    reserved
849af86da53SCyrill Gorcunov  *       12:                    reserved (Enable)
850af86da53SCyrill Gorcunov  *    13-15:                    reserved (ESCR select)
851af86da53SCyrill Gorcunov  *    16-17: Active Thread
852af86da53SCyrill Gorcunov  *       18: Compare
853af86da53SCyrill Gorcunov  *       19: Complement
854af86da53SCyrill Gorcunov  *    20-23: Threshold
855af86da53SCyrill Gorcunov  *       24: Edge
856af86da53SCyrill Gorcunov  *       25:                    reserved (FORCE_OVF)
857af86da53SCyrill Gorcunov  *       26:                    reserved (OVF_PMI_T0)
858af86da53SCyrill Gorcunov  *       27:                    reserved (OVF_PMI_T1)
859af86da53SCyrill Gorcunov  *    28-29:                    reserved
860af86da53SCyrill Gorcunov  *       30:                    reserved (Cascade)
861af86da53SCyrill Gorcunov  *       31:                    reserved (OVF)
862af86da53SCyrill Gorcunov  *
863af86da53SCyrill Gorcunov  *    High 32 bits
864af86da53SCyrill Gorcunov  *    ------------
865af86da53SCyrill Gorcunov  *        0:                    reserved (T1_USR)
866af86da53SCyrill Gorcunov  *        1:                    reserved (T1_OS)
867af86da53SCyrill Gorcunov  *        2:                    reserved (T0_USR)
868af86da53SCyrill Gorcunov  *        3:                    reserved (T0_OS)
869af86da53SCyrill Gorcunov  *        4: Tag Enable
870af86da53SCyrill Gorcunov  *      5-8: Tag Value
871af86da53SCyrill Gorcunov  *     9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
872af86da53SCyrill Gorcunov  *    25-30: enum P4_EVENTS
873af86da53SCyrill Gorcunov  *       31:                    reserved (HT thread)
874af86da53SCyrill Gorcunov  */
875af86da53SCyrill Gorcunov 
876a072738eSCyrill Gorcunov #endif /* PERF_EVENT_P4_H */
87739ef13a4SCyrill Gorcunov 
878