Lines Matching +full:only +full:- +full:1 +full:- +full:8 +full:v
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
34 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
73 * The Integrator/AP core clock can only access the low eight in vco_get()
74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
75 * r is hardwired to 22 and output divider s is hardwired to 1 in vco_get()
77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get()
78 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. in vco_get()
80 if (icst->ctype == ICST_INTEGRATOR_AP_CM) { in vco_get()
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
82 vco->r = 22; in vco_get()
83 vco->s = 1; in vco_get()
88 * The Integrator/AP system clock on the base board can only in vco_get()
89 * access the low eight bits of the v PLL divider. Bit 8 is tied low in vco_get()
93 * page 3-16. in vco_get()
95 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { in vco_get()
96 vco->v = val & INTEGRATOR_AP_SYS_BITS; in vco_get()
97 vco->r = 46; in vco_get()
98 vco->s = 3; in vco_get()
106 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the in vco_get()
107 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies in vco_get()
110 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { in vco_get()
113 vco->v = divxy ? 17 : 14; in vco_get()
114 vco->r = divxy ? 22 : 14; in vco_get()
115 vco->s = 1; in vco_get()
121 * of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
123 * in bits 8 thru 10 according to the document in vco_get()
125 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10. in vco_get()
127 if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { in vco_get()
128 vco->v = val & 0xFF; in vco_get()
129 vco->r = 22; in vco_get()
130 vco->s = (val >> 8) & 7; in vco_get()
134 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { in vco_get()
135 vco->v = (val >> 12) & 0xFF; in vco_get()
136 vco->r = 22; in vco_get()
137 vco->s = (val >> 20) & 7; in vco_get()
141 vco->v = val & 0x1ff; in vco_get()
142 vco->r = (val >> 9) & 0x7f; in vco_get()
143 vco->s = (val >> 16) & 03; in vco_get()
148 * vco_set() - commit changes to an ICST VCO
159 switch (icst->ctype) { in vco_set()
162 val = vco.v & 0xFF; in vco_set()
163 if (vco.v & 0x100) in vco_set()
164 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
165 if (vco.s != 1) in vco_set()
166 pr_err("ICST error: tried to use VOD != 1\n"); in vco_set()
172 val = vco.v & 0xFF; in vco_set()
173 if (vco.v & 0x100) in vco_set()
174 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
176 pr_err("ICST error: tried to use VOD != 1\n"); in vco_set()
182 val = (vco.v & 0xFF) | vco.s << 8; in vco_set()
183 if (vco.v & 0x100) in vco_set()
184 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
190 val = ((vco.v & 0xFF) << 12) | (vco.s << 20); in vco_set()
191 if (vco.v & 0x100) in vco_set()
192 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
199 val = vco.v | (vco.r << 9) | (vco.s << 16); in vco_set()
206 ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL); in vco_set()
209 ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val); in vco_set()
213 ret = regmap_write(icst->map, icst->lockreg_off, 0); in vco_set()
227 icst->params->ref = parent_rate; in icst_recalc_rate()
233 icst->rate = icst_hz(icst->params, vco); in icst_recalc_rate()
234 return icst->rate; in icst_recalc_rate()
243 if (icst->ctype == ICST_INTEGRATOR_AP_CM || in icst_determine_rate()
244 icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { in icst_determine_rate()
245 if (req->rate <= 12000000) in icst_determine_rate()
246 req->rate = 12000000; in icst_determine_rate()
247 else if (req->rate >= 160000000) in icst_determine_rate()
248 req->rate = 160000000; in icst_determine_rate()
251 req->rate = DIV_ROUND_CLOSEST(req->rate, 1000000) * 1000000; in icst_determine_rate()
257 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { in icst_determine_rate()
258 if (req->rate <= 6000000) in icst_determine_rate()
259 req->rate = 6000000; in icst_determine_rate()
260 else if (req->rate >= 66000000) in icst_determine_rate()
261 req->rate = 66000000; in icst_determine_rate()
264 req->rate = DIV_ROUND_CLOSEST(req->rate, 500000) * 500000; in icst_determine_rate()
270 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { in icst_determine_rate()
272 if (req->rate <= 3000000) in icst_determine_rate()
273 req->rate = 3000000; in icst_determine_rate()
274 else if (req->rate >= 50000000) in icst_determine_rate()
275 req->rate = 5000000; in icst_determine_rate()
278 req->rate = DIV_ROUND_CLOSEST(req->rate, 250000) * 250000; in icst_determine_rate()
284 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { in icst_determine_rate()
289 if (req->rate <= 25000000 || req->rate < 29000000) in icst_determine_rate()
290 req->rate = 25000000; in icst_determine_rate()
293 req->rate = 33000000; in icst_determine_rate()
299 vco = icst_hz_to_vco(icst->params, req->rate); in icst_determine_rate()
300 req->rate = icst_hz(icst->params, vco); in icst_determine_rate()
311 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { in icst_set_rate()
323 return -EINVAL; in icst_set_rate()
325 ret = regmap_write(icst->map, icst->lockreg_off, in icst_set_rate()
329 ret = regmap_update_bits(icst->map, icst->vcoreg_off, in icst_set_rate()
335 ret = regmap_write(icst->map, icst->lockreg_off, 0); in icst_set_rate()
342 icst->params->ref = parent_rate; in icst_set_rate()
343 vco = icst_hz_to_vco(icst->params, rate); in icst_set_rate()
344 icst->rate = icst_hz(icst->params, vco); in icst_set_rate()
368 return ERR_PTR(-ENOMEM); in icst_clk_setup()
370 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL); in icst_clk_setup()
373 return ERR_PTR(-ENOMEM); in icst_clk_setup()
380 init.num_parents = (parent_name ? 1 : 0); in icst_clk_setup()
381 icst->map = map; in icst_clk_setup()
382 icst->hw.init = &init; in icst_clk_setup()
383 icst->params = pclone; in icst_clk_setup()
384 icst->vcoreg_off = desc->vco_offset; in icst_clk_setup()
385 icst->lockreg_off = desc->lock_offset; in icst_clk_setup()
386 icst->ctype = ctype; in icst_clk_setup()
388 clk = clk_register(dev, &icst->hw); in icst_clk_setup()
423 * In a device tree, an memory-mapped ICST clock appear as a child
424 * of a syscon node. Assume this and probe it only as a child of a
431 .vd_min = 8,
442 .vd_min = 4 + 8,
443 .vd_max = 511 + 8,
444 .rd_min = 1 + 2,
461 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
523 of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) { in of_syscon_icst_setup()
527 if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) { in of_syscon_icst_setup()
532 if (of_device_is_compatible(np, "arm,syscon-icst525")) { in of_syscon_icst_setup()
535 } else if (of_device_is_compatible(np, "arm,syscon-icst307")) { in of_syscon_icst_setup()
538 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) { in of_syscon_icst_setup()
541 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) { in of_syscon_icst_setup()
544 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) { in of_syscon_icst_setup()
547 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) { in of_syscon_icst_setup()
550 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) { in of_syscon_icst_setup()
573 "arm,syscon-icst525", of_syscon_icst_setup);
575 "arm,syscon-icst307", of_syscon_icst_setup);
577 "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
579 "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
581 "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
583 "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
585 "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);