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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP4+ Remoteproc Devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
35 lines can also be routed to different processor sub-systems on DRA7xx as they
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm816x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm816.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/omap.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
H A Domap4.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
[all …]
H A Domap5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
H A Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
[all …]
H A Domap4-l4.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
4 power-domains = <&prm_core>;
6 clock-names = "fck";
10 reg-names = "ap", "la", "ia0";
11 #address-cells = <1>;
12 #size-cells = <1>;
22 compatible = "simple-pm-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
[all …]
H A Domap5-l4.dtsi2 compatible = "ti,omap5-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_core>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
21 compatible = "simple-pm-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
55 target-module@2000 { /* 0x4a002000, ap 3 44.0 */
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
24 #address-cells = <2>;
25 #size-cells = <2>;
27 #interrupt-cells = <3>;
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H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
/linux/drivers/phy/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
58 the mailbox. The mailbox is present only in omap4 and the register to
59 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
/linux/drivers/mailbox/
H A Domap-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP mailbox driver
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
26 #include "mailbox.h"
97 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
103 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
106 /* Mailbox FIFO handle functions */
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig MAILBOX config
3 bool "Mailbox Hardware Support"
5 Mailbox is a framework to control hardware communication between
6 on-chip processors through queued messages and interrupt driven
9 if MAILBOX
12 tristate "ARM MHU Mailbox"
16 The controller has 3 mailbox channels, the last of which can be
20 tristate "ARM MHUv2 Mailbox"
27 tristate "ARM MHUv3 Mailbox"
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/linux/drivers/remoteproc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
30 select MAILBOX
41 select MAILBOX
54 This can be either built-in or a loadable module.
71 select MAILBOX
75 and DSP on OMAP4) via the remote processor framework.
77 Currently only supported on OMAP4.
80 use-cases to run on your platform (multimedia codecs are
105 Required for Suspend-to-RAM on AM33xx and AM43xx SoCs. Also needed
111 tristate "DA8xx/OMAP-L13x remoteproc support"
[all …]
/linux/arch/arm/mach-omap2/
H A Domap_hwmod_81xx_data.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
11 #include <linux/platform_data/hsmmc-omap.h>
25 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
78 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
79 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
80 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
81 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
82 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
83 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
16 - power : Should be "50". This signifies the controller can supply up to
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
[all …]

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