1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2724ba675SRob Herring&l4_cfg { /* 0x4a000000 */ 3724ba675SRob Herring compatible = "ti,omap4-l4-cfg", "simple-pm-bus"; 4724ba675SRob Herring power-domains = <&prm_core>; 5724ba675SRob Herring clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; 6724ba675SRob Herring clock-names = "fck"; 7724ba675SRob Herring reg = <0x4a000000 0x800>, 8724ba675SRob Herring <0x4a000800 0x800>, 9724ba675SRob Herring <0x4a001000 0x1000>; 10724ba675SRob Herring reg-names = "ap", "la", "ia0"; 11724ba675SRob Herring #address-cells = <1>; 12724ba675SRob Herring #size-cells = <1>; 13724ba675SRob Herring ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 14724ba675SRob Herring <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 15724ba675SRob Herring <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 16724ba675SRob Herring <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 17724ba675SRob Herring <0x00200000 0x4a200000 0x080000>, /* segment 4 */ 18724ba675SRob Herring <0x00280000 0x4a280000 0x080000>, /* segment 5 */ 19724ba675SRob Herring <0x00300000 0x4a300000 0x080000>; /* segment 6 */ 20724ba675SRob Herring 21724ba675SRob Herring segment@0 { /* 0x4a000000 */ 22724ba675SRob Herring compatible = "simple-pm-bus"; 23724ba675SRob Herring #address-cells = <1>; 24724ba675SRob Herring #size-cells = <1>; 25724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 26724ba675SRob Herring <0x00001000 0x00001000 0x001000>, /* ap 1 */ 27724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 2 */ 28724ba675SRob Herring <0x00002000 0x00002000 0x001000>, /* ap 3 */ 29724ba675SRob Herring <0x00003000 0x00003000 0x001000>, /* ap 4 */ 30724ba675SRob Herring <0x00004000 0x00004000 0x001000>, /* ap 5 */ 31724ba675SRob Herring <0x00005000 0x00005000 0x001000>, /* ap 6 */ 32724ba675SRob Herring <0x00056000 0x00056000 0x001000>, /* ap 7 */ 33724ba675SRob Herring <0x00057000 0x00057000 0x001000>, /* ap 8 */ 34724ba675SRob Herring <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ 35724ba675SRob Herring <0x00058000 0x00058000 0x004000>, /* ap 10 */ 36724ba675SRob Herring <0x00062000 0x00062000 0x001000>, /* ap 11 */ 37724ba675SRob Herring <0x00063000 0x00063000 0x001000>, /* ap 12 */ 38724ba675SRob Herring <0x00008000 0x00008000 0x002000>, /* ap 23 */ 39724ba675SRob Herring <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ 40724ba675SRob Herring <0x00066000 0x00066000 0x001000>, /* ap 25 */ 41724ba675SRob Herring <0x00067000 0x00067000 0x001000>, /* ap 26 */ 42724ba675SRob Herring <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ 43724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 81 */ 44724ba675SRob Herring <0x00064000 0x00064000 0x001000>, /* ap 86 */ 45724ba675SRob Herring <0x00065000 0x00065000 0x001000>; /* ap 87 */ 46724ba675SRob Herring 47724ba675SRob Herring target-module@2000 { /* 0x4a002000, ap 3 06.0 */ 48724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 49724ba675SRob Herring reg = <0x2000 0x4>, 50724ba675SRob Herring <0x2010 0x4>; 51724ba675SRob Herring reg-names = "rev", "sysc"; 52724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 53724ba675SRob Herring <SYSC_IDLE_NO>, 54724ba675SRob Herring <SYSC_IDLE_SMART>, 55724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 56724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 57724ba675SRob Herring #address-cells = <1>; 58724ba675SRob Herring #size-cells = <1>; 59724ba675SRob Herring ranges = <0x0 0x2000 0x1000>; 60724ba675SRob Herring 61724ba675SRob Herring omap4_scm_core: scm@0 { 62724ba675SRob Herring compatible = "ti,omap4-scm-core", "simple-bus"; 63724ba675SRob Herring reg = <0x0 0x1000>; 64724ba675SRob Herring #address-cells = <1>; 65724ba675SRob Herring #size-cells = <1>; 66724ba675SRob Herring ranges = <0 0 0x1000>; 67724ba675SRob Herring 68724ba675SRob Herring scm_conf: scm_conf@0 { 69724ba675SRob Herring compatible = "syscon"; 70724ba675SRob Herring reg = <0x0 0x800>; 71724ba675SRob Herring #address-cells = <1>; 72724ba675SRob Herring #size-cells = <1>; 73724ba675SRob Herring }; 74724ba675SRob Herring 75724ba675SRob Herring omap_control_usb2phy: control-phy@300 { 76724ba675SRob Herring compatible = "ti,control-phy-usb2"; 77724ba675SRob Herring reg = <0x300 0x4>; 78724ba675SRob Herring reg-names = "power"; 79724ba675SRob Herring }; 80724ba675SRob Herring 81724ba675SRob Herring omap_control_usbotg: control-phy@33c { 82724ba675SRob Herring compatible = "ti,control-phy-otghs"; 83724ba675SRob Herring reg = <0x33c 0x4>; 84724ba675SRob Herring reg-names = "otghs_control"; 85724ba675SRob Herring }; 86724ba675SRob Herring }; 87724ba675SRob Herring }; 88724ba675SRob Herring 89724ba675SRob Herring target-module@4000 { /* 0x4a004000, ap 5 02.0 */ 90724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 91724ba675SRob Herring reg = <0x4000 0x4>; 92724ba675SRob Herring reg-names = "rev"; 93724ba675SRob Herring #address-cells = <1>; 94724ba675SRob Herring #size-cells = <1>; 95724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 96724ba675SRob Herring 97724ba675SRob Herring cm1: cm1@0 { 98724ba675SRob Herring compatible = "ti,omap4-cm1", "simple-bus"; 99724ba675SRob Herring reg = <0x0 0x2000>; 100724ba675SRob Herring #address-cells = <1>; 101724ba675SRob Herring #size-cells = <1>; 102724ba675SRob Herring ranges = <0 0 0x2000>; 103724ba675SRob Herring 104724ba675SRob Herring cm1_clocks: clocks { 105724ba675SRob Herring #address-cells = <1>; 106724ba675SRob Herring #size-cells = <0>; 107724ba675SRob Herring }; 108724ba675SRob Herring 109724ba675SRob Herring cm1_clockdomains: clockdomains { 110724ba675SRob Herring }; 111724ba675SRob Herring }; 112724ba675SRob Herring }; 113724ba675SRob Herring 114724ba675SRob Herring target-module@8000 { /* 0x4a008000, ap 23 32.0 */ 115724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 116724ba675SRob Herring reg = <0x8000 0x4>; 117724ba675SRob Herring reg-names = "rev"; 118724ba675SRob Herring #address-cells = <1>; 119724ba675SRob Herring #size-cells = <1>; 120724ba675SRob Herring ranges = <0x0 0x8000 0x2000>; 121724ba675SRob Herring 122724ba675SRob Herring cm2: cm2@0 { 123724ba675SRob Herring compatible = "ti,omap4-cm2", "simple-bus"; 124724ba675SRob Herring reg = <0x0 0x2000>; 125724ba675SRob Herring #address-cells = <1>; 126724ba675SRob Herring #size-cells = <1>; 127724ba675SRob Herring ranges = <0 0 0x2000>; 128724ba675SRob Herring 129724ba675SRob Herring cm2_clocks: clocks { 130724ba675SRob Herring #address-cells = <1>; 131724ba675SRob Herring #size-cells = <0>; 132724ba675SRob Herring }; 133724ba675SRob Herring 134724ba675SRob Herring cm2_clockdomains: clockdomains { 135724ba675SRob Herring }; 136724ba675SRob Herring }; 137724ba675SRob Herring }; 138724ba675SRob Herring 139724ba675SRob Herring target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ 140724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 141724ba675SRob Herring reg = <0x56000 0x4>, 142724ba675SRob Herring <0x5602c 0x4>, 143724ba675SRob Herring <0x56028 0x4>; 144724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 145724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 146724ba675SRob Herring SYSC_OMAP2_EMUFREE | 147724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 148724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 149724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 150724ba675SRob Herring <SYSC_IDLE_NO>, 151724ba675SRob Herring <SYSC_IDLE_SMART>; 152724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 153724ba675SRob Herring <SYSC_IDLE_NO>, 154724ba675SRob Herring <SYSC_IDLE_SMART>; 155724ba675SRob Herring ti,syss-mask = <1>; 156724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ 157724ba675SRob Herring clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; 158724ba675SRob Herring clock-names = "fck"; 159724ba675SRob Herring #address-cells = <1>; 160724ba675SRob Herring #size-cells = <1>; 161724ba675SRob Herring ranges = <0x0 0x56000 0x1000>; 162724ba675SRob Herring 163724ba675SRob Herring sdma: dma-controller@0 { 164724ba675SRob Herring compatible = "ti,omap4430-sdma", "ti,omap-sdma"; 165724ba675SRob Herring reg = <0x0 0x1000>; 166724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 167724ba675SRob Herring <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 168724ba675SRob Herring <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 169724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 170724ba675SRob Herring #dma-cells = <1>; 171724ba675SRob Herring dma-channels = <32>; 172724ba675SRob Herring dma-requests = <127>; 173724ba675SRob Herring }; 174724ba675SRob Herring }; 175724ba675SRob Herring 176724ba675SRob Herring target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ 177724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 178724ba675SRob Herring reg = <0x58000 0x4>, 179724ba675SRob Herring <0x58010 0x4>, 180724ba675SRob Herring <0x58014 0x4>; 181724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 182724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 183724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 184724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 185724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 186724ba675SRob Herring <SYSC_IDLE_NO>, 187724ba675SRob Herring <SYSC_IDLE_SMART>, 188724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 189724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 190724ba675SRob Herring <SYSC_IDLE_NO>, 191724ba675SRob Herring <SYSC_IDLE_SMART>, 192724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 193724ba675SRob Herring ti,syss-mask = <1>; 194724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 195724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; 196724ba675SRob Herring clock-names = "fck"; 197724ba675SRob Herring #address-cells = <1>; 198724ba675SRob Herring #size-cells = <1>; 199724ba675SRob Herring ranges = <0x0 0x58000 0x5000>; 200724ba675SRob Herring 201724ba675SRob Herring hsi: hsi@0 { 202724ba675SRob Herring compatible = "ti,omap4-hsi"; 203724ba675SRob Herring reg = <0x0 0x4000>, 204724ba675SRob Herring <0x5000 0x1000>; 205724ba675SRob Herring reg-names = "sys", "gdd"; 206724ba675SRob Herring 207724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; 208724ba675SRob Herring clock-names = "hsi_fck"; 209724ba675SRob Herring 210724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 211724ba675SRob Herring interrupt-names = "gdd_mpu"; 212724ba675SRob Herring 213724ba675SRob Herring #address-cells = <1>; 214724ba675SRob Herring #size-cells = <1>; 215724ba675SRob Herring ranges = <0 0 0x4000>; 216724ba675SRob Herring 217724ba675SRob Herring hsi_port1: hsi-port@2000 { 218724ba675SRob Herring compatible = "ti,omap4-hsi-port"; 219724ba675SRob Herring reg = <0x2000 0x800>, 220724ba675SRob Herring <0x2800 0x800>; 221724ba675SRob Herring reg-names = "tx", "rx"; 222724ba675SRob Herring interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 223724ba675SRob Herring }; 224724ba675SRob Herring 225724ba675SRob Herring hsi_port2: hsi-port@3000 { 226724ba675SRob Herring compatible = "ti,omap4-hsi-port"; 227724ba675SRob Herring reg = <0x3000 0x800>, 228724ba675SRob Herring <0x3800 0x800>; 229724ba675SRob Herring reg-names = "tx", "rx"; 230724ba675SRob Herring interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 231724ba675SRob Herring }; 232724ba675SRob Herring }; 233724ba675SRob Herring }; 234724ba675SRob Herring 235724ba675SRob Herring target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ 236724ba675SRob Herring compatible = "ti,sysc"; 237724ba675SRob Herring status = "disabled"; 238724ba675SRob Herring #address-cells = <1>; 239724ba675SRob Herring #size-cells = <1>; 240724ba675SRob Herring ranges = <0x0 0x5e000 0x2000>; 241724ba675SRob Herring }; 242724ba675SRob Herring 243724ba675SRob Herring target-module@62000 { /* 0x4a062000, ap 11 16.0 */ 244724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 245724ba675SRob Herring reg = <0x62000 0x4>, 246724ba675SRob Herring <0x62010 0x4>, 247724ba675SRob Herring <0x62014 0x4>; 248724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 249724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 250724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 251724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 252724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 253724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 254724ba675SRob Herring <SYSC_IDLE_NO>, 255724ba675SRob Herring <SYSC_IDLE_SMART>; 256724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 257724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; 258724ba675SRob Herring clock-names = "fck"; 259724ba675SRob Herring #address-cells = <1>; 260724ba675SRob Herring #size-cells = <1>; 261724ba675SRob Herring ranges = <0x0 0x62000 0x1000>; 262724ba675SRob Herring 263724ba675SRob Herring usbhstll: usbhstll@0 { 264724ba675SRob Herring compatible = "ti,usbhs-tll"; 265724ba675SRob Herring reg = <0x0 0x1000>; 266724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 267724ba675SRob Herring }; 268724ba675SRob Herring }; 269724ba675SRob Herring 270724ba675SRob Herring target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ 271724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 272724ba675SRob Herring reg = <0x64000 0x4>, 273724ba675SRob Herring <0x64010 0x4>, 274724ba675SRob Herring <0x64014 0x4>; 275724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 276724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 277724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 278724ba675SRob Herring <SYSC_IDLE_NO>, 279724ba675SRob Herring <SYSC_IDLE_SMART>, 280724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 281724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 282724ba675SRob Herring <SYSC_IDLE_NO>, 283724ba675SRob Herring <SYSC_IDLE_SMART>, 284724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 285724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 286724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; 287724ba675SRob Herring clock-names = "fck"; 288724ba675SRob Herring #address-cells = <1>; 289724ba675SRob Herring #size-cells = <1>; 290724ba675SRob Herring ranges = <0x0 0x64000 0x1000>; 291724ba675SRob Herring 292724ba675SRob Herring usbhshost: usbhshost@0 { 293724ba675SRob Herring compatible = "ti,usbhs-host"; 294724ba675SRob Herring reg = <0x0 0x800>; 295724ba675SRob Herring #address-cells = <1>; 296724ba675SRob Herring #size-cells = <1>; 297724ba675SRob Herring ranges = <0 0 0x1000>; 298724ba675SRob Herring clocks = <&init_60m_fclk>, 299724ba675SRob Herring <&xclk60mhsp1_ck>, 300724ba675SRob Herring <&xclk60mhsp2_ck>; 301724ba675SRob Herring clock-names = "refclk_60m_int", 302724ba675SRob Herring "refclk_60m_ext_p1", 303724ba675SRob Herring "refclk_60m_ext_p2"; 304724ba675SRob Herring 305724ba675SRob Herring usbhsohci: ohci@800 { 306724ba675SRob Herring compatible = "ti,ohci-omap3"; 307724ba675SRob Herring reg = <0x800 0x400>; 308724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 309724ba675SRob Herring remote-wakeup-connected; 310724ba675SRob Herring }; 311724ba675SRob Herring 312724ba675SRob Herring usbhsehci: ehci@c00 { 313724ba675SRob Herring compatible = "ti,ehci-omap"; 314724ba675SRob Herring reg = <0xc00 0x400>; 315724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 316724ba675SRob Herring }; 317724ba675SRob Herring }; 318724ba675SRob Herring }; 319724ba675SRob Herring 320724ba675SRob Herring target-module@66000 { /* 0x4a066000, ap 25 26.0 */ 321724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 322724ba675SRob Herring reg = <0x66000 0x4>, 323724ba675SRob Herring <0x66010 0x4>, 324724ba675SRob Herring <0x66014 0x4>; 325724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 326724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 327724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 328724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 329724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 330724ba675SRob Herring <SYSC_IDLE_NO>, 331724ba675SRob Herring <SYSC_IDLE_SMART>; 332724ba675SRob Herring /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ 333724ba675SRob Herring clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; 334724ba675SRob Herring clock-names = "fck"; 335724ba675SRob Herring power-domains = <&prm_tesla>; 336724ba675SRob Herring resets = <&prm_tesla 1>; 337724ba675SRob Herring reset-names = "rstctrl"; 338724ba675SRob Herring #address-cells = <1>; 339724ba675SRob Herring #size-cells = <1>; 340724ba675SRob Herring ranges = <0x0 0x66000 0x1000>; 341724ba675SRob Herring 342724ba675SRob Herring mmu_dsp: mmu@0 { 343724ba675SRob Herring compatible = "ti,omap4-iommu"; 344724ba675SRob Herring reg = <0x0 0x100>; 345724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 346724ba675SRob Herring #iommu-cells = <0>; 347724ba675SRob Herring }; 348724ba675SRob Herring }; 349724ba675SRob Herring }; 350724ba675SRob Herring 351724ba675SRob Herring segment@80000 { /* 0x4a080000 */ 352724ba675SRob Herring compatible = "simple-pm-bus"; 353724ba675SRob Herring #address-cells = <1>; 354724ba675SRob Herring #size-cells = <1>; 355724ba675SRob Herring ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ 356724ba675SRob Herring <0x0005a000 0x000da000 0x001000>, /* ap 14 */ 357724ba675SRob Herring <0x0005b000 0x000db000 0x001000>, /* ap 15 */ 358724ba675SRob Herring <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ 359724ba675SRob Herring <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ 360724ba675SRob Herring <0x0005e000 0x000de000 0x001000>, /* ap 18 */ 361724ba675SRob Herring <0x00060000 0x000e0000 0x001000>, /* ap 19 */ 362724ba675SRob Herring <0x00061000 0x000e1000 0x001000>, /* ap 20 */ 363724ba675SRob Herring <0x00074000 0x000f4000 0x001000>, /* ap 27 */ 364724ba675SRob Herring <0x00075000 0x000f5000 0x001000>, /* ap 28 */ 365724ba675SRob Herring <0x00076000 0x000f6000 0x001000>, /* ap 29 */ 366724ba675SRob Herring <0x00077000 0x000f7000 0x001000>, /* ap 30 */ 367724ba675SRob Herring <0x00036000 0x000b6000 0x001000>, /* ap 69 */ 368724ba675SRob Herring <0x00037000 0x000b7000 0x001000>, /* ap 70 */ 369724ba675SRob Herring <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ 370724ba675SRob Herring <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ 371724ba675SRob Herring <0x00029000 0x000a9000 0x001000>, /* ap 82 */ 372724ba675SRob Herring <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ 373724ba675SRob Herring <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ 374724ba675SRob Herring <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ 375724ba675SRob Herring <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ 376724ba675SRob Herring <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ 377724ba675SRob Herring 378724ba675SRob Herring target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ 379724ba675SRob Herring compatible = "ti,sysc"; 380724ba675SRob Herring status = "disabled"; 381724ba675SRob Herring #address-cells = <1>; 382724ba675SRob Herring #size-cells = <1>; 383724ba675SRob Herring ranges = <0x0 0x29000 0x1000>; 384724ba675SRob Herring }; 385724ba675SRob Herring 386724ba675SRob Herring target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ 387724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 388724ba675SRob Herring reg = <0x2b400 0x4>, 389724ba675SRob Herring <0x2b404 0x4>, 390724ba675SRob Herring <0x2b408 0x4>; 391724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 392724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 393724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 394724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 395724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 396724ba675SRob Herring <SYSC_IDLE_NO>, 397724ba675SRob Herring <SYSC_IDLE_SMART>; 398724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 399724ba675SRob Herring <SYSC_IDLE_NO>, 400724ba675SRob Herring <SYSC_IDLE_SMART>, 401724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 402724ba675SRob Herring ti,syss-mask = <1>; 403724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 404724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; 405724ba675SRob Herring clock-names = "fck"; 406724ba675SRob Herring #address-cells = <1>; 407724ba675SRob Herring #size-cells = <1>; 408724ba675SRob Herring ranges = <0x0 0x2b000 0x1000>; 409724ba675SRob Herring 410724ba675SRob Herring usb_otg_hs: usb_otg_hs@0 { 411724ba675SRob Herring compatible = "ti,omap4-musb"; 412724ba675SRob Herring reg = <0x0 0x7ff>; 413724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 414724ba675SRob Herring interrupt-names = "mc", "dma"; 415724ba675SRob Herring usb-phy = <&usb2_phy>; 416724ba675SRob Herring phys = <&usb2_phy>; 417724ba675SRob Herring phy-names = "usb2-phy"; 418724ba675SRob Herring multipoint = <1>; 419724ba675SRob Herring num-eps = <16>; 420724ba675SRob Herring ram-bits = <12>; 421724ba675SRob Herring ctrl-module = <&omap_control_usbotg>; 422724ba675SRob Herring }; 423724ba675SRob Herring }; 424724ba675SRob Herring 425724ba675SRob Herring target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ 426724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 427724ba675SRob Herring reg = <0x2d000 0x4>, 428724ba675SRob Herring <0x2d010 0x4>, 429724ba675SRob Herring <0x2d014 0x4>; 430724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 431724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 432724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 433724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 434724ba675SRob Herring <SYSC_IDLE_NO>, 435724ba675SRob Herring <SYSC_IDLE_SMART>; 436724ba675SRob Herring ti,syss-mask = <1>; 437724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 438724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; 439724ba675SRob Herring clock-names = "fck"; 440724ba675SRob Herring #address-cells = <1>; 441724ba675SRob Herring #size-cells = <1>; 442724ba675SRob Herring ranges = <0x0 0x2d000 0x1000>; 443724ba675SRob Herring 444724ba675SRob Herring ocp2scp@0 { 445724ba675SRob Herring compatible = "ti,omap-ocp2scp"; 446724ba675SRob Herring reg = <0x0 0x1f>; 447724ba675SRob Herring #address-cells = <1>; 448724ba675SRob Herring #size-cells = <1>; 449724ba675SRob Herring ranges = <0 0 0x1000>; 450724ba675SRob Herring usb2_phy: usb2phy@80 { 451724ba675SRob Herring compatible = "ti,omap-usb2"; 452724ba675SRob Herring reg = <0x80 0x58>; 453724ba675SRob Herring ctrl-module = <&omap_control_usb2phy>; 454724ba675SRob Herring clocks = <&usb_phy_cm_clk32k>; 455724ba675SRob Herring clock-names = "wkupclk"; 456724ba675SRob Herring #phy-cells = <0>; 457724ba675SRob Herring }; 458724ba675SRob Herring }; 459724ba675SRob Herring }; 460724ba675SRob Herring 461724ba675SRob Herring /* d2d mdm */ 462724ba675SRob Herring target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ 463724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 464724ba675SRob Herring reg = <0x36000 0x4>, 465724ba675SRob Herring <0x36010 0x4>, 466724ba675SRob Herring <0x36014 0x4>; 467724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 468724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; 469724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 470724ba675SRob Herring <SYSC_IDLE_NO>, 471724ba675SRob Herring <SYSC_IDLE_SMART>, 472724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 473724ba675SRob Herring ti,syss-mask = <1>; 474724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ 475724ba675SRob Herring clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; 476724ba675SRob Herring clock-names = "fck"; 477724ba675SRob Herring #address-cells = <1>; 478724ba675SRob Herring #size-cells = <1>; 479724ba675SRob Herring ranges = <0x0 0x36000 0x1000>; 480724ba675SRob Herring }; 481724ba675SRob Herring 482724ba675SRob Herring /* d2d mpu */ 483724ba675SRob Herring target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ 484724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 485724ba675SRob Herring reg = <0x4d000 0x4>, 486724ba675SRob Herring <0x4d010 0x4>, 487724ba675SRob Herring <0x4d014 0x4>; 488724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 489724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; 490724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 491724ba675SRob Herring <SYSC_IDLE_NO>, 492724ba675SRob Herring <SYSC_IDLE_SMART>, 493724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 494724ba675SRob Herring ti,syss-mask = <1>; 495724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ 496724ba675SRob Herring clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; 497724ba675SRob Herring clock-names = "fck"; 498724ba675SRob Herring #address-cells = <1>; 499724ba675SRob Herring #size-cells = <1>; 500724ba675SRob Herring ranges = <0x0 0x4d000 0x1000>; 501724ba675SRob Herring }; 502724ba675SRob Herring 503724ba675SRob Herring target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ 504724ba675SRob Herring compatible = "ti,sysc-omap4-sr", "ti,sysc"; 505724ba675SRob Herring reg = <0x59038 0x4>; 506724ba675SRob Herring reg-names = "sysc"; 507724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 508724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 509724ba675SRob Herring <SYSC_IDLE_NO>, 510724ba675SRob Herring <SYSC_IDLE_SMART>, 511724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 512724ba675SRob Herring /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 513724ba675SRob Herring clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; 514724ba675SRob Herring clock-names = "fck"; 515724ba675SRob Herring #address-cells = <1>; 516724ba675SRob Herring #size-cells = <1>; 517724ba675SRob Herring ranges = <0x0 0x59000 0x1000>; 518724ba675SRob Herring 519724ba675SRob Herring smartreflex_mpu: smartreflex@0 { 520724ba675SRob Herring compatible = "ti,omap4-smartreflex-mpu"; 521724ba675SRob Herring reg = <0x0 0x80>; 522724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 523724ba675SRob Herring }; 524724ba675SRob Herring }; 525724ba675SRob Herring 526724ba675SRob Herring target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ 527724ba675SRob Herring compatible = "ti,sysc-omap4-sr", "ti,sysc"; 528724ba675SRob Herring reg = <0x5b038 0x4>; 529724ba675SRob Herring reg-names = "sysc"; 530724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 531724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 532724ba675SRob Herring <SYSC_IDLE_NO>, 533724ba675SRob Herring <SYSC_IDLE_SMART>, 534724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 535724ba675SRob Herring /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 536724ba675SRob Herring clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; 537724ba675SRob Herring clock-names = "fck"; 538724ba675SRob Herring #address-cells = <1>; 539724ba675SRob Herring #size-cells = <1>; 540724ba675SRob Herring ranges = <0x0 0x5b000 0x1000>; 541724ba675SRob Herring 542724ba675SRob Herring smartreflex_iva: smartreflex@0 { 543724ba675SRob Herring compatible = "ti,omap4-smartreflex-iva"; 544724ba675SRob Herring reg = <0x0 0x80>; 545724ba675SRob Herring interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 546724ba675SRob Herring }; 547724ba675SRob Herring }; 548724ba675SRob Herring 549724ba675SRob Herring target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ 550724ba675SRob Herring compatible = "ti,sysc-omap4-sr", "ti,sysc"; 551724ba675SRob Herring reg = <0x5d038 0x4>; 552724ba675SRob Herring reg-names = "sysc"; 553724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 554724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 555724ba675SRob Herring <SYSC_IDLE_NO>, 556724ba675SRob Herring <SYSC_IDLE_SMART>, 557724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 558724ba675SRob Herring /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ 559724ba675SRob Herring clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; 560724ba675SRob Herring clock-names = "fck"; 561724ba675SRob Herring #address-cells = <1>; 562724ba675SRob Herring #size-cells = <1>; 563724ba675SRob Herring ranges = <0x0 0x5d000 0x1000>; 564724ba675SRob Herring 565724ba675SRob Herring smartreflex_core: smartreflex@0 { 566724ba675SRob Herring compatible = "ti,omap4-smartreflex-core"; 567724ba675SRob Herring reg = <0x0 0x80>; 568724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 569724ba675SRob Herring }; 570724ba675SRob Herring }; 571724ba675SRob Herring 572724ba675SRob Herring target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ 573724ba675SRob Herring compatible = "ti,sysc"; 574724ba675SRob Herring status = "disabled"; 575724ba675SRob Herring #address-cells = <1>; 576724ba675SRob Herring #size-cells = <1>; 577724ba675SRob Herring ranges = <0x0 0x60000 0x1000>; 578724ba675SRob Herring }; 579724ba675SRob Herring 580724ba675SRob Herring target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ 581724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 582724ba675SRob Herring reg = <0x74000 0x4>, 583724ba675SRob Herring <0x74010 0x4>; 584724ba675SRob Herring reg-names = "rev", "sysc"; 585724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 586724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 587724ba675SRob Herring <SYSC_IDLE_NO>, 588724ba675SRob Herring <SYSC_IDLE_SMART>; 589724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 590724ba675SRob Herring clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; 591724ba675SRob Herring clock-names = "fck"; 592724ba675SRob Herring #address-cells = <1>; 593724ba675SRob Herring #size-cells = <1>; 594724ba675SRob Herring ranges = <0x0 0x74000 0x1000>; 595724ba675SRob Herring 596724ba675SRob Herring mailbox: mailbox@0 { 597724ba675SRob Herring compatible = "ti,omap4-mailbox"; 598724ba675SRob Herring reg = <0x0 0x200>; 599724ba675SRob Herring interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 600724ba675SRob Herring #mbox-cells = <1>; 601724ba675SRob Herring ti,mbox-num-users = <3>; 602724ba675SRob Herring ti,mbox-num-fifos = <8>; 603724ba675SRob Herring mbox_ipu: mbox-ipu { 604724ba675SRob Herring ti,mbox-tx = <0 0 0>; 605724ba675SRob Herring ti,mbox-rx = <1 0 0>; 606724ba675SRob Herring }; 607724ba675SRob Herring mbox_dsp: mbox-dsp { 608724ba675SRob Herring ti,mbox-tx = <3 0 0>; 609724ba675SRob Herring ti,mbox-rx = <2 0 0>; 610724ba675SRob Herring }; 611724ba675SRob Herring }; 612724ba675SRob Herring }; 613724ba675SRob Herring 614724ba675SRob Herring target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ 615724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 616724ba675SRob Herring reg = <0x76000 0x4>, 617724ba675SRob Herring <0x76010 0x4>, 618724ba675SRob Herring <0x76014 0x4>; 619724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 620724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 621724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 622724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 623724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 624724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 625724ba675SRob Herring <SYSC_IDLE_NO>, 626724ba675SRob Herring <SYSC_IDLE_SMART>; 627724ba675SRob Herring ti,syss-mask = <1>; 628724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 629724ba675SRob Herring clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; 630724ba675SRob Herring clock-names = "fck"; 631724ba675SRob Herring #address-cells = <1>; 632724ba675SRob Herring #size-cells = <1>; 633724ba675SRob Herring ranges = <0x0 0x76000 0x1000>; 634724ba675SRob Herring 635724ba675SRob Herring hwspinlock: spinlock@0 { 636724ba675SRob Herring compatible = "ti,omap4-hwspinlock"; 637724ba675SRob Herring reg = <0x0 0x1000>; 638724ba675SRob Herring #hwlock-cells = <1>; 639724ba675SRob Herring }; 640724ba675SRob Herring }; 641724ba675SRob Herring }; 642724ba675SRob Herring 643724ba675SRob Herring segment@100000 { /* 0x4a100000 */ 644724ba675SRob Herring compatible = "simple-pm-bus"; 645724ba675SRob Herring #address-cells = <1>; 646724ba675SRob Herring #size-cells = <1>; 647724ba675SRob Herring ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ 648724ba675SRob Herring <0x00001000 0x00101000 0x001000>, /* ap 22 */ 649724ba675SRob Herring <0x00002000 0x00102000 0x001000>, /* ap 61 */ 650724ba675SRob Herring <0x00003000 0x00103000 0x001000>, /* ap 62 */ 651724ba675SRob Herring <0x00008000 0x00108000 0x001000>, /* ap 63 */ 652724ba675SRob Herring <0x00009000 0x00109000 0x001000>, /* ap 64 */ 653724ba675SRob Herring <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ 654724ba675SRob Herring <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ 655724ba675SRob Herring 656724ba675SRob Herring target-module@0 { /* 0x4a100000, ap 21 2a.0 */ 657724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 658724ba675SRob Herring reg = <0x0 0x4>, 659724ba675SRob Herring <0x10 0x4>; 660724ba675SRob Herring reg-names = "rev", "sysc"; 661724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 662724ba675SRob Herring <SYSC_IDLE_NO>, 663724ba675SRob Herring <SYSC_IDLE_SMART>, 664724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 665724ba675SRob Herring /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 666724ba675SRob Herring #address-cells = <1>; 667724ba675SRob Herring #size-cells = <1>; 668724ba675SRob Herring ranges = <0x0 0x0 0x1000>; 669724ba675SRob Herring 670724ba675SRob Herring omap4_pmx_core: pinmux@40 { 671724ba675SRob Herring compatible = "ti,omap4-padconf", 672724ba675SRob Herring "pinctrl-single"; 673724ba675SRob Herring reg = <0x40 0x0196>; 674724ba675SRob Herring #address-cells = <1>; 675724ba675SRob Herring #size-cells = <0>; 676724ba675SRob Herring #pinctrl-cells = <1>; 677724ba675SRob Herring #interrupt-cells = <1>; 678724ba675SRob Herring interrupt-controller; 679724ba675SRob Herring pinctrl-single,register-width = <16>; 680724ba675SRob Herring pinctrl-single,function-mask = <0x7fff>; 681724ba675SRob Herring }; 682724ba675SRob Herring 683724ba675SRob Herring omap4_padconf_global: omap4_padconf_global@5a0 { 684724ba675SRob Herring compatible = "syscon", 685724ba675SRob Herring "simple-bus"; 686724ba675SRob Herring reg = <0x5a0 0x170>; 687724ba675SRob Herring #address-cells = <1>; 688724ba675SRob Herring #size-cells = <1>; 689724ba675SRob Herring ranges = <0 0x5a0 0x170>; 690724ba675SRob Herring 691724ba675SRob Herring pbias_regulator: pbias_regulator@60 { 692724ba675SRob Herring compatible = "ti,pbias-omap4", "ti,pbias-omap"; 693724ba675SRob Herring reg = <0x60 0x4>; 694724ba675SRob Herring syscon = <&omap4_padconf_global>; 695724ba675SRob Herring pbias_mmc_reg: pbias_mmc_omap4 { 696724ba675SRob Herring regulator-name = "pbias_mmc_omap4"; 697724ba675SRob Herring regulator-min-microvolt = <1800000>; 698724ba675SRob Herring regulator-max-microvolt = <3000000>; 699724ba675SRob Herring }; 700724ba675SRob Herring }; 701724ba675SRob Herring }; 702724ba675SRob Herring }; 703724ba675SRob Herring 704724ba675SRob Herring target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ 705724ba675SRob Herring compatible = "ti,sysc"; 706724ba675SRob Herring status = "disabled"; 707724ba675SRob Herring #address-cells = <1>; 708724ba675SRob Herring #size-cells = <1>; 709724ba675SRob Herring ranges = <0x0 0x2000 0x1000>; 710724ba675SRob Herring }; 711724ba675SRob Herring 712724ba675SRob Herring target-module@8000 { /* 0x4a108000, ap 63 62.0 */ 713724ba675SRob Herring compatible = "ti,sysc"; 714724ba675SRob Herring status = "disabled"; 715724ba675SRob Herring #address-cells = <1>; 716724ba675SRob Herring #size-cells = <1>; 717724ba675SRob Herring ranges = <0x0 0x8000 0x1000>; 718724ba675SRob Herring }; 719724ba675SRob Herring 720724ba675SRob Herring target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ 721724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 722724ba675SRob Herring reg = <0xa000 0x4>, 723724ba675SRob Herring <0xa010 0x4>; 724724ba675SRob Herring reg-names = "rev", "sysc"; 725724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 726724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 727724ba675SRob Herring <SYSC_IDLE_NO>, 728724ba675SRob Herring <SYSC_IDLE_SMART>; 729724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 730724ba675SRob Herring <SYSC_IDLE_NO>, 731724ba675SRob Herring <SYSC_IDLE_SMART>; 732724ba675SRob Herring ti,sysc-delay-us = <2>; 733724ba675SRob Herring /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ 734724ba675SRob Herring clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; 735724ba675SRob Herring clock-names = "fck"; 736724ba675SRob Herring #address-cells = <1>; 737724ba675SRob Herring #size-cells = <1>; 738724ba675SRob Herring ranges = <0x0 0xa000 0x1000>; 739724ba675SRob Herring 740724ba675SRob Herring /* No child device binding or driver in mainline */ 741724ba675SRob Herring }; 742724ba675SRob Herring }; 743724ba675SRob Herring 744724ba675SRob Herring segment@180000 { /* 0x4a180000 */ 745724ba675SRob Herring compatible = "simple-pm-bus"; 746724ba675SRob Herring #address-cells = <1>; 747724ba675SRob Herring #size-cells = <1>; 748724ba675SRob Herring }; 749724ba675SRob Herring 750724ba675SRob Herring segment@200000 { /* 0x4a200000 */ 751724ba675SRob Herring compatible = "simple-pm-bus"; 752724ba675SRob Herring #address-cells = <1>; 753724ba675SRob Herring #size-cells = <1>; 754724ba675SRob Herring ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ 755724ba675SRob Herring <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ 756724ba675SRob Herring <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ 757724ba675SRob Herring <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ 758724ba675SRob Herring <0x00004000 0x00204000 0x001000>, /* ap 35 */ 759724ba675SRob Herring <0x00005000 0x00205000 0x001000>, /* ap 36 */ 760724ba675SRob Herring <0x00006000 0x00206000 0x001000>, /* ap 37 */ 761724ba675SRob Herring <0x00007000 0x00207000 0x001000>, /* ap 38 */ 762724ba675SRob Herring <0x00012000 0x00212000 0x001000>, /* ap 39 */ 763724ba675SRob Herring <0x00013000 0x00213000 0x001000>, /* ap 40 */ 764724ba675SRob Herring <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ 765724ba675SRob Herring <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ 766724ba675SRob Herring <0x00010000 0x00210000 0x001000>, /* ap 43 */ 767724ba675SRob Herring <0x00011000 0x00211000 0x001000>, /* ap 44 */ 768724ba675SRob Herring <0x00016000 0x00216000 0x001000>, /* ap 45 */ 769724ba675SRob Herring <0x00017000 0x00217000 0x001000>, /* ap 46 */ 770724ba675SRob Herring <0x00014000 0x00214000 0x001000>, /* ap 47 */ 771724ba675SRob Herring <0x00015000 0x00215000 0x001000>, /* ap 48 */ 772724ba675SRob Herring <0x00018000 0x00218000 0x001000>, /* ap 49 */ 773724ba675SRob Herring <0x00019000 0x00219000 0x001000>, /* ap 50 */ 774724ba675SRob Herring <0x00020000 0x00220000 0x001000>, /* ap 51 */ 775724ba675SRob Herring <0x00021000 0x00221000 0x001000>, /* ap 52 */ 776724ba675SRob Herring <0x00026000 0x00226000 0x001000>, /* ap 53 */ 777724ba675SRob Herring <0x00027000 0x00227000 0x001000>, /* ap 54 */ 778724ba675SRob Herring <0x00028000 0x00228000 0x001000>, /* ap 55 */ 779724ba675SRob Herring <0x00029000 0x00229000 0x001000>, /* ap 56 */ 780724ba675SRob Herring <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ 781724ba675SRob Herring <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ 782724ba675SRob Herring <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ 783724ba675SRob Herring <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ 784724ba675SRob Herring 785724ba675SRob Herring target-module@4000 { /* 0x4a204000, ap 35 42.0 */ 786724ba675SRob Herring compatible = "ti,sysc"; 787724ba675SRob Herring status = "disabled"; 788724ba675SRob Herring #address-cells = <1>; 789724ba675SRob Herring #size-cells = <1>; 790724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 791724ba675SRob Herring }; 792724ba675SRob Herring 793724ba675SRob Herring target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ 794724ba675SRob Herring compatible = "ti,sysc"; 795724ba675SRob Herring status = "disabled"; 796724ba675SRob Herring #address-cells = <1>; 797724ba675SRob Herring #size-cells = <1>; 798724ba675SRob Herring ranges = <0x0 0x6000 0x1000>; 799724ba675SRob Herring }; 800724ba675SRob Herring 801724ba675SRob Herring target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ 802724ba675SRob Herring compatible = "ti,sysc"; 803724ba675SRob Herring status = "disabled"; 804724ba675SRob Herring #address-cells = <1>; 805724ba675SRob Herring #size-cells = <1>; 806724ba675SRob Herring ranges = <0x0 0xa000 0x1000>; 807724ba675SRob Herring }; 808724ba675SRob Herring 809724ba675SRob Herring target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ 810724ba675SRob Herring compatible = "ti,sysc"; 811724ba675SRob Herring status = "disabled"; 812724ba675SRob Herring #address-cells = <1>; 813724ba675SRob Herring #size-cells = <1>; 814724ba675SRob Herring ranges = <0x0 0xc000 0x1000>; 815724ba675SRob Herring }; 816724ba675SRob Herring 817724ba675SRob Herring target-module@10000 { /* 0x4a210000, ap 43 52.0 */ 818724ba675SRob Herring compatible = "ti,sysc"; 819724ba675SRob Herring status = "disabled"; 820724ba675SRob Herring #address-cells = <1>; 821724ba675SRob Herring #size-cells = <1>; 822724ba675SRob Herring ranges = <0x0 0x10000 0x1000>; 823724ba675SRob Herring }; 824724ba675SRob Herring 825724ba675SRob Herring target-module@12000 { /* 0x4a212000, ap 39 18.0 */ 826724ba675SRob Herring compatible = "ti,sysc"; 827724ba675SRob Herring status = "disabled"; 828724ba675SRob Herring #address-cells = <1>; 829724ba675SRob Herring #size-cells = <1>; 830724ba675SRob Herring ranges = <0x0 0x12000 0x1000>; 831724ba675SRob Herring }; 832724ba675SRob Herring 833724ba675SRob Herring target-module@14000 { /* 0x4a214000, ap 47 30.0 */ 834724ba675SRob Herring compatible = "ti,sysc"; 835724ba675SRob Herring status = "disabled"; 836724ba675SRob Herring #address-cells = <1>; 837724ba675SRob Herring #size-cells = <1>; 838724ba675SRob Herring ranges = <0x0 0x14000 0x1000>; 839724ba675SRob Herring }; 840724ba675SRob Herring 841724ba675SRob Herring target-module@16000 { /* 0x4a216000, ap 45 28.0 */ 842724ba675SRob Herring compatible = "ti,sysc"; 843724ba675SRob Herring status = "disabled"; 844724ba675SRob Herring #address-cells = <1>; 845724ba675SRob Herring #size-cells = <1>; 846724ba675SRob Herring ranges = <0x0 0x16000 0x1000>; 847724ba675SRob Herring }; 848724ba675SRob Herring 849724ba675SRob Herring target-module@18000 { /* 0x4a218000, ap 49 38.0 */ 850724ba675SRob Herring compatible = "ti,sysc"; 851724ba675SRob Herring status = "disabled"; 852724ba675SRob Herring #address-cells = <1>; 853724ba675SRob Herring #size-cells = <1>; 854724ba675SRob Herring ranges = <0x0 0x18000 0x1000>; 855724ba675SRob Herring }; 856724ba675SRob Herring 857724ba675SRob Herring target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ 858724ba675SRob Herring compatible = "ti,sysc"; 859724ba675SRob Herring status = "disabled"; 860724ba675SRob Herring #address-cells = <1>; 861724ba675SRob Herring #size-cells = <1>; 862724ba675SRob Herring ranges = <0x0 0x1c000 0x1000>; 863724ba675SRob Herring }; 864724ba675SRob Herring 865724ba675SRob Herring target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ 866724ba675SRob Herring compatible = "ti,sysc"; 867724ba675SRob Herring status = "disabled"; 868724ba675SRob Herring #address-cells = <1>; 869724ba675SRob Herring #size-cells = <1>; 870724ba675SRob Herring ranges = <0x0 0x1e000 0x1000>; 871724ba675SRob Herring }; 872724ba675SRob Herring 873724ba675SRob Herring target-module@20000 { /* 0x4a220000, ap 51 40.0 */ 874724ba675SRob Herring compatible = "ti,sysc"; 875724ba675SRob Herring status = "disabled"; 876724ba675SRob Herring #address-cells = <1>; 877724ba675SRob Herring #size-cells = <1>; 878724ba675SRob Herring ranges = <0x0 0x20000 0x1000>; 879724ba675SRob Herring }; 880724ba675SRob Herring 881724ba675SRob Herring target-module@26000 { /* 0x4a226000, ap 53 34.0 */ 882724ba675SRob Herring compatible = "ti,sysc"; 883724ba675SRob Herring status = "disabled"; 884724ba675SRob Herring #address-cells = <1>; 885724ba675SRob Herring #size-cells = <1>; 886724ba675SRob Herring ranges = <0x0 0x26000 0x1000>; 887724ba675SRob Herring }; 888724ba675SRob Herring 889724ba675SRob Herring target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ 890724ba675SRob Herring compatible = "ti,sysc"; 891724ba675SRob Herring status = "disabled"; 892724ba675SRob Herring #address-cells = <1>; 893724ba675SRob Herring #size-cells = <1>; 894724ba675SRob Herring ranges = <0x0 0x28000 0x1000>; 895724ba675SRob Herring }; 896724ba675SRob Herring 897724ba675SRob Herring target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ 898724ba675SRob Herring compatible = "ti,sysc"; 899724ba675SRob Herring status = "disabled"; 900724ba675SRob Herring #address-cells = <1>; 901724ba675SRob Herring #size-cells = <1>; 902724ba675SRob Herring ranges = <0x0 0x2a000 0x1000>; 903724ba675SRob Herring }; 904724ba675SRob Herring }; 905724ba675SRob Herring 906724ba675SRob Herring segment@280000 { /* 0x4a280000 */ 907724ba675SRob Herring compatible = "simple-pm-bus"; 908724ba675SRob Herring #address-cells = <1>; 909724ba675SRob Herring #size-cells = <1>; 910724ba675SRob Herring }; 911724ba675SRob Herring 912724ba675SRob Herring l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ 913724ba675SRob Herring compatible = "simple-pm-bus"; 914724ba675SRob Herring #address-cells = <1>; 915724ba675SRob Herring #size-cells = <1>; 916724ba675SRob Herring ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ 917724ba675SRob Herring <0x00040000 0x00340000 0x001000>, /* ap 68 */ 918724ba675SRob Herring <0x00020000 0x00320000 0x004000>, /* ap 71 */ 919724ba675SRob Herring <0x00024000 0x00324000 0x002000>, /* ap 72 */ 920724ba675SRob Herring <0x00026000 0x00326000 0x001000>, /* ap 73 */ 921724ba675SRob Herring <0x00027000 0x00327000 0x001000>, /* ap 74 */ 922724ba675SRob Herring <0x00028000 0x00328000 0x001000>, /* ap 75 */ 923724ba675SRob Herring <0x00029000 0x00329000 0x001000>, /* ap 76 */ 924724ba675SRob Herring <0x00030000 0x00330000 0x010000>, /* ap 77 */ 925724ba675SRob Herring <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ 926724ba675SRob Herring <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ 927724ba675SRob Herring 928724ba675SRob Herring l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ 929724ba675SRob Herring compatible = "ti,sysc"; 930724ba675SRob Herring status = "disabled"; 931724ba675SRob Herring #address-cells = <1>; 932724ba675SRob Herring #size-cells = <1>; 933724ba675SRob Herring ranges = <0x00000000 0x00000000 0x00020000>, 934724ba675SRob Herring <0x00020000 0x00020000 0x00004000>, 935724ba675SRob Herring <0x00024000 0x00024000 0x00002000>, 936724ba675SRob Herring <0x00026000 0x00026000 0x00001000>, 937724ba675SRob Herring <0x00027000 0x00027000 0x00001000>, 938724ba675SRob Herring <0x00028000 0x00028000 0x00001000>, 939724ba675SRob Herring <0x00029000 0x00029000 0x00001000>, 940724ba675SRob Herring <0x0002a000 0x0002a000 0x00002000>, 941724ba675SRob Herring <0x0002c000 0x0002c000 0x00004000>, 942724ba675SRob Herring <0x00030000 0x00030000 0x00010000>; 943724ba675SRob Herring }; 944724ba675SRob Herring }; 945724ba675SRob Herring}; 946724ba675SRob Herring 947724ba675SRob Herring&l4_wkup { /* 0x4a300000 */ 948724ba675SRob Herring compatible = "ti,omap4-l4-wkup", "simple-pm-bus"; 949724ba675SRob Herring power-domains = <&prm_wkup>; 950724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>; 951724ba675SRob Herring clock-names = "fck"; 952724ba675SRob Herring reg = <0x4a300000 0x800>, 953724ba675SRob Herring <0x4a300800 0x800>, 954724ba675SRob Herring <0x4a301000 0x1000>; 955724ba675SRob Herring reg-names = "ap", "la", "ia0"; 956724ba675SRob Herring #address-cells = <1>; 957724ba675SRob Herring #size-cells = <1>; 958724ba675SRob Herring ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ 959724ba675SRob Herring <0x00010000 0x4a310000 0x010000>, /* segment 1 */ 960724ba675SRob Herring <0x00020000 0x4a320000 0x010000>; /* segment 2 */ 961724ba675SRob Herring 962724ba675SRob Herring segment@0 { /* 0x4a300000 */ 963724ba675SRob Herring compatible = "simple-pm-bus"; 964724ba675SRob Herring #address-cells = <1>; 965724ba675SRob Herring #size-cells = <1>; 966724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 967724ba675SRob Herring <0x00001000 0x00001000 0x001000>, /* ap 1 */ 968724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 2 */ 969724ba675SRob Herring <0x00006000 0x00006000 0x002000>, /* ap 3 */ 970724ba675SRob Herring <0x00008000 0x00008000 0x001000>, /* ap 4 */ 971724ba675SRob Herring <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ 972724ba675SRob Herring <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ 973724ba675SRob Herring <0x00004000 0x00004000 0x001000>, /* ap 17 */ 974724ba675SRob Herring <0x00005000 0x00005000 0x001000>, /* ap 18 */ 975724ba675SRob Herring <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ 976724ba675SRob Herring <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ 977724ba675SRob Herring 978724ba675SRob Herring target-module@4000 { /* 0x4a304000, ap 17 24.0 */ 979724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 980724ba675SRob Herring reg = <0x4000 0x4>, 981724ba675SRob Herring <0x4004 0x4>; 982724ba675SRob Herring reg-names = "rev", "sysc"; 983724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 984724ba675SRob Herring <SYSC_IDLE_NO>; 985724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 986724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; 987724ba675SRob Herring clock-names = "fck"; 988724ba675SRob Herring #address-cells = <1>; 989724ba675SRob Herring #size-cells = <1>; 990724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 991724ba675SRob Herring 992724ba675SRob Herring counter32k: counter@0 { 993724ba675SRob Herring compatible = "ti,omap-counter32k"; 994724ba675SRob Herring reg = <0x0 0x20>; 995724ba675SRob Herring }; 996724ba675SRob Herring }; 997724ba675SRob Herring 998724ba675SRob Herring target-module@6000 { /* 0x4a306000, ap 3 08.0 */ 999724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1000724ba675SRob Herring reg = <0x6000 0x4>; 1001724ba675SRob Herring reg-names = "rev"; 1002724ba675SRob Herring #address-cells = <1>; 1003724ba675SRob Herring #size-cells = <1>; 1004724ba675SRob Herring ranges = <0x0 0x6000 0x2000>; 1005724ba675SRob Herring 1006724ba675SRob Herring prm: prm@0 { 1007724ba675SRob Herring compatible = "ti,omap4-prm", "simple-bus"; 1008724ba675SRob Herring reg = <0x0 0x2000>; 1009724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1010724ba675SRob Herring #address-cells = <1>; 1011724ba675SRob Herring #size-cells = <1>; 1012724ba675SRob Herring ranges = <0 0 0x2000>; 1013724ba675SRob Herring 1014724ba675SRob Herring prm_clocks: clocks { 1015724ba675SRob Herring #address-cells = <1>; 1016724ba675SRob Herring #size-cells = <0>; 1017724ba675SRob Herring }; 1018724ba675SRob Herring 1019724ba675SRob Herring prm_clockdomains: clockdomains { 1020724ba675SRob Herring }; 1021724ba675SRob Herring }; 1022724ba675SRob Herring }; 1023724ba675SRob Herring 1024724ba675SRob Herring target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ 1025724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1026724ba675SRob Herring reg = <0xa000 0x4>; 1027724ba675SRob Herring reg-names = "rev"; 1028724ba675SRob Herring #address-cells = <1>; 1029724ba675SRob Herring #size-cells = <1>; 1030724ba675SRob Herring ranges = <0x0 0xa000 0x1000>; 1031724ba675SRob Herring 1032724ba675SRob Herring scrm: scrm@0 { 1033724ba675SRob Herring compatible = "ti,omap4-scrm"; 1034724ba675SRob Herring reg = <0x0 0x2000>; 1035724ba675SRob Herring 1036724ba675SRob Herring scrm_clocks: clocks { 1037724ba675SRob Herring #address-cells = <1>; 1038724ba675SRob Herring #size-cells = <0>; 1039724ba675SRob Herring }; 1040724ba675SRob Herring 1041724ba675SRob Herring scrm_clockdomains: clockdomains { 1042724ba675SRob Herring }; 1043724ba675SRob Herring }; 1044724ba675SRob Herring }; 1045724ba675SRob Herring 1046724ba675SRob Herring target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ 1047724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1048724ba675SRob Herring reg = <0xc000 0x4>, 1049724ba675SRob Herring <0xc010 0x4>; 1050724ba675SRob Herring reg-names = "rev", "sysc"; 1051724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1052724ba675SRob Herring <SYSC_IDLE_NO>, 1053724ba675SRob Herring <SYSC_IDLE_SMART>, 1054724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1055724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1056724ba675SRob Herring #address-cells = <1>; 1057724ba675SRob Herring #size-cells = <1>; 1058724ba675SRob Herring ranges = <0x0 0xc000 0x1000>; 1059724ba675SRob Herring 1060724ba675SRob Herring omap4_scm_wkup: scm@c000 { 1061724ba675SRob Herring compatible = "ti,omap4-scm-wkup"; 1062724ba675SRob Herring reg = <0xc000 0x1000>; 1063724ba675SRob Herring }; 1064724ba675SRob Herring }; 1065724ba675SRob Herring }; 1066724ba675SRob Herring 1067724ba675SRob Herring segment@10000 { /* 0x4a310000 */ 1068724ba675SRob Herring compatible = "simple-pm-bus"; 1069724ba675SRob Herring #address-cells = <1>; 1070724ba675SRob Herring #size-cells = <1>; 1071724ba675SRob Herring ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 1072724ba675SRob Herring <0x00001000 0x00011000 0x001000>, /* ap 6 */ 1073724ba675SRob Herring <0x00004000 0x00014000 0x001000>, /* ap 7 */ 1074724ba675SRob Herring <0x00005000 0x00015000 0x001000>, /* ap 8 */ 1075724ba675SRob Herring <0x00008000 0x00018000 0x001000>, /* ap 9 */ 1076724ba675SRob Herring <0x00009000 0x00019000 0x001000>, /* ap 10 */ 1077724ba675SRob Herring <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 1078724ba675SRob Herring <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ 1079724ba675SRob Herring <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ 1080724ba675SRob Herring <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ 1081724ba675SRob Herring 1082724ba675SRob Herring gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ 1083724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1084724ba675SRob Herring reg = <0x0 0x4>, 1085724ba675SRob Herring <0x10 0x4>, 1086724ba675SRob Herring <0x114 0x4>; 1087724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1088724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1089724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1090724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1091724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1092724ba675SRob Herring <SYSC_IDLE_NO>, 1093724ba675SRob Herring <SYSC_IDLE_SMART>, 1094724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1095724ba675SRob Herring ti,syss-mask = <1>; 1096724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1097724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, 1098724ba675SRob Herring <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; 1099724ba675SRob Herring clock-names = "fck", "dbclk"; 1100724ba675SRob Herring #address-cells = <1>; 1101724ba675SRob Herring #size-cells = <1>; 1102724ba675SRob Herring ranges = <0x0 0x0 0x1000>; 1103724ba675SRob Herring 1104724ba675SRob Herring gpio1: gpio@0 { 1105724ba675SRob Herring compatible = "ti,omap4-gpio"; 1106724ba675SRob Herring reg = <0x0 0x200>; 1107724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1108724ba675SRob Herring ti,gpio-always-on; 1109724ba675SRob Herring gpio-controller; 1110724ba675SRob Herring #gpio-cells = <2>; 1111724ba675SRob Herring interrupt-controller; 1112724ba675SRob Herring #interrupt-cells = <2>; 1113724ba675SRob Herring }; 1114724ba675SRob Herring }; 1115724ba675SRob Herring 1116724ba675SRob Herring target-module@4000 { /* 0x4a314000, ap 7 18.0 */ 1117724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1118724ba675SRob Herring reg = <0x4000 0x4>, 1119724ba675SRob Herring <0x4010 0x4>, 1120724ba675SRob Herring <0x4014 0x4>; 1121724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1122724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 1123724ba675SRob Herring SYSC_OMAP2_SOFTRESET)>; 1124724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1125724ba675SRob Herring <SYSC_IDLE_NO>, 1126724ba675SRob Herring <SYSC_IDLE_SMART>, 1127724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1128724ba675SRob Herring ti,syss-mask = <1>; 1129724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1130724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; 1131724ba675SRob Herring clock-names = "fck"; 1132724ba675SRob Herring #address-cells = <1>; 1133724ba675SRob Herring #size-cells = <1>; 1134724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 1135724ba675SRob Herring 1136724ba675SRob Herring wdt2: wdt@0 { 1137724ba675SRob Herring compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 1138724ba675SRob Herring reg = <0x0 0x80>; 1139724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1140724ba675SRob Herring }; 1141724ba675SRob Herring }; 1142724ba675SRob Herring 1143724ba675SRob Herring timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ 1144724ba675SRob Herring compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1145724ba675SRob Herring reg = <0x8000 0x4>, 1146724ba675SRob Herring <0x8010 0x4>, 1147724ba675SRob Herring <0x8014 0x4>; 1148724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1149724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1150724ba675SRob Herring SYSC_OMAP2_EMUFREE | 1151724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1152724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1153724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1154724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1155724ba675SRob Herring <SYSC_IDLE_NO>, 1156724ba675SRob Herring <SYSC_IDLE_SMART>; 1157724ba675SRob Herring ti,syss-mask = <1>; 1158724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1159724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; 1160724ba675SRob Herring clock-names = "fck"; 1161724ba675SRob Herring #address-cells = <1>; 1162724ba675SRob Herring #size-cells = <1>; 1163724ba675SRob Herring ranges = <0x0 0x8000 0x1000>; 1164724ba675SRob Herring 1165724ba675SRob Herring timer1: timer@0 { 1166724ba675SRob Herring compatible = "ti,omap3430-timer"; 1167724ba675SRob Herring reg = <0x0 0x80>; 1168724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, 1169724ba675SRob Herring <&sys_clkin_ck>; 1170724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1171724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1172724ba675SRob Herring ti,timer-alwon; 1173724ba675SRob Herring }; 1174724ba675SRob Herring }; 1175724ba675SRob Herring 1176724ba675SRob Herring target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ 1177724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1178724ba675SRob Herring reg = <0xc000 0x4>, 1179724ba675SRob Herring <0xc010 0x4>, 1180724ba675SRob Herring <0xc014 0x4>; 1181724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1182724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1183724ba675SRob Herring SYSC_OMAP2_EMUFREE | 1184724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1185724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1186724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1187724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1188724ba675SRob Herring <SYSC_IDLE_NO>, 1189724ba675SRob Herring <SYSC_IDLE_SMART>; 1190724ba675SRob Herring ti,syss-mask = <1>; 1191724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1192724ba675SRob Herring clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; 1193724ba675SRob Herring clock-names = "fck"; 1194724ba675SRob Herring #address-cells = <1>; 1195724ba675SRob Herring #size-cells = <1>; 1196724ba675SRob Herring ranges = <0x0 0xc000 0x1000>; 1197724ba675SRob Herring 1198724ba675SRob Herring keypad: keypad@0 { 1199724ba675SRob Herring compatible = "ti,omap4-keypad"; 1200724ba675SRob Herring reg = <0x0 0x80>; 1201724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1202724ba675SRob Herring reg-names = "mpu"; 1203724ba675SRob Herring }; 1204724ba675SRob Herring }; 1205724ba675SRob Herring 1206724ba675SRob Herring target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ 1207724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1208724ba675SRob Herring reg = <0xe000 0x4>, 1209724ba675SRob Herring <0xe010 0x4>; 1210724ba675SRob Herring reg-names = "rev", "sysc"; 1211724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1212724ba675SRob Herring <SYSC_IDLE_NO>, 1213724ba675SRob Herring <SYSC_IDLE_SMART>, 1214724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1215724ba675SRob Herring /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ 1216724ba675SRob Herring #address-cells = <1>; 1217724ba675SRob Herring #size-cells = <1>; 1218724ba675SRob Herring ranges = <0x0 0xe000 0x1000>; 1219724ba675SRob Herring 1220724ba675SRob Herring omap4_pmx_wkup: pinmux@40 { 1221724ba675SRob Herring compatible = "ti,omap4-padconf", 1222724ba675SRob Herring "pinctrl-single"; 1223724ba675SRob Herring reg = <0x40 0x0038>; 1224724ba675SRob Herring #address-cells = <1>; 1225724ba675SRob Herring #size-cells = <0>; 1226724ba675SRob Herring #pinctrl-cells = <1>; 1227724ba675SRob Herring #interrupt-cells = <1>; 1228724ba675SRob Herring interrupt-controller; 1229724ba675SRob Herring pinctrl-single,register-width = <16>; 1230724ba675SRob Herring pinctrl-single,function-mask = <0x7fff>; 1231724ba675SRob Herring }; 1232724ba675SRob Herring }; 1233724ba675SRob Herring }; 1234724ba675SRob Herring 1235724ba675SRob Herring segment@20000 { /* 0x4a320000 */ 1236724ba675SRob Herring compatible = "simple-pm-bus"; 1237724ba675SRob Herring #address-cells = <1>; 1238724ba675SRob Herring #size-cells = <1>; 1239724ba675SRob Herring ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 1240724ba675SRob Herring <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 1241724ba675SRob Herring <0x00000000 0x00020000 0x001000>, /* ap 23 */ 1242724ba675SRob Herring <0x00001000 0x00021000 0x001000>, /* ap 24 */ 1243724ba675SRob Herring <0x00002000 0x00022000 0x001000>, /* ap 25 */ 1244724ba675SRob Herring <0x00003000 0x00023000 0x001000>, /* ap 26 */ 1245724ba675SRob Herring <0x00004000 0x00024000 0x001000>, /* ap 27 */ 1246724ba675SRob Herring <0x00005000 0x00025000 0x001000>, /* ap 28 */ 1247724ba675SRob Herring <0x00007000 0x00027000 0x000400>, /* ap 29 */ 1248724ba675SRob Herring <0x00008000 0x00028000 0x000800>, /* ap 30 */ 1249724ba675SRob Herring <0x00009000 0x00029000 0x000400>; /* ap 31 */ 1250724ba675SRob Herring 1251724ba675SRob Herring target-module@0 { /* 0x4a320000, ap 23 04.0 */ 1252724ba675SRob Herring compatible = "ti,sysc"; 1253724ba675SRob Herring status = "disabled"; 1254724ba675SRob Herring #address-cells = <1>; 1255724ba675SRob Herring #size-cells = <1>; 1256724ba675SRob Herring ranges = <0x0 0x0 0x1000>; 1257724ba675SRob Herring }; 1258724ba675SRob Herring 1259724ba675SRob Herring target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ 1260724ba675SRob Herring compatible = "ti,sysc"; 1261724ba675SRob Herring status = "disabled"; 1262724ba675SRob Herring #address-cells = <1>; 1263724ba675SRob Herring #size-cells = <1>; 1264724ba675SRob Herring ranges = <0x0 0x2000 0x1000>; 1265724ba675SRob Herring }; 1266724ba675SRob Herring 1267724ba675SRob Herring target-module@4000 { /* 0x4a324000, ap 27 10.0 */ 1268724ba675SRob Herring compatible = "ti,sysc"; 1269724ba675SRob Herring status = "disabled"; 1270724ba675SRob Herring #address-cells = <1>; 1271724ba675SRob Herring #size-cells = <1>; 1272724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 1273724ba675SRob Herring }; 1274724ba675SRob Herring 1275724ba675SRob Herring target-module@6000 { /* 0x4a326000, ap 13 28.0 */ 1276724ba675SRob Herring compatible = "ti,sysc"; 1277724ba675SRob Herring status = "disabled"; 1278724ba675SRob Herring #address-cells = <1>; 1279724ba675SRob Herring #size-cells = <1>; 1280724ba675SRob Herring ranges = <0x00000000 0x00006000 0x00001000>, 1281724ba675SRob Herring <0x00001000 0x00007000 0x00000400>, 1282724ba675SRob Herring <0x00002000 0x00008000 0x00000800>, 1283724ba675SRob Herring <0x00003000 0x00009000 0x00000400>; 1284724ba675SRob Herring }; 1285724ba675SRob Herring }; 1286724ba675SRob Herring}; 1287724ba675SRob Herring 1288724ba675SRob Herring&l4_per { /* 0x48000000 */ 1289724ba675SRob Herring compatible = "ti,omap4-l4-per", "simple-pm-bus"; 1290724ba675SRob Herring power-domains = <&prm_l4per>; 1291724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>; 1292724ba675SRob Herring clock-names = "fck"; 1293724ba675SRob Herring reg = <0x48000000 0x800>, 1294724ba675SRob Herring <0x48000800 0x800>, 1295724ba675SRob Herring <0x48001000 0x400>, 1296724ba675SRob Herring <0x48001400 0x400>, 1297724ba675SRob Herring <0x48001800 0x400>, 1298724ba675SRob Herring <0x48001c00 0x400>; 1299724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 1300724ba675SRob Herring #address-cells = <1>; 1301724ba675SRob Herring #size-cells = <1>; 1302724ba675SRob Herring ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 1303724ba675SRob Herring <0x00200000 0x48200000 0x200000>; /* segment 1 */ 1304724ba675SRob Herring 1305724ba675SRob Herring segment@0 { /* 0x48000000 */ 1306724ba675SRob Herring compatible = "simple-pm-bus"; 1307724ba675SRob Herring #address-cells = <1>; 1308724ba675SRob Herring #size-cells = <1>; 1309724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1310724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 1 */ 1311724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 2 */ 1312724ba675SRob Herring <0x00020000 0x00020000 0x001000>, /* ap 3 */ 1313724ba675SRob Herring <0x00021000 0x00021000 0x001000>, /* ap 4 */ 1314724ba675SRob Herring <0x00032000 0x00032000 0x001000>, /* ap 5 */ 1315724ba675SRob Herring <0x00033000 0x00033000 0x001000>, /* ap 6 */ 1316724ba675SRob Herring <0x00034000 0x00034000 0x001000>, /* ap 7 */ 1317724ba675SRob Herring <0x00035000 0x00035000 0x001000>, /* ap 8 */ 1318724ba675SRob Herring <0x00036000 0x00036000 0x001000>, /* ap 9 */ 1319724ba675SRob Herring <0x00037000 0x00037000 0x001000>, /* ap 10 */ 1320724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 1321724ba675SRob Herring <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 1322724ba675SRob Herring <0x00040000 0x00040000 0x010000>, /* ap 13 */ 1323724ba675SRob Herring <0x00050000 0x00050000 0x001000>, /* ap 14 */ 1324724ba675SRob Herring <0x00055000 0x00055000 0x001000>, /* ap 15 */ 1325724ba675SRob Herring <0x00056000 0x00056000 0x001000>, /* ap 16 */ 1326724ba675SRob Herring <0x00057000 0x00057000 0x001000>, /* ap 17 */ 1327724ba675SRob Herring <0x00058000 0x00058000 0x001000>, /* ap 18 */ 1328724ba675SRob Herring <0x00059000 0x00059000 0x001000>, /* ap 19 */ 1329724ba675SRob Herring <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ 1330724ba675SRob Herring <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ 1331724ba675SRob Herring <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ 1332724ba675SRob Herring <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ 1333724ba675SRob Herring <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ 1334724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 25 */ 1335724ba675SRob Herring <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ 1336724ba675SRob Herring <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ 1337724ba675SRob Herring <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ 1338724ba675SRob Herring <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ 1339724ba675SRob Herring <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ 1340724ba675SRob Herring <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ 1341724ba675SRob Herring <0x00070000 0x00070000 0x001000>, /* ap 32 */ 1342724ba675SRob Herring <0x00071000 0x00071000 0x001000>, /* ap 33 */ 1343724ba675SRob Herring <0x00072000 0x00072000 0x001000>, /* ap 34 */ 1344724ba675SRob Herring <0x00073000 0x00073000 0x001000>, /* ap 35 */ 1345724ba675SRob Herring <0x00061000 0x00061000 0x001000>, /* ap 36 */ 1346724ba675SRob Herring <0x00096000 0x00096000 0x001000>, /* ap 37 */ 1347724ba675SRob Herring <0x00097000 0x00097000 0x001000>, /* ap 38 */ 1348724ba675SRob Herring <0x00076000 0x00076000 0x001000>, /* ap 39 */ 1349724ba675SRob Herring <0x00077000 0x00077000 0x001000>, /* ap 40 */ 1350724ba675SRob Herring <0x00078000 0x00078000 0x001000>, /* ap 41 */ 1351724ba675SRob Herring <0x00079000 0x00079000 0x001000>, /* ap 42 */ 1352724ba675SRob Herring <0x00086000 0x00086000 0x001000>, /* ap 43 */ 1353724ba675SRob Herring <0x00087000 0x00087000 0x001000>, /* ap 44 */ 1354724ba675SRob Herring <0x00088000 0x00088000 0x001000>, /* ap 45 */ 1355724ba675SRob Herring <0x00089000 0x00089000 0x001000>, /* ap 46 */ 1356724ba675SRob Herring <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ 1357724ba675SRob Herring <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ 1358724ba675SRob Herring <0x00098000 0x00098000 0x001000>, /* ap 49 */ 1359724ba675SRob Herring <0x00099000 0x00099000 0x001000>, /* ap 50 */ 1360724ba675SRob Herring <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ 1361724ba675SRob Herring <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ 1362724ba675SRob Herring <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ 1363724ba675SRob Herring <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ 1364724ba675SRob Herring <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ 1365724ba675SRob Herring <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ 1366724ba675SRob Herring <0x00090000 0x00090000 0x002000>, /* ap 57 */ 1367724ba675SRob Herring <0x00092000 0x00092000 0x001000>, /* ap 58 */ 1368724ba675SRob Herring <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ 1369724ba675SRob Herring <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ 1370724ba675SRob Herring <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ 1371724ba675SRob Herring <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ 1372724ba675SRob Herring <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ 1373724ba675SRob Herring <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ 1374724ba675SRob Herring <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ 1375724ba675SRob Herring <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ 1376724ba675SRob Herring <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ 1377724ba675SRob Herring <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ 1378724ba675SRob Herring <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ 1379724ba675SRob Herring <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ 1380724ba675SRob Herring <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ 1381724ba675SRob Herring <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ 1382724ba675SRob Herring <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ 1383724ba675SRob Herring <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ 1384724ba675SRob Herring <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ 1385724ba675SRob Herring <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ 1386724ba675SRob Herring <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ 1387724ba675SRob Herring <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ 1388724ba675SRob Herring <0x00001400 0x00001400 0x000400>, /* ap 81 */ 1389724ba675SRob Herring <0x00001800 0x00001800 0x000400>, /* ap 82 */ 1390724ba675SRob Herring <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ 1391724ba675SRob Herring <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ 1392724ba675SRob Herring 1393724ba675SRob Herring target-module@20000 { /* 0x48020000, ap 3 06.0 */ 1394724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1395724ba675SRob Herring reg = <0x20050 0x4>, 1396724ba675SRob Herring <0x20054 0x4>, 1397724ba675SRob Herring <0x20058 0x4>; 1398724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1399724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1400724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1401724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1402724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1403724ba675SRob Herring <SYSC_IDLE_NO>, 1404724ba675SRob Herring <SYSC_IDLE_SMART>, 1405724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1406724ba675SRob Herring ti,syss-mask = <1>; 1407724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1408724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; 1409724ba675SRob Herring clock-names = "fck"; 1410724ba675SRob Herring #address-cells = <1>; 1411724ba675SRob Herring #size-cells = <1>; 1412724ba675SRob Herring ranges = <0x0 0x20000 0x1000>; 1413724ba675SRob Herring 1414724ba675SRob Herring uart3: serial@0 { 1415724ba675SRob Herring compatible = "ti,omap4-uart"; 1416724ba675SRob Herring reg = <0x0 0x100>; 1417724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1418724ba675SRob Herring clock-frequency = <48000000>; 1419724ba675SRob Herring }; 1420724ba675SRob Herring }; 1421724ba675SRob Herring 1422724ba675SRob Herring target-module@32000 { /* 0x48032000, ap 5 02.0 */ 1423724ba675SRob Herring compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1424724ba675SRob Herring reg = <0x32000 0x4>, 1425724ba675SRob Herring <0x32010 0x4>, 1426724ba675SRob Herring <0x32014 0x4>; 1427724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1428724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1429724ba675SRob Herring SYSC_OMAP2_EMUFREE | 1430724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1431724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1432724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1433724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1434724ba675SRob Herring <SYSC_IDLE_NO>, 1435724ba675SRob Herring <SYSC_IDLE_SMART>; 1436724ba675SRob Herring ti,syss-mask = <1>; 1437724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1438724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; 1439724ba675SRob Herring clock-names = "fck"; 1440724ba675SRob Herring #address-cells = <1>; 1441724ba675SRob Herring #size-cells = <1>; 1442724ba675SRob Herring ranges = <0x0 0x32000 0x1000>; 1443724ba675SRob Herring 1444724ba675SRob Herring timer2: timer@0 { 1445724ba675SRob Herring compatible = "ti,omap3430-timer"; 1446724ba675SRob Herring reg = <0x0 0x80>; 1447724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, 1448724ba675SRob Herring <&sys_clkin_ck>; 1449724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1450724ba675SRob Herring interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1451724ba675SRob Herring }; 1452724ba675SRob Herring }; 1453724ba675SRob Herring 1454724ba675SRob Herring target-module@34000 { /* 0x48034000, ap 7 04.0 */ 1455724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1456724ba675SRob Herring reg = <0x34000 0x4>, 1457724ba675SRob Herring <0x34010 0x4>; 1458724ba675SRob Herring reg-names = "rev", "sysc"; 1459724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1460724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 1461724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1462724ba675SRob Herring <SYSC_IDLE_NO>, 1463724ba675SRob Herring <SYSC_IDLE_SMART>, 1464724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1465724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1466724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; 1467724ba675SRob Herring clock-names = "fck"; 1468724ba675SRob Herring #address-cells = <1>; 1469724ba675SRob Herring #size-cells = <1>; 1470724ba675SRob Herring ranges = <0x0 0x34000 0x1000>; 1471724ba675SRob Herring 1472724ba675SRob Herring timer3: timer@0 { 1473724ba675SRob Herring compatible = "ti,omap4430-timer"; 1474724ba675SRob Herring reg = <0x0 0x80>; 1475724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, 1476724ba675SRob Herring <&sys_clkin_ck>; 1477724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1478724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1479724ba675SRob Herring }; 1480724ba675SRob Herring }; 1481724ba675SRob Herring 1482724ba675SRob Herring target-module@36000 { /* 0x48036000, ap 9 0e.0 */ 1483724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1484724ba675SRob Herring reg = <0x36000 0x4>, 1485724ba675SRob Herring <0x36010 0x4>; 1486724ba675SRob Herring reg-names = "rev", "sysc"; 1487724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1488724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 1489724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1490724ba675SRob Herring <SYSC_IDLE_NO>, 1491724ba675SRob Herring <SYSC_IDLE_SMART>, 1492724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1493724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1494724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; 1495724ba675SRob Herring clock-names = "fck"; 1496724ba675SRob Herring #address-cells = <1>; 1497724ba675SRob Herring #size-cells = <1>; 1498724ba675SRob Herring ranges = <0x0 0x36000 0x1000>; 1499724ba675SRob Herring 1500724ba675SRob Herring timer4: timer@0 { 1501724ba675SRob Herring compatible = "ti,omap4430-timer"; 1502724ba675SRob Herring reg = <0x0 0x80>; 1503724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, 1504724ba675SRob Herring <&sys_clkin_ck>; 1505724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1506724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1507724ba675SRob Herring }; 1508724ba675SRob Herring }; 1509724ba675SRob Herring 1510724ba675SRob Herring target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ 1511724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1512724ba675SRob Herring reg = <0x3e000 0x4>, 1513724ba675SRob Herring <0x3e010 0x4>; 1514724ba675SRob Herring reg-names = "rev", "sysc"; 1515724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1516724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 1517724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1518724ba675SRob Herring <SYSC_IDLE_NO>, 1519724ba675SRob Herring <SYSC_IDLE_SMART>, 1520724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1521724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1522724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; 1523724ba675SRob Herring clock-names = "fck"; 1524724ba675SRob Herring #address-cells = <1>; 1525724ba675SRob Herring #size-cells = <1>; 1526724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>; 1527724ba675SRob Herring 1528724ba675SRob Herring timer9: timer@0 { 1529724ba675SRob Herring compatible = "ti,omap4430-timer"; 1530724ba675SRob Herring reg = <0x0 0x80>; 1531724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, 1532724ba675SRob Herring <&sys_clkin_ck>; 1533724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1534724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1535724ba675SRob Herring ti,timer-pwm; 1536724ba675SRob Herring }; 1537724ba675SRob Herring }; 1538724ba675SRob Herring 1539724ba675SRob Herring /* Unused DSS L4 access, see L3 instead */ 1540724ba675SRob Herring target-module@40000 { /* 0x48040000, ap 13 0a.0 */ 1541724ba675SRob Herring compatible = "ti,sysc"; 1542724ba675SRob Herring status = "disabled"; 1543724ba675SRob Herring #address-cells = <1>; 1544724ba675SRob Herring #size-cells = <1>; 1545724ba675SRob Herring ranges = <0x0 0x40000 0x10000>; 1546724ba675SRob Herring }; 1547724ba675SRob Herring 1548724ba675SRob Herring target-module@55000 { /* 0x48055000, ap 15 0c.0 */ 1549724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1550724ba675SRob Herring reg = <0x55000 0x4>, 1551724ba675SRob Herring <0x55010 0x4>, 1552724ba675SRob Herring <0x55114 0x4>; 1553724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1554724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1555724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1556724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1557724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1558724ba675SRob Herring <SYSC_IDLE_NO>, 1559724ba675SRob Herring <SYSC_IDLE_SMART>, 1560724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1561724ba675SRob Herring ti,syss-mask = <1>; 1562724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1563724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, 1564724ba675SRob Herring <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; 1565724ba675SRob Herring clock-names = "fck", "dbclk"; 1566724ba675SRob Herring #address-cells = <1>; 1567724ba675SRob Herring #size-cells = <1>; 1568724ba675SRob Herring ranges = <0x0 0x55000 0x1000>; 1569724ba675SRob Herring 1570724ba675SRob Herring gpio2: gpio@0 { 1571724ba675SRob Herring compatible = "ti,omap4-gpio"; 1572724ba675SRob Herring reg = <0x0 0x200>; 1573724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1574724ba675SRob Herring gpio-controller; 1575724ba675SRob Herring #gpio-cells = <2>; 1576724ba675SRob Herring interrupt-controller; 1577724ba675SRob Herring #interrupt-cells = <2>; 1578724ba675SRob Herring }; 1579724ba675SRob Herring }; 1580724ba675SRob Herring 1581724ba675SRob Herring target-module@57000 { /* 0x48057000, ap 17 16.0 */ 1582724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1583724ba675SRob Herring reg = <0x57000 0x4>, 1584724ba675SRob Herring <0x57010 0x4>, 1585724ba675SRob Herring <0x57114 0x4>; 1586724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1587724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1588724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1589724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1590724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1591724ba675SRob Herring <SYSC_IDLE_NO>, 1592724ba675SRob Herring <SYSC_IDLE_SMART>, 1593724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1594724ba675SRob Herring ti,syss-mask = <1>; 1595724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1596724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, 1597724ba675SRob Herring <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; 1598724ba675SRob Herring clock-names = "fck", "dbclk"; 1599724ba675SRob Herring #address-cells = <1>; 1600724ba675SRob Herring #size-cells = <1>; 1601724ba675SRob Herring ranges = <0x0 0x57000 0x1000>; 1602724ba675SRob Herring 1603724ba675SRob Herring gpio3: gpio@0 { 1604724ba675SRob Herring compatible = "ti,omap4-gpio"; 1605724ba675SRob Herring reg = <0x0 0x200>; 1606724ba675SRob Herring interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1607724ba675SRob Herring gpio-controller; 1608724ba675SRob Herring #gpio-cells = <2>; 1609724ba675SRob Herring interrupt-controller; 1610724ba675SRob Herring #interrupt-cells = <2>; 1611724ba675SRob Herring }; 1612724ba675SRob Herring }; 1613724ba675SRob Herring 1614724ba675SRob Herring target-module@59000 { /* 0x48059000, ap 19 10.0 */ 1615724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1616724ba675SRob Herring reg = <0x59000 0x4>, 1617724ba675SRob Herring <0x59010 0x4>, 1618724ba675SRob Herring <0x59114 0x4>; 1619724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1620724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1621724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1622724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1623724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1624724ba675SRob Herring <SYSC_IDLE_NO>, 1625724ba675SRob Herring <SYSC_IDLE_SMART>, 1626724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1627724ba675SRob Herring ti,syss-mask = <1>; 1628724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1629724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, 1630724ba675SRob Herring <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; 1631724ba675SRob Herring clock-names = "fck", "dbclk"; 1632724ba675SRob Herring #address-cells = <1>; 1633724ba675SRob Herring #size-cells = <1>; 1634724ba675SRob Herring ranges = <0x0 0x59000 0x1000>; 1635724ba675SRob Herring 1636724ba675SRob Herring gpio4: gpio@0 { 1637724ba675SRob Herring compatible = "ti,omap4-gpio"; 1638724ba675SRob Herring reg = <0x0 0x200>; 1639724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1640724ba675SRob Herring gpio-controller; 1641724ba675SRob Herring #gpio-cells = <2>; 1642724ba675SRob Herring interrupt-controller; 1643724ba675SRob Herring #interrupt-cells = <2>; 1644724ba675SRob Herring }; 1645724ba675SRob Herring }; 1646724ba675SRob Herring 1647724ba675SRob Herring target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ 1648724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1649724ba675SRob Herring reg = <0x5b000 0x4>, 1650724ba675SRob Herring <0x5b010 0x4>, 1651724ba675SRob Herring <0x5b114 0x4>; 1652724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1653724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1654724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1655724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1656724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1657724ba675SRob Herring <SYSC_IDLE_NO>, 1658724ba675SRob Herring <SYSC_IDLE_SMART>, 1659724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1660724ba675SRob Herring ti,syss-mask = <1>; 1661724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1662724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, 1663724ba675SRob Herring <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; 1664724ba675SRob Herring clock-names = "fck", "dbclk"; 1665724ba675SRob Herring #address-cells = <1>; 1666724ba675SRob Herring #size-cells = <1>; 1667724ba675SRob Herring ranges = <0x0 0x5b000 0x1000>; 1668724ba675SRob Herring 1669724ba675SRob Herring gpio5: gpio@0 { 1670724ba675SRob Herring compatible = "ti,omap4-gpio"; 1671724ba675SRob Herring reg = <0x0 0x200>; 1672724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1673724ba675SRob Herring gpio-controller; 1674724ba675SRob Herring #gpio-cells = <2>; 1675724ba675SRob Herring interrupt-controller; 1676724ba675SRob Herring #interrupt-cells = <2>; 1677724ba675SRob Herring }; 1678724ba675SRob Herring }; 1679724ba675SRob Herring 1680724ba675SRob Herring target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ 1681724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1682724ba675SRob Herring reg = <0x5d000 0x4>, 1683724ba675SRob Herring <0x5d010 0x4>, 1684724ba675SRob Herring <0x5d114 0x4>; 1685724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1686724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1687724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1688724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1689724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1690724ba675SRob Herring <SYSC_IDLE_NO>, 1691724ba675SRob Herring <SYSC_IDLE_SMART>, 1692724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1693724ba675SRob Herring ti,syss-mask = <1>; 1694724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1695724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, 1696724ba675SRob Herring <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; 1697724ba675SRob Herring clock-names = "fck", "dbclk"; 1698724ba675SRob Herring #address-cells = <1>; 1699724ba675SRob Herring #size-cells = <1>; 1700724ba675SRob Herring ranges = <0x0 0x5d000 0x1000>; 1701724ba675SRob Herring 1702724ba675SRob Herring gpio6: gpio@0 { 1703724ba675SRob Herring compatible = "ti,omap4-gpio"; 1704724ba675SRob Herring reg = <0x0 0x200>; 1705724ba675SRob Herring interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1706724ba675SRob Herring gpio-controller; 1707724ba675SRob Herring #gpio-cells = <2>; 1708724ba675SRob Herring interrupt-controller; 1709724ba675SRob Herring #interrupt-cells = <2>; 1710724ba675SRob Herring }; 1711724ba675SRob Herring }; 1712724ba675SRob Herring 1713724ba675SRob Herring target-module@60000 { /* 0x48060000, ap 25 1e.0 */ 1714724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1715724ba675SRob Herring reg = <0x60000 0x8>, 1716724ba675SRob Herring <0x60010 0x8>, 1717724ba675SRob Herring <0x60090 0x8>; 1718724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1719724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1720724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1721724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1722724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1723724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1724724ba675SRob Herring <SYSC_IDLE_NO>, 1725724ba675SRob Herring <SYSC_IDLE_SMART>, 1726724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1727724ba675SRob Herring ti,syss-mask = <1>; 1728724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1729724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; 1730724ba675SRob Herring clock-names = "fck"; 1731724ba675SRob Herring #address-cells = <1>; 1732724ba675SRob Herring #size-cells = <1>; 1733724ba675SRob Herring ranges = <0x0 0x60000 0x1000>; 1734724ba675SRob Herring 1735724ba675SRob Herring i2c3: i2c@0 { 1736724ba675SRob Herring compatible = "ti,omap4-i2c"; 1737724ba675SRob Herring reg = <0x0 0x100>; 1738724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1739724ba675SRob Herring #address-cells = <1>; 1740724ba675SRob Herring #size-cells = <0>; 1741724ba675SRob Herring }; 1742724ba675SRob Herring }; 1743724ba675SRob Herring 1744724ba675SRob Herring target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ 1745724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1746724ba675SRob Herring reg = <0x6a050 0x4>, 1747724ba675SRob Herring <0x6a054 0x4>, 1748724ba675SRob Herring <0x6a058 0x4>; 1749724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1750724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1751724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1752724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1753724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1754724ba675SRob Herring <SYSC_IDLE_NO>, 1755724ba675SRob Herring <SYSC_IDLE_SMART>, 1756724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1757724ba675SRob Herring ti,syss-mask = <1>; 1758724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1759724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; 1760724ba675SRob Herring clock-names = "fck"; 1761724ba675SRob Herring #address-cells = <1>; 1762724ba675SRob Herring #size-cells = <1>; 1763724ba675SRob Herring ranges = <0x0 0x6a000 0x1000>; 1764724ba675SRob Herring 1765724ba675SRob Herring uart1: serial@0 { 1766724ba675SRob Herring compatible = "ti,omap4-uart"; 1767724ba675SRob Herring reg = <0x0 0x100>; 1768724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1769724ba675SRob Herring clock-frequency = <48000000>; 1770724ba675SRob Herring }; 1771724ba675SRob Herring }; 1772724ba675SRob Herring 1773724ba675SRob Herring target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ 1774724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1775724ba675SRob Herring reg = <0x6c050 0x4>, 1776724ba675SRob Herring <0x6c054 0x4>, 1777724ba675SRob Herring <0x6c058 0x4>; 1778724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1779724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1780724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1781724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1782724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1783724ba675SRob Herring <SYSC_IDLE_NO>, 1784724ba675SRob Herring <SYSC_IDLE_SMART>, 1785724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1786724ba675SRob Herring ti,syss-mask = <1>; 1787724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1788724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; 1789724ba675SRob Herring clock-names = "fck"; 1790724ba675SRob Herring #address-cells = <1>; 1791724ba675SRob Herring #size-cells = <1>; 1792724ba675SRob Herring ranges = <0x0 0x6c000 0x1000>; 1793724ba675SRob Herring 1794724ba675SRob Herring uart2: serial@0 { 1795724ba675SRob Herring compatible = "ti,omap4-uart"; 1796724ba675SRob Herring reg = <0x0 0x100>; 1797724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1798724ba675SRob Herring clock-frequency = <48000000>; 1799724ba675SRob Herring }; 1800724ba675SRob Herring }; 1801724ba675SRob Herring 1802724ba675SRob Herring target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ 1803724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1804724ba675SRob Herring reg = <0x6e050 0x4>, 1805724ba675SRob Herring <0x6e054 0x4>, 1806724ba675SRob Herring <0x6e058 0x4>; 1807724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1808724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1809724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1810724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1811724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1812724ba675SRob Herring <SYSC_IDLE_NO>, 1813724ba675SRob Herring <SYSC_IDLE_SMART>, 1814724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1815724ba675SRob Herring ti,syss-mask = <1>; 1816724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1817724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; 1818724ba675SRob Herring clock-names = "fck"; 1819724ba675SRob Herring #address-cells = <1>; 1820724ba675SRob Herring #size-cells = <1>; 1821724ba675SRob Herring ranges = <0x0 0x6e000 0x1000>; 1822724ba675SRob Herring 1823724ba675SRob Herring uart4: serial@0 { 1824724ba675SRob Herring compatible = "ti,omap4-uart"; 1825724ba675SRob Herring reg = <0x0 0x100>; 1826724ba675SRob Herring interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1827724ba675SRob Herring clock-frequency = <48000000>; 1828724ba675SRob Herring }; 1829724ba675SRob Herring }; 1830724ba675SRob Herring 1831724ba675SRob Herring target-module@70000 { /* 0x48070000, ap 32 28.0 */ 1832724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1833724ba675SRob Herring reg = <0x70000 0x8>, 1834724ba675SRob Herring <0x70010 0x8>, 1835724ba675SRob Herring <0x70090 0x8>; 1836724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1837724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1838724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1839724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1840724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1841724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1842724ba675SRob Herring <SYSC_IDLE_NO>, 1843724ba675SRob Herring <SYSC_IDLE_SMART>, 1844724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1845724ba675SRob Herring ti,syss-mask = <1>; 1846724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1847724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; 1848724ba675SRob Herring clock-names = "fck"; 1849724ba675SRob Herring #address-cells = <1>; 1850724ba675SRob Herring #size-cells = <1>; 1851724ba675SRob Herring ranges = <0x0 0x70000 0x1000>; 1852724ba675SRob Herring 1853724ba675SRob Herring i2c1: i2c@0 { 1854724ba675SRob Herring compatible = "ti,omap4-i2c"; 1855724ba675SRob Herring reg = <0x0 0x100>; 1856724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1857724ba675SRob Herring #address-cells = <1>; 1858724ba675SRob Herring #size-cells = <0>; 1859724ba675SRob Herring }; 1860724ba675SRob Herring }; 1861724ba675SRob Herring 1862724ba675SRob Herring target-module@72000 { /* 0x48072000, ap 34 30.0 */ 1863724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1864724ba675SRob Herring reg = <0x72000 0x8>, 1865724ba675SRob Herring <0x72010 0x8>, 1866724ba675SRob Herring <0x72090 0x8>; 1867724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1868724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1869724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1870724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1871724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1872724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1873724ba675SRob Herring <SYSC_IDLE_NO>, 1874724ba675SRob Herring <SYSC_IDLE_SMART>, 1875724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1876724ba675SRob Herring ti,syss-mask = <1>; 1877724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1878724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; 1879724ba675SRob Herring clock-names = "fck"; 1880724ba675SRob Herring #address-cells = <1>; 1881724ba675SRob Herring #size-cells = <1>; 1882724ba675SRob Herring ranges = <0x0 0x72000 0x1000>; 1883724ba675SRob Herring 1884724ba675SRob Herring i2c2: i2c@0 { 1885724ba675SRob Herring compatible = "ti,omap4-i2c"; 1886724ba675SRob Herring reg = <0x0 0x100>; 1887724ba675SRob Herring interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1888724ba675SRob Herring #address-cells = <1>; 1889724ba675SRob Herring #size-cells = <0>; 1890724ba675SRob Herring }; 1891724ba675SRob Herring }; 1892724ba675SRob Herring 1893724ba675SRob Herring target-module@76000 { /* 0x48076000, ap 39 38.0 */ 1894724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1895724ba675SRob Herring reg = <0x76000 0x4>, 1896724ba675SRob Herring <0x76010 0x4>; 1897724ba675SRob Herring reg-names = "rev", "sysc"; 1898724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1899724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1900724ba675SRob Herring <SYSC_IDLE_NO>, 1901724ba675SRob Herring <SYSC_IDLE_SMART>, 1902724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1903724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1904724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; 1905724ba675SRob Herring clock-names = "fck"; 1906724ba675SRob Herring #address-cells = <1>; 1907724ba675SRob Herring #size-cells = <1>; 1908724ba675SRob Herring ranges = <0x0 0x76000 0x1000>; 1909724ba675SRob Herring 1910724ba675SRob Herring /* No child device binding or driver in mainline */ 1911724ba675SRob Herring }; 1912724ba675SRob Herring 1913724ba675SRob Herring target-module@78000 { /* 0x48078000, ap 41 1a.0 */ 1914724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1915724ba675SRob Herring reg = <0x78000 0x4>, 1916724ba675SRob Herring <0x78010 0x4>, 1917724ba675SRob Herring <0x78014 0x4>; 1918724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1919724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1920724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1921724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1922724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1923724ba675SRob Herring <SYSC_IDLE_NO>, 1924724ba675SRob Herring <SYSC_IDLE_SMART>; 1925724ba675SRob Herring ti,syss-mask = <1>; 1926724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1927724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; 1928724ba675SRob Herring clock-names = "fck"; 1929724ba675SRob Herring #address-cells = <1>; 1930724ba675SRob Herring #size-cells = <1>; 1931724ba675SRob Herring ranges = <0x0 0x78000 0x1000>; 1932724ba675SRob Herring 1933724ba675SRob Herring elm: elm@0 { 1934724ba675SRob Herring compatible = "ti,am3352-elm"; 1935724ba675SRob Herring reg = <0x0 0x2000>; 1936724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1937724ba675SRob Herring status = "disabled"; 1938724ba675SRob Herring }; 1939724ba675SRob Herring }; 1940724ba675SRob Herring 1941724ba675SRob Herring target-module@86000 { /* 0x48086000, ap 43 24.0 */ 1942724ba675SRob Herring compatible = "ti,sysc-omap2-timer", "ti,sysc"; 1943724ba675SRob Herring reg = <0x86000 0x4>, 1944724ba675SRob Herring <0x86010 0x4>, 1945724ba675SRob Herring <0x86014 0x4>; 1946724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1947724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1948724ba675SRob Herring SYSC_OMAP2_EMUFREE | 1949724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1950724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1951724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1952724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1953724ba675SRob Herring <SYSC_IDLE_NO>, 1954724ba675SRob Herring <SYSC_IDLE_SMART>; 1955724ba675SRob Herring ti,syss-mask = <1>; 1956724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1957724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; 1958724ba675SRob Herring clock-names = "fck"; 1959724ba675SRob Herring #address-cells = <1>; 1960724ba675SRob Herring #size-cells = <1>; 1961724ba675SRob Herring ranges = <0x0 0x86000 0x1000>; 1962724ba675SRob Herring 1963724ba675SRob Herring timer10: timer@0 { 1964724ba675SRob Herring compatible = "ti,omap3430-timer"; 1965724ba675SRob Herring reg = <0x0 0x80>; 1966724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, 1967724ba675SRob Herring <&sys_clkin_ck>; 1968724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1969724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1970724ba675SRob Herring ti,timer-pwm; 1971724ba675SRob Herring }; 1972724ba675SRob Herring }; 1973724ba675SRob Herring 1974724ba675SRob Herring target-module@88000 { /* 0x48088000, ap 45 2e.0 */ 1975724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1976724ba675SRob Herring reg = <0x88000 0x4>, 1977724ba675SRob Herring <0x88010 0x4>; 1978724ba675SRob Herring reg-names = "rev", "sysc"; 1979724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1980724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 1981724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1982724ba675SRob Herring <SYSC_IDLE_NO>, 1983724ba675SRob Herring <SYSC_IDLE_SMART>, 1984724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1985724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 1986724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; 1987724ba675SRob Herring clock-names = "fck"; 1988724ba675SRob Herring #address-cells = <1>; 1989724ba675SRob Herring #size-cells = <1>; 1990724ba675SRob Herring ranges = <0x0 0x88000 0x1000>; 1991724ba675SRob Herring 1992724ba675SRob Herring timer11: timer@0 { 1993724ba675SRob Herring compatible = "ti,omap4430-timer"; 1994724ba675SRob Herring reg = <0x0 0x80>; 1995724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, 1996724ba675SRob Herring <&sys_clkin_ck>; 1997724ba675SRob Herring clock-names = "fck", "timer_sys_ck"; 1998724ba675SRob Herring interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1999724ba675SRob Herring ti,timer-pwm; 2000724ba675SRob Herring }; 2001724ba675SRob Herring }; 2002724ba675SRob Herring 2003724ba675SRob Herring rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ 2004724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2005724ba675SRob Herring reg = <0x91fe0 0x4>, 2006724ba675SRob Herring <0x91fe4 0x4>; 2007724ba675SRob Herring reg-names = "rev", "sysc"; 2008724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 2009724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2010724ba675SRob Herring <SYSC_IDLE_NO>; 2011724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 2012724ba675SRob Herring clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; 2013724ba675SRob Herring clock-names = "fck"; 2014724ba675SRob Herring #address-cells = <1>; 2015724ba675SRob Herring #size-cells = <1>; 2016724ba675SRob Herring ranges = <0x0 0x90000 0x2000>; 2017724ba675SRob Herring 2018724ba675SRob Herring rng: rng@0 { 2019724ba675SRob Herring compatible = "ti,omap4-rng"; 2020724ba675SRob Herring reg = <0x0 0x2000>; 2021724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2022724ba675SRob Herring }; 2023724ba675SRob Herring }; 2024724ba675SRob Herring 2025724ba675SRob Herring target-module@96000 { /* 0x48096000, ap 37 26.0 */ 2026724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2027724ba675SRob Herring reg = <0x9608c 0x4>; 2028724ba675SRob Herring reg-names = "sysc"; 2029724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2030724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 2031724ba675SRob Herring SYSC_OMAP2_SOFTRESET)>; 2032724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2033724ba675SRob Herring <SYSC_IDLE_NO>, 2034724ba675SRob Herring <SYSC_IDLE_SMART>; 2035724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2036724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; 2037724ba675SRob Herring clock-names = "fck"; 2038724ba675SRob Herring #address-cells = <1>; 2039724ba675SRob Herring #size-cells = <1>; 2040724ba675SRob Herring ranges = <0x0 0x96000 0x1000>; 2041724ba675SRob Herring 2042724ba675SRob Herring mcbsp4: mcbsp@0 { 2043724ba675SRob Herring compatible = "ti,omap4-mcbsp"; 2044724ba675SRob Herring reg = <0x0 0xff>; /* L4 Interconnect */ 2045724ba675SRob Herring reg-names = "mpu"; 2046*cc2d819dSTony Lindgren clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>; 2047*cc2d819dSTony Lindgren clock-names = "fck"; 2048724ba675SRob Herring interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2049724ba675SRob Herring interrupt-names = "common"; 2050724ba675SRob Herring ti,buffer-size = <128>; 2051724ba675SRob Herring dmas = <&sdma 31>, 2052724ba675SRob Herring <&sdma 32>; 2053724ba675SRob Herring dma-names = "tx", "rx"; 2054724ba675SRob Herring status = "disabled"; 2055724ba675SRob Herring }; 2056724ba675SRob Herring }; 2057724ba675SRob Herring 2058724ba675SRob Herring target-module@98000 { /* 0x48098000, ap 49 22.0 */ 2059724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2060724ba675SRob Herring reg = <0x98000 0x4>, 2061724ba675SRob Herring <0x98010 0x4>; 2062724ba675SRob Herring reg-names = "rev", "sysc"; 2063724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2064724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2065724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2066724ba675SRob Herring <SYSC_IDLE_NO>, 2067724ba675SRob Herring <SYSC_IDLE_SMART>, 2068724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2069724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2070724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; 2071724ba675SRob Herring clock-names = "fck"; 2072724ba675SRob Herring #address-cells = <1>; 2073724ba675SRob Herring #size-cells = <1>; 2074724ba675SRob Herring ranges = <0x0 0x98000 0x1000>; 2075724ba675SRob Herring 2076724ba675SRob Herring mcspi1: spi@0 { 2077724ba675SRob Herring compatible = "ti,omap4-mcspi"; 2078724ba675SRob Herring reg = <0x0 0x200>; 2079724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 2080724ba675SRob Herring #address-cells = <1>; 2081724ba675SRob Herring #size-cells = <0>; 2082724ba675SRob Herring ti,spi-num-cs = <4>; 2083724ba675SRob Herring dmas = <&sdma 35>, 2084724ba675SRob Herring <&sdma 36>, 2085724ba675SRob Herring <&sdma 37>, 2086724ba675SRob Herring <&sdma 38>, 2087724ba675SRob Herring <&sdma 39>, 2088724ba675SRob Herring <&sdma 40>, 2089724ba675SRob Herring <&sdma 41>, 2090724ba675SRob Herring <&sdma 42>; 2091724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1", 2092724ba675SRob Herring "tx2", "rx2", "tx3", "rx3"; 2093724ba675SRob Herring }; 2094724ba675SRob Herring }; 2095724ba675SRob Herring 2096724ba675SRob Herring target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ 2097724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2098724ba675SRob Herring reg = <0x9a000 0x4>, 2099724ba675SRob Herring <0x9a010 0x4>; 2100724ba675SRob Herring reg-names = "rev", "sysc"; 2101724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2102724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2103724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2104724ba675SRob Herring <SYSC_IDLE_NO>, 2105724ba675SRob Herring <SYSC_IDLE_SMART>, 2106724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2107724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2108724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; 2109724ba675SRob Herring clock-names = "fck"; 2110724ba675SRob Herring #address-cells = <1>; 2111724ba675SRob Herring #size-cells = <1>; 2112724ba675SRob Herring ranges = <0x0 0x9a000 0x1000>; 2113724ba675SRob Herring 2114724ba675SRob Herring mcspi2: spi@0 { 2115724ba675SRob Herring compatible = "ti,omap4-mcspi"; 2116724ba675SRob Herring reg = <0x0 0x200>; 2117724ba675SRob Herring interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 2118724ba675SRob Herring #address-cells = <1>; 2119724ba675SRob Herring #size-cells = <0>; 2120724ba675SRob Herring ti,spi-num-cs = <2>; 2121724ba675SRob Herring dmas = <&sdma 43>, 2122724ba675SRob Herring <&sdma 44>, 2123724ba675SRob Herring <&sdma 45>, 2124724ba675SRob Herring <&sdma 46>; 2125724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1"; 2126724ba675SRob Herring }; 2127724ba675SRob Herring }; 2128724ba675SRob Herring 2129724ba675SRob Herring target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ 2130724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2131724ba675SRob Herring reg = <0x9c000 0x4>, 2132724ba675SRob Herring <0x9c010 0x4>; 2133724ba675SRob Herring reg-names = "rev", "sysc"; 2134724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2135724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2136724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2137724ba675SRob Herring <SYSC_IDLE_NO>, 2138724ba675SRob Herring <SYSC_IDLE_SMART>, 2139724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2140724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2141724ba675SRob Herring <SYSC_IDLE_NO>, 2142724ba675SRob Herring <SYSC_IDLE_SMART>, 2143724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2144724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 2145724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; 2146724ba675SRob Herring clock-names = "fck"; 2147724ba675SRob Herring #address-cells = <1>; 2148724ba675SRob Herring #size-cells = <1>; 2149724ba675SRob Herring ranges = <0x0 0x9c000 0x1000>; 2150724ba675SRob Herring 2151724ba675SRob Herring mmc1: mmc@0 { 2152724ba675SRob Herring compatible = "ti,omap4-hsmmc"; 2153724ba675SRob Herring reg = <0x0 0x400>; 2154724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2155724ba675SRob Herring ti,dual-volt; 2156724ba675SRob Herring ti,needs-special-reset; 2157724ba675SRob Herring dmas = <&sdma 61>, <&sdma 62>; 2158724ba675SRob Herring dma-names = "tx", "rx"; 2159724ba675SRob Herring pbias-supply = <&pbias_mmc_reg>; 2160724ba675SRob Herring }; 2161724ba675SRob Herring }; 2162724ba675SRob Herring 2163724ba675SRob Herring target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ 2164724ba675SRob Herring compatible = "ti,sysc"; 2165724ba675SRob Herring status = "disabled"; 2166724ba675SRob Herring #address-cells = <1>; 2167724ba675SRob Herring #size-cells = <1>; 2168724ba675SRob Herring ranges = <0x0 0x9e000 0x1000>; 2169724ba675SRob Herring }; 2170724ba675SRob Herring 2171724ba675SRob Herring target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ 2172724ba675SRob Herring compatible = "ti,sysc"; 2173724ba675SRob Herring status = "disabled"; 2174724ba675SRob Herring #address-cells = <1>; 2175724ba675SRob Herring #size-cells = <1>; 2176724ba675SRob Herring ranges = <0x0 0xa2000 0x1000>; 2177724ba675SRob Herring }; 2178724ba675SRob Herring 2179724ba675SRob Herring target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ 2180724ba675SRob Herring compatible = "ti,sysc"; 2181724ba675SRob Herring status = "disabled"; 2182724ba675SRob Herring #address-cells = <1>; 2183724ba675SRob Herring #size-cells = <1>; 2184724ba675SRob Herring ranges = <0x00000000 0x000a4000 0x00001000>, 2185724ba675SRob Herring <0x00001000 0x000a5000 0x00001000>; 2186724ba675SRob Herring }; 2187724ba675SRob Herring 2188724ba675SRob Herring des_target: target-module@a5000 { /* 0x480a5000 */ 2189724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2190724ba675SRob Herring reg = <0xa5030 0x4>, 2191724ba675SRob Herring <0xa5034 0x4>, 2192724ba675SRob Herring <0xa5038 0x4>; 2193724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2194724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2195724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2196724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2197724ba675SRob Herring <SYSC_IDLE_NO>, 2198724ba675SRob Herring <SYSC_IDLE_SMART>, 2199724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2200724ba675SRob Herring ti,syss-mask = <1>; 2201724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 2202724ba675SRob Herring clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>; 2203724ba675SRob Herring clock-names = "fck"; 2204724ba675SRob Herring #address-cells = <1>; 2205724ba675SRob Herring #size-cells = <1>; 2206724ba675SRob Herring ranges = <0 0xa5000 0x00001000>; 2207724ba675SRob Herring 2208724ba675SRob Herring des: des@0 { 2209724ba675SRob Herring compatible = "ti,omap4-des"; 2210724ba675SRob Herring reg = <0 0xa0>; 2211724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2212724ba675SRob Herring dmas = <&sdma 117>, <&sdma 116>; 2213724ba675SRob Herring dma-names = "tx", "rx"; 2214724ba675SRob Herring }; 2215724ba675SRob Herring }; 2216724ba675SRob Herring 2217724ba675SRob Herring target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ 2218724ba675SRob Herring compatible = "ti,sysc"; 2219724ba675SRob Herring status = "disabled"; 2220724ba675SRob Herring #address-cells = <1>; 2221724ba675SRob Herring #size-cells = <1>; 2222724ba675SRob Herring ranges = <0x0 0xa8000 0x4000>; 2223724ba675SRob Herring }; 2224724ba675SRob Herring 2225724ba675SRob Herring target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ 2226724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2227724ba675SRob Herring reg = <0xad000 0x4>, 2228724ba675SRob Herring <0xad010 0x4>; 2229724ba675SRob Herring reg-names = "rev", "sysc"; 2230724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2231724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2232724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2233724ba675SRob Herring <SYSC_IDLE_NO>, 2234724ba675SRob Herring <SYSC_IDLE_SMART>, 2235724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2236724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2237724ba675SRob Herring <SYSC_IDLE_NO>, 2238724ba675SRob Herring <SYSC_IDLE_SMART>, 2239724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2240724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2241724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; 2242724ba675SRob Herring clock-names = "fck"; 2243724ba675SRob Herring #address-cells = <1>; 2244724ba675SRob Herring #size-cells = <1>; 2245724ba675SRob Herring ranges = <0x0 0xad000 0x1000>; 2246724ba675SRob Herring 2247724ba675SRob Herring mmc3: mmc@0 { 2248724ba675SRob Herring compatible = "ti,omap4-hsmmc"; 2249724ba675SRob Herring reg = <0x0 0x400>; 2250724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2251724ba675SRob Herring ti,needs-special-reset; 2252724ba675SRob Herring dmas = <&sdma 77>, <&sdma 78>; 2253724ba675SRob Herring dma-names = "tx", "rx"; 2254724ba675SRob Herring }; 2255724ba675SRob Herring }; 2256724ba675SRob Herring 2257724ba675SRob Herring target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ 2258724ba675SRob Herring compatible = "ti,sysc"; 2259724ba675SRob Herring status = "disabled"; 2260724ba675SRob Herring #address-cells = <1>; 2261724ba675SRob Herring #size-cells = <1>; 2262724ba675SRob Herring ranges = <0x0 0xb0000 0x1000>; 2263724ba675SRob Herring }; 2264724ba675SRob Herring 2265724ba675SRob Herring target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ 2266724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2267724ba675SRob Herring reg = <0xb2000 0x4>, 2268724ba675SRob Herring <0xb2014 0x4>, 2269724ba675SRob Herring <0xb2018 0x4>; 2270724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2271724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2272724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2273724ba675SRob Herring ti,syss-mask = <1>; 2274724ba675SRob Herring ti,no-reset-on-init; 2275724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2276724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; 2277724ba675SRob Herring clock-names = "fck"; 2278724ba675SRob Herring #address-cells = <1>; 2279724ba675SRob Herring #size-cells = <1>; 2280724ba675SRob Herring ranges = <0x0 0xb2000 0x1000>; 2281724ba675SRob Herring 2282724ba675SRob Herring hdqw1w: 1w@0 { 2283724ba675SRob Herring compatible = "ti,omap3-1w"; 2284724ba675SRob Herring reg = <0x0 0x1000>; 2285724ba675SRob Herring interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 2286724ba675SRob Herring }; 2287724ba675SRob Herring }; 2288724ba675SRob Herring 2289724ba675SRob Herring target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ 2290724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2291724ba675SRob Herring reg = <0xb4000 0x4>, 2292724ba675SRob Herring <0xb4010 0x4>; 2293724ba675SRob Herring reg-names = "rev", "sysc"; 2294724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2295724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2296724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2297724ba675SRob Herring <SYSC_IDLE_NO>, 2298724ba675SRob Herring <SYSC_IDLE_SMART>, 2299724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2300724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2301724ba675SRob Herring <SYSC_IDLE_NO>, 2302724ba675SRob Herring <SYSC_IDLE_SMART>, 2303724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2304724ba675SRob Herring /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 2305724ba675SRob Herring clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; 2306724ba675SRob Herring clock-names = "fck"; 2307724ba675SRob Herring #address-cells = <1>; 2308724ba675SRob Herring #size-cells = <1>; 2309724ba675SRob Herring ranges = <0x0 0xb4000 0x1000>; 2310724ba675SRob Herring 2311724ba675SRob Herring mmc2: mmc@0 { 2312724ba675SRob Herring compatible = "ti,omap4-hsmmc"; 2313724ba675SRob Herring reg = <0x0 0x400>; 2314724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2315724ba675SRob Herring ti,needs-special-reset; 2316724ba675SRob Herring dmas = <&sdma 47>, <&sdma 48>; 2317724ba675SRob Herring dma-names = "tx", "rx"; 2318724ba675SRob Herring }; 2319724ba675SRob Herring }; 2320724ba675SRob Herring 2321724ba675SRob Herring target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ 2322724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2323724ba675SRob Herring reg = <0xb8000 0x4>, 2324724ba675SRob Herring <0xb8010 0x4>; 2325724ba675SRob Herring reg-names = "rev", "sysc"; 2326724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2327724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2328724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2329724ba675SRob Herring <SYSC_IDLE_NO>, 2330724ba675SRob Herring <SYSC_IDLE_SMART>, 2331724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2332724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2333724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; 2334724ba675SRob Herring clock-names = "fck"; 2335724ba675SRob Herring #address-cells = <1>; 2336724ba675SRob Herring #size-cells = <1>; 2337724ba675SRob Herring ranges = <0x0 0xb8000 0x1000>; 2338724ba675SRob Herring 2339724ba675SRob Herring mcspi3: spi@0 { 2340724ba675SRob Herring compatible = "ti,omap4-mcspi"; 2341724ba675SRob Herring reg = <0x0 0x200>; 2342724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2343724ba675SRob Herring #address-cells = <1>; 2344724ba675SRob Herring #size-cells = <0>; 2345724ba675SRob Herring ti,spi-num-cs = <2>; 2346724ba675SRob Herring dmas = <&sdma 15>, <&sdma 16>; 2347724ba675SRob Herring dma-names = "tx0", "rx0"; 2348724ba675SRob Herring }; 2349724ba675SRob Herring }; 2350724ba675SRob Herring 2351724ba675SRob Herring target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ 2352724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2353724ba675SRob Herring reg = <0xba000 0x4>, 2354724ba675SRob Herring <0xba010 0x4>; 2355724ba675SRob Herring reg-names = "rev", "sysc"; 2356724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2357724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2358724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2359724ba675SRob Herring <SYSC_IDLE_NO>, 2360724ba675SRob Herring <SYSC_IDLE_SMART>, 2361724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2362724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2363724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; 2364724ba675SRob Herring clock-names = "fck"; 2365724ba675SRob Herring #address-cells = <1>; 2366724ba675SRob Herring #size-cells = <1>; 2367724ba675SRob Herring ranges = <0x0 0xba000 0x1000>; 2368724ba675SRob Herring 2369724ba675SRob Herring mcspi4: spi@0 { 2370724ba675SRob Herring compatible = "ti,omap4-mcspi"; 2371724ba675SRob Herring reg = <0x0 0x200>; 2372724ba675SRob Herring interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2373724ba675SRob Herring #address-cells = <1>; 2374724ba675SRob Herring #size-cells = <0>; 2375724ba675SRob Herring ti,spi-num-cs = <1>; 2376724ba675SRob Herring dmas = <&sdma 70>, <&sdma 71>; 2377724ba675SRob Herring dma-names = "tx0", "rx0"; 2378724ba675SRob Herring }; 2379724ba675SRob Herring }; 2380724ba675SRob Herring 2381724ba675SRob Herring target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ 2382724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2383724ba675SRob Herring reg = <0xd1000 0x4>, 2384724ba675SRob Herring <0xd1010 0x4>; 2385724ba675SRob Herring reg-names = "rev", "sysc"; 2386724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2387724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2388724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2389724ba675SRob Herring <SYSC_IDLE_NO>, 2390724ba675SRob Herring <SYSC_IDLE_SMART>, 2391724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2392724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2393724ba675SRob Herring <SYSC_IDLE_NO>, 2394724ba675SRob Herring <SYSC_IDLE_SMART>, 2395724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2396724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2397724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; 2398724ba675SRob Herring clock-names = "fck"; 2399724ba675SRob Herring #address-cells = <1>; 2400724ba675SRob Herring #size-cells = <1>; 2401724ba675SRob Herring ranges = <0x0 0xd1000 0x1000>; 2402724ba675SRob Herring 2403724ba675SRob Herring mmc4: mmc@0 { 2404724ba675SRob Herring compatible = "ti,omap4-hsmmc"; 2405724ba675SRob Herring reg = <0x0 0x400>; 2406724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2407724ba675SRob Herring ti,needs-special-reset; 2408724ba675SRob Herring dmas = <&sdma 57>, <&sdma 58>; 2409724ba675SRob Herring dma-names = "tx", "rx"; 2410724ba675SRob Herring }; 2411724ba675SRob Herring }; 2412724ba675SRob Herring 2413724ba675SRob Herring target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ 2414724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2415724ba675SRob Herring reg = <0xd5000 0x4>, 2416724ba675SRob Herring <0xd5010 0x4>; 2417724ba675SRob Herring reg-names = "rev", "sysc"; 2418724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2419724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>; 2420724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2421724ba675SRob Herring <SYSC_IDLE_NO>, 2422724ba675SRob Herring <SYSC_IDLE_SMART>, 2423724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2424724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2425724ba675SRob Herring <SYSC_IDLE_NO>, 2426724ba675SRob Herring <SYSC_IDLE_SMART>, 2427724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2428724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2429724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; 2430724ba675SRob Herring clock-names = "fck"; 2431724ba675SRob Herring #address-cells = <1>; 2432724ba675SRob Herring #size-cells = <1>; 2433724ba675SRob Herring ranges = <0x0 0xd5000 0x1000>; 2434724ba675SRob Herring 2435724ba675SRob Herring mmc5: mmc@0 { 2436724ba675SRob Herring compatible = "ti,omap4-hsmmc"; 2437724ba675SRob Herring reg = <0x0 0x400>; 2438724ba675SRob Herring interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2439724ba675SRob Herring ti,needs-special-reset; 2440724ba675SRob Herring dmas = <&sdma 59>, <&sdma 60>; 2441724ba675SRob Herring dma-names = "tx", "rx"; 2442724ba675SRob Herring }; 2443724ba675SRob Herring }; 2444724ba675SRob Herring }; 2445724ba675SRob Herring 2446724ba675SRob Herring segment@200000 { /* 0x48200000 */ 2447724ba675SRob Herring compatible = "simple-pm-bus"; 2448724ba675SRob Herring #address-cells = <1>; 2449724ba675SRob Herring #size-cells = <1>; 2450724ba675SRob Herring ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ 2451724ba675SRob Herring <0x00151000 0x00351000 0x001000>; /* ap 78 */ 2452724ba675SRob Herring 2453724ba675SRob Herring target-module@150000 { /* 0x48350000, ap 77 4c.0 */ 2454724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2455724ba675SRob Herring reg = <0x150000 0x8>, 2456724ba675SRob Herring <0x150010 0x8>, 2457724ba675SRob Herring <0x150090 0x8>; 2458724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 2459724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 2460724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 2461724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 2462724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 2463724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2464724ba675SRob Herring <SYSC_IDLE_NO>, 2465724ba675SRob Herring <SYSC_IDLE_SMART>, 2466724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2467724ba675SRob Herring ti,syss-mask = <1>; 2468724ba675SRob Herring /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ 2469724ba675SRob Herring clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; 2470724ba675SRob Herring clock-names = "fck"; 2471724ba675SRob Herring #address-cells = <1>; 2472724ba675SRob Herring #size-cells = <1>; 2473724ba675SRob Herring ranges = <0x0 0x150000 0x1000>; 2474724ba675SRob Herring 2475724ba675SRob Herring i2c4: i2c@0 { 2476724ba675SRob Herring compatible = "ti,omap4-i2c"; 2477724ba675SRob Herring reg = <0x0 0x100>; 2478724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 2479724ba675SRob Herring #address-cells = <1>; 2480724ba675SRob Herring #size-cells = <0>; 2481724ba675SRob Herring }; 2482724ba675SRob Herring }; 2483724ba675SRob Herring }; 2484724ba675SRob Herring}; 2485724ba675SRob Herring 2486