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/linux/drivers/mtd/nand/raw/
H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,ns2-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
15 const: brcm,ns2-pinmux
24 - $ref: /schemas/pinctrl/pincfg-node.yaml#
25 - $ref: /schemas/pinctrl/pinmux-node.yaml#
67 bias-disable: true
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H A Dnvidia,tegra114-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra114-pinmux
19 - description: pad control registers
20 - description: mux registers
23 "^pinmux(-[a-z0-9-_]+)?$":
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
32 #define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
53 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
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H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/pinctrl/am43xx.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
24 stdout-path = &uart0;
27 evm_v3_3d: fixedregulator-v3_3d {
28 compatible = "regulator-fixed";
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/linux/arch/arm/boot/dts/st/
H A Dspear1310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
63 smi-pmx {
83 nand {
86 st,function = "nand";
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-isiot.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
24 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
35 default-brightness-level = <100>;
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "1P8V";
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H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-galaxys.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include "s5pv210-aries.dtsi"
9 model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210";
11 chassis-type = "handset";
14 stdout-path = &uart2;
17 nand_pwrseq: nand-pwrseq {
18 compatible = "mmc-pwrseq-simple";
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/linux/drivers/clk/imx/
H A Dclk-imx8mn.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2019 NXP.
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <linux/clk-provider.h>
321 struct device *dev = &pdev->dev; in imx8mn_clocks_probe()
322 struct device_node *np = dev->of_node; in imx8mn_clocks_probe()
329 return -ENOMEM; in imx8mn_clocks_probe()
331 clk_hw_data->num = IMX8MN_CLK_END; in imx8mn_clocks_probe()
332 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
342 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); in imx8mn_clocks_probe()
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H A Dclk-imx8mm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <linux/clk-provider.h>
301 struct device *dev = &pdev->dev; in imx8mm_clocks_probe()
302 struct device_node *np = dev->of_node; in imx8mm_clocks_probe()
309 return -ENOMEM; in imx8mm_clocks_probe()
311 clk_hw_data->num = IMX8MM_CLK_END; in imx8mm_clocks_probe()
312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
322 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); in imx8mm_clocks_probe()
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H A Dclk-imx8mq.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <linux/clk-provider.h>
286 struct device *dev = &pdev->dev; in imx8mq_clocks_probe()
287 struct device_node *np = dev->of_node; in imx8mq_clocks_probe()
293 return -ENOMEM; in imx8mq_clocks_probe()
295 clk_hw_data->num = IMX8MQ_CLK_END; in imx8mq_clocks_probe()
296 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
307 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); in imx8mq_clocks_probe()
397 np = dev->of_node; in imx8mq_clocks_probe()
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-mio-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
502 uint64_t nand:1; member
506 uint64_t nand:1;
526 uint64_t nand:1; member
530 uint64_t nand:1;
571 uint64_t nand:1; member
575 uint64_t nand:1;
2795 uint64_t sel:5; member
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/linux/drivers/pinctrl/
H A Dpinctrl-artpec6.c2 * Driver for the Axis ARTPEC-6 pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
294 .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
360 .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
401 { 0, 35, 0x0 }, /* 0x0 - 0x8c */
402 { 36, 52, 0x100 }, /* 0x100 - 0x140 */
403 { 53, 96, 0x180 }, /* 0x180 - 0x22c */
412 return (pin - pin_register[i].start) * 4 + in artpec6_pmx_reg_offset()
457 return -EINVAL; in artpec6_pconf_drive_mA_to_field()
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114-roth.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
15 linux,initrd-start = <0x82000000>;
16 linux,initrd-end = <0x82800000>;
24 trusted-foundations {
25 compatible = "tlm,trusted-foundations";
26 tlm,version-major = <2>;
27 tlm,version-minor = <8>;
40 avdd-dsi-csi-supply = <&vdd_1v2_ap>;
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/linux/drivers/clk/meson/
H A Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-clkc-utils.h"
17 #include "vid-pll-div.h"
19 #include <dt-bindings/clock/gxbb-clkc.h>
646 .index = -1,
713 * b) CCF has a clock hand-off mechanism to make the sure the
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H A Ds4-peripherals.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "vid-pll-div.h"
15 #include "clk-dualdiv.h"
16 #include "meson-clkc-utils.h"
17 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
645 .sel = {
1328 * muxed by a glitch-free switch. The CCF can manage this glitch-free
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H A Dg12a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-clkc-utils.h"
28 #include <dt-bindings/clock/g12a-clkc.h>
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