Lines Matching +full:nand +full:- +full:sel

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2018-2019 NXP.
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <linux/clk-provider.h>
321 	struct device *dev = &pdev->dev;  in imx8mn_clocks_probe()
322 	struct device_node *np = dev->of_node;  in imx8mn_clocks_probe()
329 		return -ENOMEM;  in imx8mn_clocks_probe()
331 	clk_hw_data->num = IMX8MN_CLK_END;  in imx8mn_clocks_probe()
332 	hws = clk_hw_data->hws;  in imx8mn_clocks_probe()
342 	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");  in imx8mn_clocks_probe()
421 	np = dev->of_node;  in imx8mn_clocks_probe()
445 	/* CORE SEL */  in imx8mn_clocks_probe()
466 	 * DRAM clocks are manipulated from TF-A outside clock framework.  in imx8mn_clocks_probe()
482 	hws[IMX8MN_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mn_nand_sels, base + 0xab00);  in imx8mn_clocks_probe()
551 …hws[IMX8MN_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &s…  in imx8mn_clocks_probe()
593 					   hws[IMX8MN_CLK_A53_CORE]->clk,  in imx8mn_clocks_probe()
594 					   hws[IMX8MN_CLK_A53_CORE]->clk,  in imx8mn_clocks_probe()
595 					   hws[IMX8MN_ARM_PLL_OUT]->clk,  in imx8mn_clocks_probe()
596 					   hws[IMX8MN_CLK_A53_DIV]->clk);  in imx8mn_clocks_probe()
617 	{ .compatible = "fsl,imx8mn-ccm" },
625 		.name = "imx8mn-ccm",
636 MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");