Lines Matching +full:nand +full:- +full:sel

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <linux/clk-provider.h>
301 	struct device *dev = &pdev->dev;  in imx8mm_clocks_probe()
302 	struct device_node *np = dev->of_node;  in imx8mm_clocks_probe()
309 		return -ENOMEM;  in imx8mm_clocks_probe()
311 	clk_hw_data->num = IMX8MM_CLK_END;  in imx8mm_clocks_probe()
312 	hws = clk_hw_data->hws;  in imx8mm_clocks_probe()
322 	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");  in imx8mm_clocks_probe()
326 		return -ENOMEM;  in imx8mm_clocks_probe()
400 	np = dev->of_node;  in imx8mm_clocks_probe()
429 	/* CORE SEL */  in imx8mm_clocks_probe()
455 	 * DRAM clocks are manipulated from TF-A outside clock framework.  in imx8mm_clocks_probe()
483 	hws[IMX8MM_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mm_nand_sels, base + 0xab00);  in imx8mm_clocks_probe()
549 …hws[IMX8MM_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &s…  in imx8mm_clocks_probe()
599 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
600 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
601 					   hws[IMX8MM_ARM_PLL_OUT]->clk,  in imx8mm_clocks_probe()
602 					   hws[IMX8MM_CLK_A53_DIV]->clk);  in imx8mm_clocks_probe()
623 	{ .compatible = "fsl,imx8mm-ccm" },
631 		.name = "imx8mm-ccm",
642 MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");