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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_padding.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
27 * struct mtk_padding - Basic information of the Padding
45 return clk_prepare_enable(padding->clk); in mtk_padding_clk_enable()
52 clk_disable_unprepare(padding->clk); in mtk_padding_clk_disable()
60 padding->reg + PADDING_CONTROL_REG); in mtk_padding_start()
67 writel(0, padding->reg + PADDING_PIC_SIZE_REG); in mtk_padding_start()
68 writel(0, padding->reg + PADDING_H_REG); in mtk_padding_start()
69 writel(0, padding->reg + PADDING_V_REG); in mtk_padding_start()
70 writel(0, padding->reg + PADDING_COLOR_REG); in mtk_padding_start()
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H A Dmtk_disp_ccorr.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/soc/mediatek/mtk-cmdq.h>
47 return clk_prepare_enable(ccorr->clk); in mtk_ccorr_clk_enable()
54 clk_disable_unprepare(ccorr->clk); in mtk_ccorr_clk_disable()
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
73 writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); in mtk_ccorr_start()
80 writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); in mtk_ccorr_stop()
92 /* identity value 0x100000000 -> 0x400(mt8183), */ in mtk_ctm_s31_32_to_s1_n()
93 /* identity value 0x100000000 -> 0x800(mt8192), */ in mtk_ctm_s31_32_to_s1_n()
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H A Dmtk_disp_aal.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
40 * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure
57 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
64 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
91 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_get_lut_size()
104 if (!(aal->data && aal->data->has_gamma)) in mtk_aal_gamma_set()
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H A Dmtk_ethdr.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/soc/mediatek/mtk-cmdq.h>
16 #include <linux/soc/mediatek/mtk-mmsys.h>
108 priv->vblank_cb = vblank_cb; in mtk_ethdr_register_vblank_cb()
109 priv->vblank_cb_data = vblank_cb_data; in mtk_ethdr_register_vblank_cb()
116 priv->vblank_cb = NULL; in mtk_ethdr_unregister_vblank_cb()
117 priv->vblank_cb_data = NULL; in mtk_ethdr_unregister_vblank_cb()
124 writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); in mtk_ethdr_enable_vblank()
131 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); in mtk_ethdr_disable_vblank()
138 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA); in mtk_ethdr_irq_handler()
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H A Dmtk_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
29 * struct mtk_crtc - MediaTek specific crtc structure.
97 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_crtc_finish_page_flip()
100 if (mtk_crtc->event) { in mtk_crtc_finish_page_flip()
101 spin_lock_irqsave(&crtc->dev->event_lock, flags); in mtk_crtc_finish_page_flip()
102 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); in mtk_crtc_finish_page_flip()
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H A Dmtk_ddp_comp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/mtk-cmdq.h>
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
76 cmdq_reg->offset + offset, value); in mtk_ddp_write()
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
89 cmdq_reg->offset + offset, value); in mtk_ddp_write_relaxed()
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask()
102 cmdq_reg->offset + offset, value, mask); in mtk_ddp_write_mask()
118 return clk_prepare_enable(priv->clk); in mtk_ddp_clk_enable()
125 clk_disable_unprepare(priv->clk); in mtk_ddp_clk_disable()
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H A Dmtk_disp_ovl.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/soc/mediatek/mtk-cmdq.h>
51 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
52 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
53 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
77 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
79 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
156 * struct mtk_disp_ovl - DISP_OVL driver structure
175 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); in mtk_disp_ovl_irq_handler()
177 if (!priv->vblank_cb) in mtk_disp_ovl_irq_handler()
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/linux/drivers/clk/mediatek/
H A Dclk-mt6735-infracfg.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "clk-gate.h"
10 #include "clk-mtk.h"
12 #include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
13 #include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
30 GATE_MTK(CLK_INFRA_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
90 { .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
99 .name = "clk-mt6735-infracfg",
H A Dclk-mt8516.c1 // SPDX-License-Identifier: GPL-2.0
16 #include "clk-gate.h"
17 #include "clk-mtk.h"
19 #include <dt-bindings/clock/mt8516-clk.h>
583 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
664 { .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc },
665 { .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc },
674 .name = "clk-mt8516",
H A Dclk-mt8167.c1 // SPDX-License-Identifier: GPL-2.0
16 #include "clk-gate.h"
17 #include "clk-mtk.h"
19 #include <dt-bindings/clock/mt8167-clk.h>
792 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
882 { .compatible = "mediatek,mt8167-topckgen", .data = &topck_desc },
883 { .compatible = "mediatek,mt8167-infracfg", .data = &infra_desc },
892 .name = "clk-mt8167",
/linux/drivers/soc/mediatek/
H A Dmtk-mutex.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
31 * are present, hence requiring multiple 32-bits registers.
44 _mutex->data->mutex_mod_reg : \
45 _mutex->data->mutex_mod1_reg; \
705 * So that MUTEX can not only send a STREAM_DONE event to GCE
854 if (!mtx->mutex[i].claimed) { in mtk_mutex_get()
855 mtx->mutex[i].claimed = true; in mtk_mutex_get()
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