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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp26 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
27 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
46 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
47 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
68 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
69 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
88 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
89 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
91 Opc = Mips::MOVE16_MM; in copyPhysReg()
93 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
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H A DMipsInstrInfo.cpp1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
9 // This file contains the Mips implementation of the TargetInstrInfo class.
16 #include "Mips.h"
43 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
58 return MCInstBuilder(Mips::SLL) in getNop()
59 .addReg(Mips::ZERO) in getNop()
60 .addReg(Mips::ZERO) in getNop()
70 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
79 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM; in insertNop()
81 Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL; in insertNop()
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H A DMipsExpandPseudo.cpp16 // spills between ll and sc. These stores cause some MIPS implementations to
21 #include "Mips.h"
30 #define DEBUG_TYPE "mips-pseudo"
48 return "Mips pseudo instruction expansion pass"; in getPassName()
83 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
84 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
85 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
87 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
90 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
91 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
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H A DMips16InstrInfo.cpp40 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
73 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
74 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
75 Opc = Mips::MoveR3216; in copyPhysReg()
76 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
77 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
78 Opc = Mips::Move32R16; in copyPhysReg()
79 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
80 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
81 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
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H A DMipsRegisterInfo.cpp1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
15 #include "Mips.h"
35 #define DEBUG_TYPE "mips-reg-info"
40 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) { in MipsRegisterInfo()
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
56 return &Mips::GPRMM16RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
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H A DMicroMipsSizeReduction.cpp13 #include "Mips.h"
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
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H A DMipsMCInstLower.cpp1 //===- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ----------===//
9 // This file contains code to lower Mips MachineInstrs to their corresponding
38 Mips::Specifier TargetKind = Mips::S_None; in LowerSymbolOperand()
56 TargetKind = Mips::S_GPREL; in LowerSymbolOperand()
59 TargetKind = Mips::S_GOT_CALL; in LowerSymbolOperand()
62 TargetKind = Mips::S_GOT; in LowerSymbolOperand()
65 TargetKind = Mips::S_HI; in LowerSymbolOperand()
68 TargetKind = Mips::S_LO; in LowerSymbolOperand()
71 TargetKind = Mips::S_TLSGD; in LowerSymbolOperand()
74 TargetKind = Mips::S_TLSLDM; in LowerSymbolOperand()
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H A DMipsInstructionSelector.cpp10 /// Mips.
23 #define DEBUG_TYPE "mips-isel"
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
136 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
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H A DMipsSEFrameLowering.cpp48 if (Mips::ACC64RegClass.contains(Src)) in getMFHiLoOpc()
49 return std::make_pair((unsigned)Mips::PseudoMFHI, in getMFHiLoOpc()
50 (unsigned)Mips::PseudoMFLO); in getMFHiLoOpc()
52 if (Mips::ACC64DSPRegClass.contains(Src)) in getMFHiLoOpc()
53 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); in getMFHiLoOpc()
55 if (Mips::ACC128RegClass.contains(Src)) in getMFHiLoOpc()
56 return std::make_pair((unsigned)Mips::PseudoMFHI64, in getMFHiLoOpc()
57 (unsigned)Mips::PseudoMFLO64); in getMFHiLoOpc()
115 case Mips::LOAD_CCOND_DSP: in expandInstr()
118 case Mips::STORE_CCOND_DSP: in expandInstr()
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H A DMips16ISelLowering.cpp24 #define DEBUG_TYPE "mips-lower"
30 "pseudos for Mips 16"),
133 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
177 case Mips::SelBeqZ: in EmitInstrWithCustomInserter()
178 return emitSel16(Mips::BeqzRxImm16, MI, BB); in EmitInstrWithCustomInserter()
179 case Mips::SelBneZ: in EmitInstrWithCustomInserter()
180 return emitSel16(Mips::BnezRxImm16, MI, BB); in EmitInstrWithCustomInserter()
181 case Mips::SelTBteqZCmpi: in EmitInstrWithCustomInserter()
182 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
183 case Mips::SelTBteqZSlti: in EmitInstrWithCustomInserter()
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H A DMipsSERegisterInfo.cpp15 #include "Mips.h"
35 #define DEBUG_TYPE "mips-reg-info"
52 return &Mips::GPR32RegClass; in intRegClass()
55 return &Mips::GPR64RegClass; in intRegClass()
64 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
65 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
67 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
68 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
70 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
71 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
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H A DMipsRegisterBankInfo.cpp9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
26 namespace Mips { namespace
71 } // end namespace Mips
326 if (Bank == &Mips::FPRBRegBank) in setTypesAccordingToPhysicalRegister()
328 else if (Bank == &Mips::GPRBRegBank) in setTypesAccordingToPhysicalRegister()
354 return &Mips::ValueMappings[Mips::MSAIdx]; in getMSAMapping()
358 return Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] in getFprbMapping()
359 : &Mips::ValueMappings[Mips::DPRIdx]; in getFprbMapping()
369 return &Mips::ValueMappings[Mips::GPRIdx]; in getGprbOrCustomMapping()
372 return &Mips::ValueMappings[Mips::DPRIdx]; in getGprbOrCustomMapping()
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaMIPS.cpp1 //===------ SemaMIPS.cpp -------- MIPS target-specific routines -----------===//
9 // This file implements semantic analysis functions specific to MIPS.
35 if (Mips::BI__builtin_mips_addu_qb <= BuiltinID && in CheckMipsBuiltinCpu()
36 BuiltinID <= Mips::BI__builtin_mips_lwx) { in CheckMipsBuiltinCpu()
41 if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID && in CheckMipsBuiltinCpu()
42 BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) { in CheckMipsBuiltinCpu()
48 if (Mips::BI__builtin_msa_add_a_b <= BuiltinID && in CheckMipsBuiltinCpu()
49 BuiltinID <= Mips::BI__builtin_msa_xori_b) { in CheckMipsBuiltinCpu()
70 case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
71 case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
62 #define DEBUG_TYPE "mips-asm-parser"
122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
10 #include "Mips.h"
20 EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
21 cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
25 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
28 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
29 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
70 assert(Options.getABIName().empty() && "Unknown ABI option for MIPS"); in computeTargetABI()
78 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
82 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
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H A DMipsMCCodeEmitter.cpp1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
62 case Mips::fixup_Mips_PC16: in addFixup()
63 case Mips::fixup_Mips_Branch_PCRel: in addFixup()
64 case Mips::fixup_MIPS_PC18_S3: in addFixup()
65 case Mips::fixup_MIPS_PC19_S2: in addFixup()
66 case Mips::fixup_MIPS_PC21_S2: in addFixup()
67 case Mips::fixup_MIPS_PC26_S2: in addFixup()
68 case Mips::fixup_MIPS_PCHI16: in addFixup()
69 case Mips::fixup_MIPS_PCLO16: in addFixup()
70 case Mips::fixup_MICROMIPS_PC7_S1: in addFixup()
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H A DMipsMCTargetDesc.cpp1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
9 // This file provides Mips specific target descriptions.
55 {codeview::RegisterId::MIPS_ZERO, Mips::ZERO}, in initLLVMToCVRegMapping()
56 {codeview::RegisterId::MIPS_AT, Mips::AT}, in initLLVMToCVRegMapping()
57 {codeview::RegisterId::MIPS_V0, Mips::V0}, in initLLVMToCVRegMapping()
58 {codeview::RegisterId::MIPS_V1, Mips::V1}, in initLLVMToCVRegMapping()
59 {codeview::RegisterId::MIPS_A0, Mips::A0}, in initLLVMToCVRegMapping()
60 {codeview::RegisterId::MIPS_A1, Mips::A1}, in initLLVMToCVRegMapping()
61 {codeview::RegisterId::MIPS_A2, Mips::A2}, in initLLVMToCVRegMapping()
62 {codeview::RegisterId::MIPS_A3, Mips::A3}, in initLLVMToCVRegMapping()
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H A DMipsAsmBackend.cpp1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
44 case Mips::fixup_Mips_LO16: in adjustFixupValue()
45 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
46 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
47 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
48 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
49 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
50 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
51 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
52 case Mips::fixup_Mips_CALL_LO16: in adjustFixupValue()
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H A DMipsMCAsmInfo.cpp1 //===-- MipsMCAsmInfo.cpp - Mips Asm Properties ---------------------------===//
64 const MCSpecifierExpr *Mips::createGpOff(const MCExpr *Expr, Mips::Specifier S, in createGpOff()
66 Expr = MCSpecifierExpr::create(Expr, Mips::S_GPREL, Ctx); in createGpOff()
67 Expr = MCSpecifierExpr::create(Expr, Mips::S_NEG, Ctx); in createGpOff()
76 case Mips::S_None: in printImpl()
77 case Mips::S_Special: in printImpl()
78 llvm_unreachable("Mips::S_None and MEK_Special are invalid"); in printImpl()
80 case Mips::S_DTPREL: in printImpl()
81 // Mips::S_DTPREL is used for marking TLS DIEExpr only in printImpl()
85 case Mips::S_CALL_HI16: in printImpl()
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H A DMipsELFObjectWriter.cpp1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
32 #define DEBUG_TYPE "mips-elf-object-writer"
120 /// R_(MIPS|MICROMIPS|MIPS16)_HI16 for all symbols and
121 /// R_(MIPS|MICROMIPS|MIPS16)_GOT16 for local symbols only.
161 case Mips::S_DTPREL: in getRelocType()
162 case Mips::S_DTPREL_HI: in getRelocType()
163 case Mips::S_DTPREL_LO: in getRelocType()
164 case Mips::S_TLSLDM: in getRelocType()
165 case Mips::S_TLSGD: in getRelocType()
166 case Mips::S_GOTTPREL: in getRelocType()
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H A DMipsNaClELFStreamer.cpp1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
9 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
32 #define DEBUG_TYPE "mips-mc-nacl"
36 const unsigned IndirectBranchMaskReg = Mips::T6;
37 const unsigned LoadStoreStackMaskReg = Mips::T7;
58 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
62 return MI.getOperand(0).getReg() == Mips::ZERO; in isIndirectJump()
64 return MI.getOpcode() == Mips::JR; in isIndirectJump()
69 && MI.getOperand(0).getReg() == Mips::SP); in isStackPointerFirstOperand()
81 case Mips::JAL: in isCall()
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H A DMipsInstPrinter.cpp1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
9 // This class prints an Mips MCInst to a .s file.
14 #include "Mips.h"
37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
86 case Mips::RDHWR: in printInst()
87 case Mips::RDHWR64: in printInst()
91 case Mips::Save16: in printInst()
96 case Mips::SaveX16: in printInst()
101 case Mips::Restore16: in printInst()
106 case Mips::RestoreX16: in printInst()
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H A DMipsABIFlagsSection.h1 //===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
29 // The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
67 Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG; in getFlags1Value()
127 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setGPRSizeFromPredicates()
133 CPR1Size = Mips::AFL_REG_NONE; in setCPR1SizeFromPredicates()
135 CPR1Size = Mips::AFL_REG_128; in setCPR1SizeFromPredicates()
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/freebsd/contrib/file/magic/Magdir/
H A Dmips3 # $File: mips,v 1.15 2024/09/01 13:49:15 christos Exp $
4 # mips: file(1) magic for MIPS ECOFF and Ucode, as used in SGI IRIX
7 0 name display-mips-ecoff
16 # MIPS 1
20 >>0 use \^display-mips-ecoff
26 >>0 use \^display-mips-ecoff
30 >>0 use display-mips-ecoff
36 >>0 use display-mips-ecoff
38 # MIPS 2 additions
41 >16 beshort 56 MIPSEB MIPS-II ECOFF executable
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
9 // This file is part of the Mips Disassembler.
33 #define DEBUG_TYPE "mips-disassembler"
46 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)), in MipsDisassembler()
49 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); } in hasMips2()
50 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); } in hasMips3()
51 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); } in hasMips32()
54 return STI.hasFeature(Mips::FeatureMips32r6); in hasMips32r6()
57 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); } in isFP64()
59 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); } in isGP64()
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