Lines Matching full:mips
1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
63 #define DEBUG_TYPE "mips-asm-parser"
123 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
124 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
125 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
126 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
127 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
128 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
129 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
130 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
131 Mips::FeatureNaN2008
577 return getSTI().hasFeature(Mips::FeatureGP64Bit); in isGP64bit()
581 return getSTI().hasFeature(Mips::FeatureFP64Bit); in isFP64bit()
602 return getSTI().hasFeature(Mips::FeatureFPXX); in isABI_FPXX()
606 return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg)); in useOddSPReg()
610 return getSTI().hasFeature(Mips::FeatureMicroMips); in inMicroMipsMode()
614 return getSTI().hasFeature(Mips::FeatureMips1); in hasMips1()
618 return getSTI().hasFeature(Mips::FeatureMips2); in hasMips2()
622 return getSTI().hasFeature(Mips::FeatureMips3); in hasMips3()
626 return getSTI().hasFeature(Mips::FeatureMips4); in hasMips4()
630 return getSTI().hasFeature(Mips::FeatureMips5); in hasMips5()
634 return getSTI().hasFeature(Mips::FeatureMips32); in hasMips32()
638 return getSTI().hasFeature(Mips::FeatureMips64); in hasMips64()
642 return getSTI().hasFeature(Mips::FeatureMips32r2); in hasMips32r2()
646 return getSTI().hasFeature(Mips::FeatureMips64r2); in hasMips64r2()
650 return (getSTI().hasFeature(Mips::FeatureMips32r3)); in hasMips32r3()
654 return (getSTI().hasFeature(Mips::FeatureMips64r3)); in hasMips64r3()
658 return (getSTI().hasFeature(Mips::FeatureMips32r5)); in hasMips32r5()
662 return (getSTI().hasFeature(Mips::FeatureMips64r5)); in hasMips64r5()
666 return getSTI().hasFeature(Mips::FeatureMips32r6); in hasMips32r6()
670 return getSTI().hasFeature(Mips::FeatureMips64r6); in hasMips64r6()
674 return getSTI().hasFeature(Mips::FeatureDSP); in hasDSP()
678 return getSTI().hasFeature(Mips::FeatureDSPR2); in hasDSPR2()
682 return getSTI().hasFeature(Mips::FeatureDSPR3); in hasDSPR3()
686 return getSTI().hasFeature(Mips::FeatureMSA); in hasMSA()
690 return (getSTI().hasFeature(Mips::FeatureCnMips)); in hasCnMips()
694 return (getSTI().hasFeature(Mips::FeatureCnMipsP)); in hasCnMipsP()
702 return getSTI().hasFeature(Mips::FeatureMips16); in inMips16Mode()
706 return getSTI().hasFeature(Mips::FeatureUseTCCInDIV); in useTraps()
710 return getSTI().hasFeature(Mips::FeatureSoftFloat); in useSoftFloat()
713 return getSTI().hasFeature(Mips::FeatureMT); in hasMT()
717 return getSTI().hasFeature(Mips::FeatureCRC); in hasCRC()
721 return getSTI().hasFeature(Mips::FeatureVirt); in hasVirt()
725 return getSTI().hasFeature(Mips::FeatureGINV); in hasGINV()
807 /// MipsOperand - Instances of this class represent a parsed Mips machine
922 unsigned ClassID = Mips::GPR32RegClassID; in getGPR32Reg()
930 unsigned ClassID = Mips::GPR32RegClassID; in getGPRMM16Reg()
938 unsigned ClassID = Mips::GPR64RegClassID; in getGPR64Reg()
949 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) in getAFGR64Reg()
957 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) in getFGR64Reg()
965 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) in getFGR32Reg()
973 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) in getFCCReg()
983 unsigned ClassID = Mips::MSA128BRegClassID; in getMSA128Reg()
991 unsigned ClassID = Mips::MSACtrlRegClassID; in getMSACtrlReg()
999 unsigned ClassID = Mips::COP0RegClassID; in getCOP0Reg()
1007 unsigned ClassID = Mips::COP2RegClassID; in getCOP2Reg()
1015 unsigned ClassID = Mips::COP3RegClassID; in getCOP3Reg()
1023 unsigned ClassID = Mips::ACC64DSPRegClassID; in getACC64DSPReg()
1031 unsigned ClassID = Mips::HI32DSPRegClassID; in getHI32DSPReg()
1039 unsigned ClassID = Mips::LO32DSPRegClassID; in getLO32DSPReg()
1047 unsigned ClassID = Mips::CCRRegClassID; in getCCRReg()
1055 unsigned ClassID = Mips::HWRegsRegClassID; in getHWRegsReg()
1385 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmOffsetSP()
1391 && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmWordAlignedOffsetSP()
1397 && (getMemBase()->getGPR32Reg() == Mips::GP); in isMemWithSimmWordAlignedOffsetGP()
1430 if (!((R0 == Mips::S0 && R1 == Mips::RA) || in isRegList16()
1431 (R0 == Mips::S0_64 && R1 == Mips::RA_64))) in isRegList16()
1762 case Mips::BEQ_MM: in hasShortDelaySlot()
1763 case Mips::BNE_MM: in hasShortDelaySlot()
1764 case Mips::BLTZ_MM: in hasShortDelaySlot()
1765 case Mips::BGEZ_MM: in hasShortDelaySlot()
1766 case Mips::BLEZ_MM: in hasShortDelaySlot()
1767 case Mips::BGTZ_MM: in hasShortDelaySlot()
1768 case Mips::JRC16_MM: in hasShortDelaySlot()
1769 case Mips::JALS_MM: in hasShortDelaySlot()
1770 case Mips::JALRS_MM: in hasShortDelaySlot()
1771 case Mips::JALRS16_MM: in hasShortDelaySlot()
1772 case Mips::BGEZALS_MM: in hasShortDelaySlot()
1773 case Mips::BLTZALS_MM: in hasShortDelaySlot()
1775 case Mips::J_MM: in hasShortDelaySlot()
1888 case Mips::BBIT0: in processInstruction()
1889 case Mips::BBIT032: in processInstruction()
1890 case Mips::BBIT1: in processInstruction()
1891 case Mips::BBIT132: in processInstruction()
1895 case Mips::BEQ: in processInstruction()
1896 case Mips::BNE: in processInstruction()
1897 case Mips::BEQ_MM: in processInstruction()
1898 case Mips::BNE_MM: in processInstruction()
1909 case Mips::BGEZ: in processInstruction()
1910 case Mips::BGTZ: in processInstruction()
1911 case Mips::BLEZ: in processInstruction()
1912 case Mips::BLTZ: in processInstruction()
1913 case Mips::BGEZAL: in processInstruction()
1914 case Mips::BLTZAL: in processInstruction()
1915 case Mips::BC1F: in processInstruction()
1916 case Mips::BC1T: in processInstruction()
1917 case Mips::BGEZ_MM: in processInstruction()
1918 case Mips::BGTZ_MM: in processInstruction()
1919 case Mips::BLEZ_MM: in processInstruction()
1920 case Mips::BLTZ_MM: in processInstruction()
1921 case Mips::BGEZAL_MM: in processInstruction()
1922 case Mips::BLTZAL_MM: in processInstruction()
1923 case Mips::BC1F_MM: in processInstruction()
1924 case Mips::BC1T_MM: in processInstruction()
1925 case Mips::BC1EQZC_MMR6: in processInstruction()
1926 case Mips::BC1NEZC_MMR6: in processInstruction()
1927 case Mips::BC2EQZC_MMR6: in processInstruction()
1928 case Mips::BC2NEZC_MMR6: in processInstruction()
1939 case Mips::BGEC: case Mips::BGEC_MMR6: in processInstruction()
1940 case Mips::BLTC: case Mips::BLTC_MMR6: in processInstruction()
1941 case Mips::BGEUC: case Mips::BGEUC_MMR6: in processInstruction()
1942 case Mips::BLTUC: case Mips::BLTUC_MMR6: in processInstruction()
1943 case Mips::BEQC: case Mips::BEQC_MMR6: in processInstruction()
1944 case Mips::BNEC: case Mips::BNEC_MMR6: in processInstruction()
1954 case Mips::BLEZC: case Mips::BLEZC_MMR6: in processInstruction()
1955 case Mips::BGEZC: case Mips::BGEZC_MMR6: in processInstruction()
1956 case Mips::BGTZC: case Mips::BGTZC_MMR6: in processInstruction()
1957 case Mips::BLTZC: case Mips::BLTZC_MMR6: in processInstruction()
1967 case Mips::BEQZC: case Mips::BEQZC_MMR6: in processInstruction()
1968 case Mips::BNEZC: case Mips::BNEZC_MMR6: in processInstruction()
1978 case Mips::BEQZ16_MM: in processInstruction()
1979 case Mips::BEQZC16_MMR6: in processInstruction()
1980 case Mips::BNEZ16_MM: in processInstruction()
1981 case Mips::BNEZC16_MMR6: in processInstruction()
1996 if (hasMips32r6() && Opcode == Mips::SSNOP) { in processInstruction()
2010 case Mips::BBIT0: in processInstruction()
2011 case Mips::BBIT032: in processInstruction()
2012 case Mips::BBIT1: in processInstruction()
2013 case Mips::BBIT132: in processInstruction()
2020 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 || in processInstruction()
2021 Opcode == Mips::BBIT1 ? 63 : 31)) in processInstruction()
2024 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032 in processInstruction()
2025 : Mips::BBIT132); in processInstruction()
2030 case Mips::SEQi: in processInstruction()
2031 case Mips::SNEi: in processInstruction()
2046 // The MIPS backend models most of the divison instructions and macros as in processInstruction()
2055 case Mips::SDivIMacro: in processInstruction()
2056 case Mips::UDivIMacro: in processInstruction()
2057 case Mips::DSDivIMacro: in processInstruction()
2058 case Mips::DUDivIMacro: in processInstruction()
2060 if (Inst.getOperand(1).getReg() == Mips::ZERO || in processInstruction()
2061 Inst.getOperand(1).getReg() == Mips::ZERO_64) in processInstruction()
2067 case Mips::DSDIV: in processInstruction()
2068 case Mips::SDIV: in processInstruction()
2069 case Mips::UDIV: in processInstruction()
2070 case Mips::DUDIV: in processInstruction()
2071 case Mips::UDIV_MM: in processInstruction()
2072 case Mips::SDIV_MM: in processInstruction()
2076 case Mips::SDivMacro: in processInstruction()
2077 case Mips::DSDivMacro: in processInstruction()
2078 case Mips::UDivMacro: in processInstruction()
2079 case Mips::DUDivMacro: in processInstruction()
2080 case Mips::DIV: in processInstruction()
2081 case Mips::DIVU: in processInstruction()
2082 case Mips::DDIV: in processInstruction()
2083 case Mips::DDIVU: in processInstruction()
2084 case Mips::DIVU_MMR6: in processInstruction()
2085 case Mips::DIV_MMR6: in processInstruction()
2086 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || in processInstruction()
2087 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { in processInstruction()
2088 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || in processInstruction()
2089 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) in processInstruction()
2098 if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) { in processInstruction()
2100 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); in processInstruction()
2101 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2102 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2109 if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { in processInstruction()
2123 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), in processInstruction()
2129 JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM); in processInstruction()
2131 JalrInst.setOpcode(Mips::JALR); in processInstruction()
2132 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in processInstruction()
2133 JalrInst.addOperand(MCOperand::createReg(Mips::T9)); in processInstruction()
2172 if (MCID.mayLoad() && Opcode != Mips::LWP_MM) { in processInstruction()
2185 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2186 (BaseReg.getReg() == Mips::GP || in processInstruction()
2187 BaseReg.getReg() == Mips::GP_64)) { in processInstruction()
2189 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2206 case Mips::ADDIUSP_MM: in processInstruction()
2215 case Mips::SLL16_MM: in processInstruction()
2216 case Mips::SRL16_MM: in processInstruction()
2224 case Mips::LI16_MM: in processInstruction()
2232 case Mips::ADDIUR2_MM: in processInstruction()
2241 case Mips::ANDI16_MM: in processInstruction()
2251 case Mips::LBU16_MM: in processInstruction()
2259 case Mips::SB16_MM: in processInstruction()
2260 case Mips::SB16_MMR6: in processInstruction()
2268 case Mips::LHU16_MM: in processInstruction()
2269 case Mips::SH16_MM: in processInstruction()
2270 case Mips::SH16_MMR6: in processInstruction()
2278 case Mips::LW16_MM: in processInstruction()
2279 case Mips::SW16_MM: in processInstruction()
2280 case Mips::SW16_MMR6: in processInstruction()
2288 case Mips::ADDIUPC_MM: in processInstruction()
2296 case Mips::LWP_MM: in processInstruction()
2297 case Mips::SWP_MM: in processInstruction()
2298 if (Inst.getOperand(0).getReg() == Mips::RA) in processInstruction()
2301 case Mips::MOVEP_MM: in processInstruction()
2302 case Mips::MOVEP_MMR6: { in processInstruction()
2305 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || in processInstruction()
2306 (R0 == Mips::A1 && R1 == Mips::A3) || in processInstruction()
2307 (R0 == Mips::A2 && R1 == Mips::A3) || in processInstruction()
2308 (R0 == Mips::A0 && R1 == Mips::S5) || in processInstruction()
2309 (R0 == Mips::A0 && R1 == Mips::S6) || in processInstruction()
2310 (R0 == Mips::A0 && R1 == Mips::A1) || in processInstruction()
2311 (R0 == Mips::A0 && R1 == Mips::A2) || in processInstruction()
2312 (R0 == Mips::A0 && R1 == Mips::A3)); in processInstruction()
2404 if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg || in processInstruction()
2441 case Mips::LoadImm32: in tryExpandInstruction()
2443 case Mips::LoadImm64: in tryExpandInstruction()
2445 case Mips::LoadAddrImm32: in tryExpandInstruction()
2446 case Mips::LoadAddrImm64: in tryExpandInstruction()
2451 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, in tryExpandInstruction()
2453 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
2457 case Mips::LoadAddrReg32: in tryExpandInstruction()
2458 case Mips::LoadAddrReg64: in tryExpandInstruction()
2466 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
2470 case Mips::B_MM_Pseudo: in tryExpandInstruction()
2471 case Mips::B_MMR6_Pseudo: in tryExpandInstruction()
2474 case Mips::SWM_MM: in tryExpandInstruction()
2475 case Mips::LWM_MM: in tryExpandInstruction()
2478 case Mips::JalOneReg: in tryExpandInstruction()
2479 case Mips::JalTwoReg: in tryExpandInstruction()
2481 case Mips::BneImm: in tryExpandInstruction()
2482 case Mips::BeqImm: in tryExpandInstruction()
2483 case Mips::BEQLImmMacro: in tryExpandInstruction()
2484 case Mips::BNELImmMacro: in tryExpandInstruction()
2486 case Mips::BLT: in tryExpandInstruction()
2487 case Mips::BLE: in tryExpandInstruction()
2488 case Mips::BGE: in tryExpandInstruction()
2489 case Mips::BGT: in tryExpandInstruction()
2490 case Mips::BLTU: in tryExpandInstruction()
2491 case Mips::BLEU: in tryExpandInstruction()
2492 case Mips::BGEU: in tryExpandInstruction()
2493 case Mips::BGTU: in tryExpandInstruction()
2494 case Mips::BLTL: in tryExpandInstruction()
2495 case Mips::BLEL: in tryExpandInstruction()
2496 case Mips::BGEL: in tryExpandInstruction()
2497 case Mips::BGTL: in tryExpandInstruction()
2498 case Mips::BLTUL: in tryExpandInstruction()
2499 case Mips::BLEUL: in tryExpandInstruction()
2500 case Mips::BGEUL: in tryExpandInstruction()
2501 case Mips::BGTUL: in tryExpandInstruction()
2502 case Mips::BLTImmMacro: in tryExpandInstruction()
2503 case Mips::BLEImmMacro: in tryExpandInstruction()
2504 case Mips::BGEImmMacro: in tryExpandInstruction()
2505 case Mips::BGTImmMacro: in tryExpandInstruction()
2506 case Mips::BLTUImmMacro: in tryExpandInstruction()
2507 case Mips::BLEUImmMacro: in tryExpandInstruction()
2508 case Mips::BGEUImmMacro: in tryExpandInstruction()
2509 case Mips::BGTUImmMacro: in tryExpandInstruction()
2510 case Mips::BLTLImmMacro: in tryExpandInstruction()
2511 case Mips::BLELImmMacro: in tryExpandInstruction()
2512 case Mips::BGELImmMacro: in tryExpandInstruction()
2513 case Mips::BGTLImmMacro: in tryExpandInstruction()
2514 case Mips::BLTULImmMacro: in tryExpandInstruction()
2515 case Mips::BLEULImmMacro: in tryExpandInstruction()
2516 case Mips::BGEULImmMacro: in tryExpandInstruction()
2517 case Mips::BGTULImmMacro: in tryExpandInstruction()
2519 case Mips::SDivMacro: in tryExpandInstruction()
2520 case Mips::SDivIMacro: in tryExpandInstruction()
2521 case Mips::SRemMacro: in tryExpandInstruction()
2522 case Mips::SRemIMacro: in tryExpandInstruction()
2525 case Mips::DSDivMacro: in tryExpandInstruction()
2526 case Mips::DSDivIMacro: in tryExpandInstruction()
2527 case Mips::DSRemMacro: in tryExpandInstruction()
2528 case Mips::DSRemIMacro: in tryExpandInstruction()
2531 case Mips::UDivMacro: in tryExpandInstruction()
2532 case Mips::UDivIMacro: in tryExpandInstruction()
2533 case Mips::URemMacro: in tryExpandInstruction()
2534 case Mips::URemIMacro: in tryExpandInstruction()
2537 case Mips::DUDivMacro: in tryExpandInstruction()
2538 case Mips::DUDivIMacro: in tryExpandInstruction()
2539 case Mips::DURemMacro: in tryExpandInstruction()
2540 case Mips::DURemIMacro: in tryExpandInstruction()
2543 case Mips::PseudoTRUNC_W_S: in tryExpandInstruction()
2546 case Mips::PseudoTRUNC_W_D32: in tryExpandInstruction()
2549 case Mips::PseudoTRUNC_W_D: in tryExpandInstruction()
2553 case Mips::LoadImmSingleGPR: in tryExpandInstruction()
2556 case Mips::LoadImmSingleFGR: in tryExpandInstruction()
2559 case Mips::LoadImmDoubleGPR: in tryExpandInstruction()
2562 case Mips::LoadImmDoubleFGR: in tryExpandInstruction()
2565 case Mips::LoadImmDoubleFGR_32: in tryExpandInstruction()
2569 case Mips::Ulh: in tryExpandInstruction()
2571 case Mips::Ulhu: in tryExpandInstruction()
2573 case Mips::Ush: in tryExpandInstruction()
2575 case Mips::Ulw: in tryExpandInstruction()
2576 case Mips::Usw: in tryExpandInstruction()
2578 case Mips::NORImm: in tryExpandInstruction()
2579 case Mips::NORImm64: in tryExpandInstruction()
2581 case Mips::SGE: in tryExpandInstruction()
2582 case Mips::SGEU: in tryExpandInstruction()
2584 case Mips::SGEImm: in tryExpandInstruction()
2585 case Mips::SGEUImm: in tryExpandInstruction()
2586 case Mips::SGEImm64: in tryExpandInstruction()
2587 case Mips::SGEUImm64: in tryExpandInstruction()
2589 case Mips::SGTImm: in tryExpandInstruction()
2590 case Mips::SGTUImm: in tryExpandInstruction()
2591 case Mips::SGTImm64: in tryExpandInstruction()
2592 case Mips::SGTUImm64: in tryExpandInstruction()
2594 case Mips::SLE: in tryExpandInstruction()
2595 case Mips::SLEU: in tryExpandInstruction()
2597 case Mips::SLEImm: in tryExpandInstruction()
2598 case Mips::SLEUImm: in tryExpandInstruction()
2599 case Mips::SLEImm64: in tryExpandInstruction()
2600 case Mips::SLEUImm64: in tryExpandInstruction()
2602 case Mips::SLTImm64: in tryExpandInstruction()
2604 Inst.setOpcode(Mips::SLTi64); in tryExpandInstruction()
2608 case Mips::SLTUImm64: in tryExpandInstruction()
2610 Inst.setOpcode(Mips::SLTiu64); in tryExpandInstruction()
2614 case Mips::ADDi: case Mips::ADDi_MM: in tryExpandInstruction()
2615 case Mips::ADDiu: case Mips::ADDiu_MM: in tryExpandInstruction()
2616 case Mips::SLTi: case Mips::SLTi_MM: in tryExpandInstruction()
2617 case Mips::SLTiu: case Mips::SLTiu_MM: in tryExpandInstruction()
2627 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64: in tryExpandInstruction()
2628 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: in tryExpandInstruction()
2629 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64: in tryExpandInstruction()
2639 case Mips::ROL: in tryExpandInstruction()
2640 case Mips::ROR: in tryExpandInstruction()
2642 case Mips::ROLImm: in tryExpandInstruction()
2643 case Mips::RORImm: in tryExpandInstruction()
2645 case Mips::DROL: in tryExpandInstruction()
2646 case Mips::DROR: in tryExpandInstruction()
2648 case Mips::DROLImm: in tryExpandInstruction()
2649 case Mips::DRORImm: in tryExpandInstruction()
2651 case Mips::ABSMacro: in tryExpandInstruction()
2653 case Mips::MULImmMacro: in tryExpandInstruction()
2654 case Mips::DMULImmMacro: in tryExpandInstruction()
2656 case Mips::MULOMacro: in tryExpandInstruction()
2657 case Mips::DMULOMacro: in tryExpandInstruction()
2659 case Mips::MULOUMacro: in tryExpandInstruction()
2660 case Mips::DMULOUMacro: in tryExpandInstruction()
2662 case Mips::DMULMacro: in tryExpandInstruction()
2664 case Mips::LDMacro: in tryExpandInstruction()
2665 case Mips::SDMacro: in tryExpandInstruction()
2667 Inst.getOpcode() == Mips::LDMacro) in tryExpandInstruction()
2670 case Mips::SDC1_M1: in tryExpandInstruction()
2674 case Mips::SEQMacro: in tryExpandInstruction()
2676 case Mips::SEQIMacro: in tryExpandInstruction()
2678 case Mips::SNEMacro: in tryExpandInstruction()
2680 case Mips::SNEIMacro: in tryExpandInstruction()
2682 case Mips::MFTC0: case Mips::MTTC0: in tryExpandInstruction()
2683 case Mips::MFTGPR: case Mips::MTTGPR: in tryExpandInstruction()
2684 case Mips::MFTLO: case Mips::MTTLO: in tryExpandInstruction()
2685 case Mips::MFTHI: case Mips::MTTHI: in tryExpandInstruction()
2686 case Mips::MFTACX: case Mips::MTTACX: in tryExpandInstruction()
2687 case Mips::MFTDSP: case Mips::MTTDSP: in tryExpandInstruction()
2688 case Mips::MFTC1: case Mips::MTTC1: in tryExpandInstruction()
2689 case Mips::MFTHC1: case Mips::MTTHC1: in tryExpandInstruction()
2690 case Mips::CFTC1: case Mips::CTTC1: in tryExpandInstruction()
2692 case Mips::SaaAddr: in tryExpandInstruction()
2693 case Mips::SaadAddr: in tryExpandInstruction()
2709 if (Opcode == Mips::JalOneReg) { in expandJalWithRegs()
2712 JalrInst.setOpcode(Mips::JALRS16_MM); in expandJalWithRegs()
2715 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM); in expandJalWithRegs()
2718 JalrInst.setOpcode(Mips::JALR); in expandJalWithRegs()
2719 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in expandJalWithRegs()
2722 } else if (Opcode == Mips::JalTwoReg) { in expandJalWithRegs()
2725 JalrInst.setOpcode(Mips::JALRS_MM); in expandJalWithRegs()
2727 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in expandJalWithRegs()
2753 /// @param SrcReg A register to add to the immediate or Mips::NoRegister
2783 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; in loadImmediate()
2786 if (SrcReg != Mips::NoRegister) in loadImmediate()
2808 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2812 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2824 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2839 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2840 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2848 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2849 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2851 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2857 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2859 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2880 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2881 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2896 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, in loadImmediate()
2908 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2933 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2977 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && in loadAndAddSymbolAddress()
2978 SrcReg != Mips::ZERO_64; in loadAndAddSymbolAddress()
3004 bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym; in loadAndAddSymbolAddress()
3010 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
3017 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
3019 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
3021 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, in loadAndAddSymbolAddress()
3026 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, in loadAndAddSymbolAddress()
3062 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
3064 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg, in loadAndAddSymbolAddress()
3066 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3070 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3076 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3133 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg, in loadAndAddSymbolAddress()
3137 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3141 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3181 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3183 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in loadAndAddSymbolAddress()
3185 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3186 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in loadAndAddSymbolAddress()
3188 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3189 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3191 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3208 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3210 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3211 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3213 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3215 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3216 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3218 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3231 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3233 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3235 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3236 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3238 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3239 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3242 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3276 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3277 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3281 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3293 if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) in nextReg()
3294 return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; in nextReg()
3297 case Mips::ZERO: return Mips::AT; in nextReg()
3298 case Mips::AT: return Mips::V0; in nextReg()
3299 case Mips::V0: return Mips::V1; in nextReg()
3300 case Mips::V1: return Mips::A0; in nextReg()
3301 case Mips::A0: return Mips::A1; in nextReg()
3302 case Mips::A1: return Mips::A2; in nextReg()
3303 case Mips::A2: return Mips::A3; in nextReg()
3304 case Mips::A3: return Mips::T0; in nextReg()
3305 case Mips::T0: return Mips::T1; in nextReg()
3306 case Mips::T1: return Mips::T2; in nextReg()
3307 case Mips::T2: return Mips::T3; in nextReg()
3308 case Mips::T3: return Mips::T4; in nextReg()
3309 case Mips::T4: return Mips::T5; in nextReg()
3310 case Mips::T5: return Mips::T6; in nextReg()
3311 case Mips::T6: return Mips::T7; in nextReg()
3312 case Mips::T7: return Mips::S0; in nextReg()
3313 case Mips::S0: return Mips::S1; in nextReg()
3314 case Mips::S1: return Mips::S2; in nextReg()
3315 case Mips::S2: return Mips::S3; in nextReg()
3316 case Mips::S3: return Mips::S4; in nextReg()
3317 case Mips::S4: return Mips::S5; in nextReg()
3318 case Mips::S5: return Mips::S6; in nextReg()
3319 case Mips::S6: return Mips::S7; in nextReg()
3320 case Mips::S7: return Mips::T8; in nextReg()
3321 case Mips::T8: return Mips::T9; in nextReg()
3322 case Mips::T9: return Mips::K0; in nextReg()
3323 case Mips::K0: return Mips::K1; in nextReg()
3324 case Mips::K1: return Mips::GP; in nextReg()
3325 case Mips::GP: return Mips::SP; in nextReg()
3326 case Mips::SP: return Mips::FP; in nextReg()
3327 case Mips::FP: return Mips::RA; in nextReg()
3328 case Mips::RA: return Mips::ZERO; in nextReg()
3329 case Mips::D0: return Mips::F1; in nextReg()
3330 case Mips::D1: return Mips::F3; in nextReg()
3331 case Mips::D2: return Mips::F5; in nextReg()
3332 case Mips::D3: return Mips::F7; in nextReg()
3333 case Mips::D4: return Mips::F9; in nextReg()
3334 case Mips::D5: return Mips::F11; in nextReg()
3335 case Mips::D6: return Mips::F13; in nextReg()
3336 case Mips::D7: return Mips::F15; in nextReg()
3337 case Mips::D8: return Mips::F17; in nextReg()
3338 case Mips::D9: return Mips::F19; in nextReg()
3339 case Mips::D10: return Mips::F21; in nextReg()
3340 case Mips::D11: return Mips::F23; in nextReg()
3341 case Mips::D12: return Mips::F25; in nextReg()
3342 case Mips::D13: return Mips::F27; in nextReg()
3343 case Mips::D14: return Mips::F29; in nextReg()
3344 case Mips::D15: return Mips::F31; in nextReg()
3367 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3370 TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3386 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in emitPartialAddress()
3397 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in emitPartialAddress()
3399 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in emitPartialAddress()
3401 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3402 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in emitPartialAddress()
3404 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3440 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3459 unsigned TmpReg = Mips::ZERO; in expandLoadSingleImmToFPR()
3467 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, in expandLoadSingleImmToFPR()
3470 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3493 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3513 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3517 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3521 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3551 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in expandLoadDoubleImmToGPR()
3555 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3557 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3558 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); in expandLoadDoubleImmToGPR()
3576 unsigned TmpReg = Mips::ZERO; in expandLoadDoubleImmToFPR()
3586 if (TmpReg != Mips::ZERO && in expandLoadDoubleImmToFPR()
3587 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, in expandLoadDoubleImmToFPR()
3590 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3594 if (TmpReg != Mips::ZERO && in expandLoadDoubleImmToFPR()
3595 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToFPR()
3600 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3601 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3603 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3604 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3630 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg, in expandLoadDoubleImmToFPR()
3647 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3648 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3649 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3657 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM); in expandUncondBranchMMPseudo()
3664 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3665 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3666 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3698 case Mips::BneImm: in expandBranchImm()
3699 OpCode = Mips::BNE; in expandBranchImm()
3701 case Mips::BeqImm: in expandBranchImm()
3702 OpCode = Mips::BEQ; in expandBranchImm()
3704 case Mips::BEQLImmMacro: in expandBranchImm()
3705 OpCode = Mips::BEQL; in expandBranchImm()
3708 case Mips::BNELImmMacro: in expandBranchImm()
3709 OpCode = Mips::BNEL; in expandBranchImm()
3720 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, in expandBranchImm()
3722 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3724 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3733 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, in expandBranchImm()
3740 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3769 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMem16Inst()
3770 (DstRegClassID == Mips::GPR64RegClassID); in expandMem16Inst()
3800 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true, in expandMem16Inst()
3805 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) in expandMem16Inst()
3806 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, in expandMem16Inst()
3851 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI); in expandMem16Inst()
3852 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI); in expandMem16Inst()
3853 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3854 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3855 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3856 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) in expandMem16Inst()
3857 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3861 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3862 if (BaseReg != Mips::ZERO) in expandMem16Inst()
3863 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3896 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMem9Inst()
3897 (DstRegClassID == Mips::GPR64RegClassID); in expandMem9Inst()
3937 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple()
3945 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP || in expandLoadStoreMultiple()
3946 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) && in expandLoadStoreMultiple()
3947 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA || in expandLoadStoreMultiple()
3948 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) { in expandLoadStoreMultiple()
3951 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; in expandLoadStoreMultiple()
3953 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
3988 case Mips::BLTImmMacro: in expandCondBranches()
3989 PseudoOpcode = Mips::BLT; in expandCondBranches()
3991 case Mips::BLEImmMacro: in expandCondBranches()
3992 PseudoOpcode = Mips::BLE; in expandCondBranches()
3994 case Mips::BGEImmMacro: in expandCondBranches()
3995 PseudoOpcode = Mips::BGE; in expandCondBranches()
3997 case Mips::BGTImmMacro: in expandCondBranches()
3998 PseudoOpcode = Mips::BGT; in expandCondBranches()
4000 case Mips::BLTUImmMacro: in expandCondBranches()
4001 PseudoOpcode = Mips::BLTU; in expandCondBranches()
4003 case Mips::BLEUImmMacro: in expandCondBranches()
4004 PseudoOpcode = Mips::BLEU; in expandCondBranches()
4006 case Mips::BGEUImmMacro: in expandCondBranches()
4007 PseudoOpcode = Mips::BGEU; in expandCondBranches()
4009 case Mips::BGTUImmMacro: in expandCondBranches()
4010 PseudoOpcode = Mips::BGTU; in expandCondBranches()
4012 case Mips::BLTLImmMacro: in expandCondBranches()
4013 PseudoOpcode = Mips::BLTL; in expandCondBranches()
4015 case Mips::BLELImmMacro: in expandCondBranches()
4016 PseudoOpcode = Mips::BLEL; in expandCondBranches()
4018 case Mips::BGELImmMacro: in expandCondBranches()
4019 PseudoOpcode = Mips::BGEL; in expandCondBranches()
4021 case Mips::BGTLImmMacro: in expandCondBranches()
4022 PseudoOpcode = Mips::BGTL; in expandCondBranches()
4024 case Mips::BLTULImmMacro: in expandCondBranches()
4025 PseudoOpcode = Mips::BLTUL; in expandCondBranches()
4027 case Mips::BLEULImmMacro: in expandCondBranches()
4028 PseudoOpcode = Mips::BLEUL; in expandCondBranches()
4030 case Mips::BGEULImmMacro: in expandCondBranches()
4031 PseudoOpcode = Mips::BGEUL; in expandCondBranches()
4033 case Mips::BGTULImmMacro: in expandCondBranches()
4034 PseudoOpcode = Mips::BGTUL; in expandCondBranches()
4038 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), in expandCondBranches()
4044 case Mips::BLT: in expandCondBranches()
4045 case Mips::BLTU: in expandCondBranches()
4046 case Mips::BLTL: in expandCondBranches()
4047 case Mips::BLTUL: in expandCondBranches()
4051 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
4052 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
4053 ZeroSrcOpcode = Mips::BGTZ; in expandCondBranches()
4054 ZeroTrgOpcode = Mips::BLTZ; in expandCondBranches()
4056 case Mips::BLE: in expandCondBranches()
4057 case Mips::BLEU: in expandCondBranches()
4058 case Mips::BLEL: in expandCondBranches()
4059 case Mips::BLEUL: in expandCondBranches()
4063 ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
4064 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
4065 ZeroSrcOpcode = Mips::BGEZ; in expandCondBranches()
4066 ZeroTrgOpcode = Mips::BLEZ; in expandCondBranches()
4068 case Mips::BGE: in expandCondBranches()
4069 case Mips::BGEU: in expandCondBranches()
4070 case Mips::BGEL: in expandCondBranches()
4071 case Mips::BGEUL: in expandCondBranches()
4075 ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
4076 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
4077 ZeroSrcOpcode = Mips::BLEZ; in expandCondBranches()
4078 ZeroTrgOpcode = Mips::BGEZ; in expandCondBranches()
4080 case Mips::BGT: in expandCondBranches()
4081 case Mips::BGTU: in expandCondBranches()
4082 case Mips::BGTL: in expandCondBranches()
4083 case Mips::BGTUL: in expandCondBranches()
4087 ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
4088 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
4089 ZeroSrcOpcode = Mips::BLTZ; in expandCondBranches()
4090 ZeroTrgOpcode = Mips::BGTZ; in expandCondBranches()
4096 bool IsTrgRegZero = (TrgReg == Mips::ZERO); in expandCondBranches()
4097 bool IsSrcRegZero = (SrcReg == Mips::ZERO); in expandCondBranches()
4102 if (PseudoOpcode == Mips::BLT) { in expandCondBranches()
4103 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4107 if (PseudoOpcode == Mips::BLE) { in expandCondBranches()
4108 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4113 if (PseudoOpcode == Mips::BGE) { in expandCondBranches()
4114 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4119 if (PseudoOpcode == Mips::BGT) { in expandCondBranches()
4120 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4124 if (PseudoOpcode == Mips::BGTU) { in expandCondBranches()
4125 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4132 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4142 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) || in expandCondBranches()
4143 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { in expandCondBranches()
4150 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) || in expandCondBranches()
4151 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) { in expandCondBranches()
4157 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4175 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, in expandCondBranches()
4176 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO, in expandCondBranches()
4213 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4217 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL) in expandCondBranches()
4218 : (AcceptsEquality ? Mips::BEQ : Mips::BNE), in expandCondBranches()
4219 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
4263 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV; in expandDivRem()
4264 ZeroReg = Mips::ZERO_64; in expandDivRem()
4265 SubOp = Mips::DSUB; in expandDivRem()
4267 DivOp = Signed ? Mips::SDIV : Mips::UDIV; in expandDivRem()
4268 ZeroReg = Mips::ZERO; in expandDivRem()
4269 SubOp = Mips::SUB; in expandDivRem()
4275 bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro || in expandDivRem()
4276 Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro || in expandDivRem()
4277 Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro || in expandDivRem()
4278 Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro; in expandDivRem()
4280 bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro || in expandDivRem()
4281 Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro || in expandDivRem()
4282 Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro || in expandDivRem()
4283 Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro; in expandDivRem()
4292 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4294 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4299 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4302 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); in expandDivRem()
4308 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), in expandDivRem()
4312 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4322 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { in expandDivRem()
4324 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4327 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4333 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) { in expandDivRem()
4344 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4349 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4355 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4361 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4372 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4380 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4383 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4386 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDivRem()
4390 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
4393 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4395 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDivRem()
4399 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4420 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4421 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4423 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
4424 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
4425 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4427 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32) in expandTrunc()
4428 : Mips::CVT_W_S, in expandTrunc()
4430 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
4435 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32) in expandTrunc()
4436 : Mips::TRUNC_W_S, in expandTrunc()
4485 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, in expandUlh()
4487 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); in expandUlh()
4488 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
4489 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4530 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4531 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4532 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4533 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); in expandUsh()
4534 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4535 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4537 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4538 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4539 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); in expandUsh()
4570 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); in expandUxw()
4589 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()
4590 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()
4595 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4617 case Mips::SGE: in expandSge()
4618 OpCode = Mips::SLT; in expandSge()
4620 case Mips::SGEU: in expandSge()
4621 OpCode = Mips::SLTu; in expandSge()
4629 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4651 case Mips::SGEImm: in expandSgeImm()
4652 case Mips::SGEImm64: in expandSgeImm()
4653 OpRegCode = Mips::SLT; in expandSgeImm()
4654 OpImmCode = Mips::SLTi; in expandSgeImm()
4656 case Mips::SGEUImm: in expandSgeImm()
4657 case Mips::SGEUImm64: in expandSgeImm()
4658 OpRegCode = Mips::SLTu; in expandSgeImm()
4659 OpImmCode = Mips::SLTiu; in expandSgeImm()
4669 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4679 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgeImm()
4684 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4708 case Mips::SGTImm: in expandSgtImm()
4709 case Mips::SGTImm64: in expandSgtImm()
4710 OpCode = Mips::SLT; in expandSgtImm()
4712 case Mips::SGTUImm: in expandSgtImm()
4713 case Mips::SGTUImm64: in expandSgtImm()
4714 OpCode = Mips::SLTu; in expandSgtImm()
4727 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgtImm()
4754 case Mips::SLE: in expandSle()
4755 OpCode = Mips::SLT; in expandSle()
4757 case Mips::SLEU: in expandSle()
4758 OpCode = Mips::SLTu; in expandSle()
4766 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4788 case Mips::SLEImm: in expandSleImm()
4789 case Mips::SLEImm64: in expandSleImm()
4790 OpRegCode = Mips::SLT; in expandSleImm()
4792 case Mips::SLEUImm: in expandSleImm()
4793 case Mips::SLEUImm64: in expandSleImm()
4794 OpRegCode = Mips::SLTu; in expandSleImm()
4809 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSleImm()
4814 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4829 unsigned ATReg = Mips::NoRegister; in expandAliasImmediate()
4830 unsigned FinalDstReg = Mips::NoRegister; in expandAliasImmediate()
4847 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, in expandAliasImmediate()
4852 case Mips::ADDi: in expandAliasImmediate()
4853 FinalOpcode = Mips::ADD; in expandAliasImmediate()
4855 case Mips::ADDiu: in expandAliasImmediate()
4856 FinalOpcode = Mips::ADDu; in expandAliasImmediate()
4858 case Mips::ANDi: in expandAliasImmediate()
4859 FinalOpcode = Mips::AND; in expandAliasImmediate()
4861 case Mips::NORImm: in expandAliasImmediate()
4862 FinalOpcode = Mips::NOR; in expandAliasImmediate()
4864 case Mips::ORi: in expandAliasImmediate()
4865 FinalOpcode = Mips::OR; in expandAliasImmediate()
4867 case Mips::SLTi: in expandAliasImmediate()
4868 FinalOpcode = Mips::SLT; in expandAliasImmediate()
4870 case Mips::SLTiu: in expandAliasImmediate()
4871 FinalOpcode = Mips::SLTu; in expandAliasImmediate()
4873 case Mips::XORi: in expandAliasImmediate()
4874 FinalOpcode = Mips::XOR; in expandAliasImmediate()
4876 case Mips::ADDi_MM: in expandAliasImmediate()
4877 FinalOpcode = Mips::ADD_MM; in expandAliasImmediate()
4879 case Mips::ADDiu_MM: in expandAliasImmediate()
4880 FinalOpcode = Mips::ADDu_MM; in expandAliasImmediate()
4882 case Mips::ANDi_MM: in expandAliasImmediate()
4883 FinalOpcode = Mips::AND_MM; in expandAliasImmediate()
4885 case Mips::ORi_MM: in expandAliasImmediate()
4886 FinalOpcode = Mips::OR_MM; in expandAliasImmediate()
4888 case Mips::SLTi_MM: in expandAliasImmediate()
4889 FinalOpcode = Mips::SLT_MM; in expandAliasImmediate()
4891 case Mips::SLTiu_MM: in expandAliasImmediate()
4892 FinalOpcode = Mips::SLTu_MM; in expandAliasImmediate()
4894 case Mips::XORi_MM: in expandAliasImmediate()
4895 FinalOpcode = Mips::XOR_MM; in expandAliasImmediate()
4897 case Mips::ANDi64: in expandAliasImmediate()
4898 FinalOpcode = Mips::AND64; in expandAliasImmediate()
4900 case Mips::NORImm64: in expandAliasImmediate()
4901 FinalOpcode = Mips::NOR64; in expandAliasImmediate()
4903 case Mips::ORi64: in expandAliasImmediate()
4904 FinalOpcode = Mips::OR64; in expandAliasImmediate()
4906 case Mips::SLTImm64: in expandAliasImmediate()
4907 FinalOpcode = Mips::SLT64; in expandAliasImmediate()
4909 case Mips::SLTUImm64: in expandAliasImmediate()
4910 FinalOpcode = Mips::SLTu64; in expandAliasImmediate()
4912 case Mips::XORi64: in expandAliasImmediate()
4913 FinalOpcode = Mips::XOR64; in expandAliasImmediate()
4917 if (FinalDstReg == Mips::NoRegister) in expandAliasImmediate()
4929 unsigned ATReg = Mips::NoRegister; in expandRotation()
4935 unsigned FirstShift = Mips::NOP; in expandRotation()
4936 unsigned SecondShift = Mips::NOP; in expandRotation()
4945 if (Inst.getOpcode() == Mips::ROL) { in expandRotation()
4946 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4947 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4951 if (Inst.getOpcode() == Mips::ROR) { in expandRotation()
4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4963 case Mips::ROL: in expandRotation()
4964 FirstShift = Mips::SRLV; in expandRotation()
4965 SecondShift = Mips::SLLV; in expandRotation()
4967 case Mips::ROR: in expandRotation()
4968 FirstShift = Mips::SLLV; in expandRotation()
4969 SecondShift = Mips::SRLV; in expandRotation()
4977 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4980 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4992 unsigned ATReg = Mips::NoRegister; in expandRotationImm()
4997 unsigned FirstShift = Mips::NOP; in expandRotationImm()
4998 unsigned SecondShift = Mips::NOP; in expandRotationImm()
5001 if (Inst.getOpcode() == Mips::ROLImm) { in expandRotationImm()
5006 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
5010 if (Inst.getOpcode() == Mips::RORImm) { in expandRotationImm()
5011 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
5020 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
5027 case Mips::ROLImm: in expandRotationImm()
5028 FirstShift = Mips::SLL; in expandRotationImm()
5029 SecondShift = Mips::SRL; in expandRotationImm()
5031 case Mips::RORImm: in expandRotationImm()
5032 FirstShift = Mips::SRL; in expandRotationImm()
5033 SecondShift = Mips::SLL; in expandRotationImm()
5043 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm()
5054 unsigned ATReg = Mips::NoRegister; in expandDRotation()
5060 unsigned FirstShift = Mips::NOP; in expandDRotation()
5061 unsigned SecondShift = Mips::NOP; in expandDRotation()
5070 if (Inst.getOpcode() == Mips::DROL) { in expandDRotation()
5071 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5072 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandDRotation()
5076 if (Inst.getOpcode() == Mips::DROR) { in expandDRotation()
5077 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
5088 case Mips::DROL: in expandDRotation()
5089 FirstShift = Mips::DSRLV; in expandDRotation()
5090 SecondShift = Mips::DSLLV; in expandDRotation()
5092 case Mips::DROR: in expandDRotation()
5093 FirstShift = Mips::DSLLV; in expandDRotation()
5094 SecondShift = Mips::DSRLV; in expandDRotation()
5102 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5105 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation()
5117 unsigned ATReg = Mips::NoRegister; in expandDRotationImm()
5122 unsigned FirstShift = Mips::NOP; in expandDRotationImm()
5123 unsigned SecondShift = Mips::NOP; in expandDRotationImm()
5128 unsigned FinalOpcode = Mips::NOP; in expandDRotationImm()
5130 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5132 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5134 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5135 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5137 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5139 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5140 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5142 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5146 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5156 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
5163 case Mips::DROLImm: in expandDRotationImm()
5165 FirstShift = Mips::DSLL; in expandDRotationImm()
5166 SecondShift = Mips::DSRL32; in expandDRotationImm()
5169 FirstShift = Mips::DSLL32; in expandDRotationImm()
5170 SecondShift = Mips::DSRL32; in expandDRotationImm()
5173 FirstShift = Mips::DSLL32; in expandDRotationImm()
5174 SecondShift = Mips::DSRL; in expandDRotationImm()
5177 case Mips::DRORImm: in expandDRotationImm()
5179 FirstShift = Mips::DSRL; in expandDRotationImm()
5180 SecondShift = Mips::DSLL32; in expandDRotationImm()
5183 FirstShift = Mips::DSRL32; in expandDRotationImm()
5184 SecondShift = Mips::DSLL32; in expandDRotationImm()
5187 FirstShift = Mips::DSRL32; in expandDRotationImm()
5188 SecondShift = Mips::DSLL; in expandDRotationImm()
5200 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotationImm()
5214 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
5216 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
5219 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
5227 unsigned ATReg = Mips::NoRegister; in expandMulImm()
5236 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, in expandMulImm()
5239 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, in expandMulImm()
5242 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5250 unsigned ATReg = Mips::NoRegister; in expandMulO()
5259 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, in expandMulO()
5262 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5264 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
5267 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5270 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5277 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5280 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulO()
5284 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5292 unsigned ATReg = Mips::NoRegister; in expandMulOU()
5301 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu, in expandMulOU()
5304 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
5305 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5307 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); in expandMulOU()
5314 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
5317 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulOU()
5332 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); in expandDMULMacro()
5333 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5353 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; in expandLoadStoreDMacro()
5400 unsigned Opcode = Mips::SWC1; in expandStoreDM1Macro()
5443 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5445 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5449 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5450 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5470 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5474 if (SrcReg == Mips::ZERO) { in expandSeqI()
5476 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, in expandSeqI()
5484 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSeqI()
5486 Opc = Mips::XORi; in expandSeqI()
5494 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, in expandSeqI()
5498 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5499 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5504 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5524 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
5525 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5526 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5530 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSne()
5531 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5551 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5555 if (SrcReg == Mips::ZERO) { in expandSneI()
5557 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5566 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSneI()
5568 Opc = Mips::XORi; in expandSneI()
5573 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5581 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSneI()
5585 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5586 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5595 case Mips::MFTLO: in getRegisterForMxtrDSP()
5596 case Mips::MTTLO: in getRegisterForMxtrDSP()
5598 case Mips::AC0: in getRegisterForMxtrDSP()
5599 return Mips::ZERO; in getRegisterForMxtrDSP()
5600 case Mips::AC1: in getRegisterForMxtrDSP()
5601 return Mips::A0; in getRegisterForMxtrDSP()
5602 case Mips::AC2: in getRegisterForMxtrDSP()
5603 return Mips::T0; in getRegisterForMxtrDSP()
5604 case Mips::AC3: in getRegisterForMxtrDSP()
5605 return Mips::T4; in getRegisterForMxtrDSP()
5609 case Mips::MFTHI: in getRegisterForMxtrDSP()
5610 case Mips::MTTHI: in getRegisterForMxtrDSP()
5612 case Mips::AC0: in getRegisterForMxtrDSP()
5613 return Mips::AT; in getRegisterForMxtrDSP()
5614 case Mips::AC1: in getRegisterForMxtrDSP()
5615 return Mips::A1; in getRegisterForMxtrDSP()
5616 case Mips::AC2: in getRegisterForMxtrDSP()
5617 return Mips::T1; in getRegisterForMxtrDSP()
5618 case Mips::AC3: in getRegisterForMxtrDSP()
5619 return Mips::T5; in getRegisterForMxtrDSP()
5623 case Mips::MFTACX: in getRegisterForMxtrDSP()
5624 case Mips::MTTACX: in getRegisterForMxtrDSP()
5626 case Mips::AC0: in getRegisterForMxtrDSP()
5627 return Mips::V0; in getRegisterForMxtrDSP()
5628 case Mips::AC1: in getRegisterForMxtrDSP()
5629 return Mips::A2; in getRegisterForMxtrDSP()
5630 case Mips::AC2: in getRegisterForMxtrDSP()
5631 return Mips::T2; in getRegisterForMxtrDSP()
5632 case Mips::AC3: in getRegisterForMxtrDSP()
5633 return Mips::T6; in getRegisterForMxtrDSP()
5637 case Mips::MFTDSP: in getRegisterForMxtrDSP()
5638 case Mips::MTTDSP: in getRegisterForMxtrDSP()
5639 return Mips::S0; in getRegisterForMxtrDSP()
5649 case Mips::F0: return Mips::ZERO; in getRegisterForMxtrFP()
5650 case Mips::F1: return Mips::AT; in getRegisterForMxtrFP()
5651 case Mips::F2: return Mips::V0; in getRegisterForMxtrFP()
5652 case Mips::F3: return Mips::V1; in getRegisterForMxtrFP()
5653 case Mips::F4: return Mips::A0; in getRegisterForMxtrFP()
5654 case Mips::F5: return Mips::A1; in getRegisterForMxtrFP()
5655 case Mips::F6: return Mips::A2; in getRegisterForMxtrFP()
5656 case Mips::F7: return Mips::A3; in getRegisterForMxtrFP()
5657 case Mips::F8: return Mips::T0; in getRegisterForMxtrFP()
5658 case Mips::F9: return Mips::T1; in getRegisterForMxtrFP()
5659 case Mips::F10: return Mips::T2; in getRegisterForMxtrFP()
5660 case Mips::F11: return Mips::T3; in getRegisterForMxtrFP()
5661 case Mips::F12: return Mips::T4; in getRegisterForMxtrFP()
5662 case Mips::F13: return Mips::T5; in getRegisterForMxtrFP()
5663 case Mips::F14: return Mips::T6; in getRegisterForMxtrFP()
5664 case Mips::F15: return Mips::T7; in getRegisterForMxtrFP()
5665 case Mips::F16: return Mips::S0; in getRegisterForMxtrFP()
5666 case Mips::F17: return Mips::S1; in getRegisterForMxtrFP()
5667 case Mips::F18: return Mips::S2; in getRegisterForMxtrFP()
5668 case Mips::F19: return Mips::S3; in getRegisterForMxtrFP()
5669 case Mips::F20: return Mips::S4; in getRegisterForMxtrFP()
5670 case Mips::F21: return Mips::S5; in getRegisterForMxtrFP()
5671 case Mips::F22: return Mips::S6; in getRegisterForMxtrFP()
5672 case Mips::F23: return Mips::S7; in getRegisterForMxtrFP()
5673 case Mips::F24: return Mips::T8; in getRegisterForMxtrFP()
5674 case Mips::F25: return Mips::T9; in getRegisterForMxtrFP()
5675 case Mips::F26: return Mips::K0; in getRegisterForMxtrFP()
5676 case Mips::F27: return Mips::K1; in getRegisterForMxtrFP()
5677 case Mips::F28: return Mips::GP; in getRegisterForMxtrFP()
5678 case Mips::F29: return Mips::SP; in getRegisterForMxtrFP()
5679 case Mips::F30: return Mips::FP; in getRegisterForMxtrFP()
5680 case Mips::F31: return Mips::RA; in getRegisterForMxtrFP()
5688 case Mips::COP00: return Mips::ZERO; in getRegisterForMxtrC0()
5689 case Mips::COP01: return Mips::AT; in getRegisterForMxtrC0()
5690 case Mips::COP02: return Mips::V0; in getRegisterForMxtrC0()
5691 case Mips::COP03: return Mips::V1; in getRegisterForMxtrC0()
5692 case Mips::COP04: return Mips::A0; in getRegisterForMxtrC0()
5693 case Mips::COP05: return Mips::A1; in getRegisterForMxtrC0()
5694 case Mips::COP06: return Mips::A2; in getRegisterForMxtrC0()
5695 case Mips::COP07: return Mips::A3; in getRegisterForMxtrC0()
5696 case Mips::COP08: return Mips::T0; in getRegisterForMxtrC0()
5697 case Mips::COP09: return Mips::T1; in getRegisterForMxtrC0()
5698 case Mips::COP010: return Mips::T2; in getRegisterForMxtrC0()
5699 case Mips::COP011: return Mips::T3; in getRegisterForMxtrC0()
5700 case Mips::COP012: return Mips::T4; in getRegisterForMxtrC0()
5701 case Mips::COP013: return Mips::T5; in getRegisterForMxtrC0()
5702 case Mips::COP014: return Mips::T6; in getRegisterForMxtrC0()
5703 case Mips::COP015: return Mips::T7; in getRegisterForMxtrC0()
5704 case Mips::COP016: return Mips::S0; in getRegisterForMxtrC0()
5705 case Mips::COP017: return Mips::S1; in getRegisterForMxtrC0()
5706 case Mips::COP018: return Mips::S2; in getRegisterForMxtrC0()
5707 case Mips::COP019: return Mips::S3; in getRegisterForMxtrC0()
5708 case Mips::COP020: return Mips::S4; in getRegisterForMxtrC0()
5709 case Mips::COP021: return Mips::S5; in getRegisterForMxtrC0()
5710 case Mips::COP022: return Mips::S6; in getRegisterForMxtrC0()
5711 case Mips::COP023: return Mips::S7; in getRegisterForMxtrC0()
5712 case Mips::COP024: return Mips::T8; in getRegisterForMxtrC0()
5713 case Mips::COP025: return Mips::T9; in getRegisterForMxtrC0()
5714 case Mips::COP026: return Mips::K0; in getRegisterForMxtrC0()
5715 case Mips::COP027: return Mips::K1; in getRegisterForMxtrC0()
5716 case Mips::COP028: return Mips::GP; in getRegisterForMxtrC0()
5717 case Mips::COP029: return Mips::SP; in getRegisterForMxtrC0()
5718 case Mips::COP030: return Mips::FP; in getRegisterForMxtrC0()
5719 case Mips::COP031: return Mips::RA; in getRegisterForMxtrC0()
5735 case Mips::MFTC0: in expandMXTRAlias()
5738 case Mips::MTTC0: in expandMXTRAlias()
5743 case Mips::MFTGPR: in expandMXTRAlias()
5746 case Mips::MTTGPR: in expandMXTRAlias()
5749 case Mips::MFTLO: in expandMXTRAlias()
5750 case Mips::MFTHI: in expandMXTRAlias()
5751 case Mips::MFTACX: in expandMXTRAlias()
5752 case Mips::MFTDSP: in expandMXTRAlias()
5755 case Mips::MTTLO: in expandMXTRAlias()
5756 case Mips::MTTHI: in expandMXTRAlias()
5757 case Mips::MTTACX: in expandMXTRAlias()
5758 case Mips::MTTDSP: in expandMXTRAlias()
5762 case Mips::MFTHC1: in expandMXTRAlias()
5765 case Mips::MFTC1: in expandMXTRAlias()
5770 case Mips::MTTHC1: in expandMXTRAlias()
5773 case Mips::MTTC1: in expandMXTRAlias()
5777 case Mips::CFTC1: in expandMXTRAlias()
5780 case Mips::CTTC1: in expandMXTRAlias()
5788 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg() in expandMXTRAlias()
5791 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, in expandMXTRAlias()
5805 unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD; in expandSaaAddr()
5835 case Mips::DATI: in checkEarlyTargetMatchPredicate()
5836 case Mips::DAHI: in checkEarlyTargetMatchPredicate()
5848 case Mips::DAUI: in checkTargetMatchPredicate()
5849 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5850 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5857 case Mips::JALR_HB: in checkTargetMatchPredicate()
5858 case Mips::JALR_HB64: in checkTargetMatchPredicate()
5859 case Mips::JALRC_HB_MMR6: in checkTargetMatchPredicate()
5860 case Mips::JALRC_MMR6: in checkTargetMatchPredicate()
5864 case Mips::LWP_MM: in checkTargetMatchPredicate()
5868 case Mips::SYNC: in checkTargetMatchPredicate()
5872 case Mips::MFC0: in checkTargetMatchPredicate()
5873 case Mips::MTC0: in checkTargetMatchPredicate()
5874 case Mips::MTC2: in checkTargetMatchPredicate()
5875 case Mips::MFC2: in checkTargetMatchPredicate()
5891 case Mips::BLEZC: case Mips::BLEZC_MMR6: in checkTargetMatchPredicate()
5892 case Mips::BGEZC: case Mips::BGEZC_MMR6: in checkTargetMatchPredicate()
5893 case Mips::BGTZC: case Mips::BGTZC_MMR6: in checkTargetMatchPredicate()
5894 case Mips::BLTZC: case Mips::BLTZC_MMR6: in checkTargetMatchPredicate()
5895 case Mips::BEQZC: case Mips::BEQZC_MMR6: in checkTargetMatchPredicate()
5896 case Mips::BNEZC: case Mips::BNEZC_MMR6: in checkTargetMatchPredicate()
5897 case Mips::BLEZC64: in checkTargetMatchPredicate()
5898 case Mips::BGEZC64: in checkTargetMatchPredicate()
5899 case Mips::BGTZC64: in checkTargetMatchPredicate()
5900 case Mips::BLTZC64: in checkTargetMatchPredicate()
5901 case Mips::BEQZC64: in checkTargetMatchPredicate()
5902 case Mips::BNEZC64: in checkTargetMatchPredicate()
5903 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5904 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5907 case Mips::BGEC: case Mips::BGEC_MMR6: in checkTargetMatchPredicate()
5908 case Mips::BLTC: case Mips::BLTC_MMR6: in checkTargetMatchPredicate()
5909 case Mips::BGEUC: case Mips::BGEUC_MMR6: in checkTargetMatchPredicate()
5910 case Mips::BLTUC: case Mips::BLTUC_MMR6: in checkTargetMatchPredicate()
5911 case Mips::BEQC: case Mips::BEQC_MMR6: in checkTargetMatchPredicate()
5912 case Mips::BNEC: case Mips::BNEC_MMR6: in checkTargetMatchPredicate()
5913 case Mips::BGEC64: in checkTargetMatchPredicate()
5914 case Mips::BLTC64: in checkTargetMatchPredicate()
5915 case Mips::BGEUC64: in checkTargetMatchPredicate()
5916 case Mips::BLTUC64: in checkTargetMatchPredicate()
5917 case Mips::BEQC64: in checkTargetMatchPredicate()
5918 case Mips::BNEC64: in checkTargetMatchPredicate()
5919 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5920 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5922 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5923 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5928 case Mips::DINS: { in checkTargetMatchPredicate()
5937 case Mips::DINSM: in checkTargetMatchPredicate()
5938 case Mips::DINSU: { in checkTargetMatchPredicate()
5947 case Mips::DEXT: { in checkTargetMatchPredicate()
5956 case Mips::DEXTM: in checkTargetMatchPredicate()
5957 case Mips::DEXTU: { in checkTargetMatchPredicate()
5966 case Mips::CRC32B: case Mips::CRC32CB: in checkTargetMatchPredicate()
5967 case Mips::CRC32H: case Mips::CRC32CH: in checkTargetMatchPredicate()
5968 case Mips::CRC32W: case Mips::CRC32CW: in checkTargetMatchPredicate()
5969 case Mips::CRC32D: case Mips::CRC32CD: in checkTargetMatchPredicate()
5977 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) in checkTargetMatchPredicate()
6211 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) && in ConvertXWPOperands()
6399 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex); in getATReg()
6853 unsigned PrevReg = Mips::NoRegister; in parseRegisterList()
6868 if ((isGP64bit() && RegNo == Mips::RA_64) || in parseRegisterList()
6869 (!isGP64bit() && RegNo == Mips::RA)) { in parseRegisterList()
6874 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) || in parseRegisterList()
6875 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) && in parseRegisterList()
6886 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6887 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) || in parseRegisterList()
6888 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) in parseRegisterList()
6890 if (!(((RegNo == Mips::FP || RegNo == Mips::RA || in parseRegisterList()
6891 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) && in parseRegisterList()
6893 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 || in parseRegisterList()
6894 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) && in parseRegisterList()
6897 if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6898 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) || in parseRegisterList()
6899 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && isGP64bit()))) in parseRegisterList()
6987 // as tested in test/MC/Mips/mips64r6/valid.s. in areEqualRegs()
7209 setFeatureBits(Mips::FeatureMSA, "msa"); in parseSetMsaDirective()
7222 clearFeatureBits(Mips::FeatureMSA, "msa"); in parseSetNoMsaDirective()
7237 clearFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetNoDspDirective()
7252 clearFeatureBits(Mips::FeatureMips3D, "mips3d"); in parseSetNoMips3DDirective()
7267 setFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetMips16Directive()
7283 clearFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetNoMips16Directive()
7325 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetOddSPRegDirective()
7339 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetNoOddSPRegDirective()
7354 setFeatureBits(Mips::FeatureMT, "mt"); in parseSetMtDirective()
7370 clearFeatureBits(Mips::FeatureMT, "mt"); in parseSetNoMtDirective()
7387 clearFeatureBits(Mips::FeatureCRC, "crc"); in parseSetNoCRCDirective()
7404 clearFeatureBits(Mips::FeatureVirt, "virt"); in parseSetNoVirtDirective()
7421 clearFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetNoGINVDirective()
7471 setFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetSoftFloatDirective()
7482 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetHardFloatDirective()
7589 case Mips::FeatureMips3D: in parseSetFeature()
7590 setFeatureBits(Mips::FeatureMips3D, "mips3d"); in parseSetFeature()
7593 case Mips::FeatureDSP: in parseSetFeature()
7594 setFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetFeature()
7597 case Mips::FeatureDSPR2: in parseSetFeature()
7598 setFeatureBits(Mips::FeatureDSPR2, "dspr2"); in parseSetFeature()
7601 case Mips::FeatureMicroMips: in parseSetFeature()
7602 setFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseSetFeature()
7605 case Mips::FeatureMips1: in parseSetFeature()
7609 case Mips::FeatureMips2: in parseSetFeature()
7613 case Mips::FeatureMips3: in parseSetFeature()
7617 case Mips::FeatureMips4: in parseSetFeature()
7621 case Mips::FeatureMips5: in parseSetFeature()
7625 case Mips::FeatureMips32: in parseSetFeature()
7629 case Mips::FeatureMips32r2: in parseSetFeature()
7633 case Mips::FeatureMips32r3: in parseSetFeature()
7637 case Mips::FeatureMips32r5: in parseSetFeature()
7641 case Mips::FeatureMips32r6: in parseSetFeature()
7645 case Mips::FeatureMips64: in parseSetFeature()
7649 case Mips::FeatureMips64r2: in parseSetFeature()
7653 case Mips::FeatureMips64r3: in parseSetFeature()
7657 case Mips::FeatureMips64r5: in parseSetFeature()
7661 case Mips::FeatureMips64r6: in parseSetFeature()
7665 case Mips::FeatureCRC: in parseSetFeature()
7666 setFeatureBits(Mips::FeatureCRC, "crc"); in parseSetFeature()
7669 case Mips::FeatureVirt: in parseSetFeature()
7670 setFeatureBits(Mips::FeatureVirt, "virt"); in parseSetFeature()
7673 case Mips::FeatureGINV: in parseSetFeature()
7674 setFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetFeature()
7978 clearFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseDirectiveSet()
7988 return parseSetFeature(Mips::FeatureMicroMips); in parseDirectiveSet()
7993 return parseSetFeature(Mips::FeatureMips1); in parseDirectiveSet()
7995 return parseSetFeature(Mips::FeatureMips2); in parseDirectiveSet()
7997 return parseSetFeature(Mips::FeatureMips3); in parseDirectiveSet()
7999 return parseSetFeature(Mips::FeatureMips4); in parseDirectiveSet()
8001 return parseSetFeature(Mips::FeatureMips5); in parseDirectiveSet()
8003 return parseSetFeature(Mips::FeatureMips32); in parseDirectiveSet()
8005 return parseSetFeature(Mips::FeatureMips32r2); in parseDirectiveSet()
8007 return parseSetFeature(Mips::FeatureMips32r3); in parseDirectiveSet()
8009 return parseSetFeature(Mips::FeatureMips32r5); in parseDirectiveSet()
8011 return parseSetFeature(Mips::FeatureMips32r6); in parseDirectiveSet()
8013 return parseSetFeature(Mips::FeatureMips64); in parseDirectiveSet()
8015 return parseSetFeature(Mips::FeatureMips64r2); in parseDirectiveSet()
8017 return parseSetFeature(Mips::FeatureMips64r3); in parseDirectiveSet()
8019 return parseSetFeature(Mips::FeatureMips64r5); in parseDirectiveSet()
8025 return parseSetFeature(Mips::FeatureMips64r6); in parseDirectiveSet()
8028 return parseSetFeature(Mips::FeatureDSP); in parseDirectiveSet()
8030 return parseSetFeature(Mips::FeatureDSPR2); in parseDirectiveSet()
8034 return parseSetFeature(Mips::FeatureMips3D); in parseDirectiveSet()
8050 return parseSetFeature(Mips::FeatureCRC); in parseDirectiveSet()
8054 return parseSetFeature(Mips::FeatureVirt); in parseDirectiveSet()
8058 return parseSetFeature(Mips::FeatureGINV); in parseDirectiveSet()
8302 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
8309 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8325 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
8332 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8346 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
8353 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8365 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
8372 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8384 setModuleFeatureBits(Mips::FeatureMT, "mt"); in parseDirectiveModule()
8391 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8403 setModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
8410 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8422 clearModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
8429 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8441 setModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
8448 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8460 clearModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
8467 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8479 setModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
8486 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8498 clearModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
8505 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModule()
8549 // If generating ELF, don't do anything (the .MIPS.abiflags section gets in parseDirectiveModuleFP()
8579 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8580 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8582 setFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8583 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8605 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8606 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8608 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8609 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8614 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8615 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8617 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8618 setFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()