Lines Matching full:mips
29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
30 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
96 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
97 Opc = Mips::CFC1; in copyPhysReg()
98 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()
99 Opc = Mips::MFC1; in copyPhysReg()
100 else if (Mips::HI32RegClass.contains(SrcReg)) { in copyPhysReg()
101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
103 } else if (Mips::LO32RegClass.contains(SrcReg)) { in copyPhysReg()
104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) in copyPhysReg()
107 Opc = Mips::MFHI_DSP; in copyPhysReg()
108 else if (Mips::LO32DSPRegClass.contains(SrcReg)) in copyPhysReg()
109 Opc = Mips::MFLO_DSP; in copyPhysReg()
110 else if (Mips::DSPCCRegClass.contains(SrcReg)) { in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
115 else if (Mips::MSACtrlRegClass.contains(SrcReg)) in copyPhysReg()
116 Opc = Mips::CFCMSA; in copyPhysReg()
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
120 Opc = Mips::CTC1; in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
122 Opc = Mips::MTC1; in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
128 Opc = Mips::MTHI_DSP; in copyPhysReg()
129 else if (Mips::LO32DSPRegClass.contains(DestReg)) in copyPhysReg()
130 Opc = Mips::MTLO_DSP; in copyPhysReg()
131 else if (Mips::DSPCCRegClass.contains(DestReg)) { in copyPhysReg()
132 BuildMI(MBB, I, DL, get(Mips::WRDSP)) in copyPhysReg()
136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { in copyPhysReg()
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) in copyPhysReg()
143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
144 Opc = Mips::FMOV_S; in copyPhysReg()
145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
146 Opc = Mips::FMOV_D32; in copyPhysReg()
147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
148 Opc = Mips::FMOV_D64; in copyPhysReg()
149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
152 else if (Mips::HI64RegClass.contains(SrcReg)) in copyPhysReg()
153 Opc = Mips::MFHI64, SrcReg = 0; in copyPhysReg()
154 else if (Mips::LO64RegClass.contains(SrcReg)) in copyPhysReg()
155 Opc = Mips::MFLO64, SrcReg = 0; in copyPhysReg()
156 else if (Mips::FGR64RegClass.contains(SrcReg)) in copyPhysReg()
157 Opc = Mips::DMFC1; in copyPhysReg()
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
160 if (Mips::HI64RegClass.contains(DestReg)) in copyPhysReg()
161 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
162 else if (Mips::LO64RegClass.contains(DestReg)) in copyPhysReg()
163 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
164 else if (Mips::FGR64RegClass.contains(DestReg)) in copyPhysReg()
165 Opc = Mips::DMTC1; in copyPhysReg()
167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg in copyPhysReg()
168 if (Mips::MSA128BRegClass.contains(SrcReg)) in copyPhysReg()
169 Opc = Mips::MOVE_V; in copyPhysReg()
190 case Mips::OR_MM: in isORCopyInst()
191 case Mips::OR: in isORCopyInst()
192 if (MI.getOperand(2).getReg() == Mips::ZERO) in isORCopyInst()
195 case Mips::OR64: in isORCopyInst()
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64) in isORCopyInst()
203 /// We check for the common case of 'or', as it's MIPS' preferred instruction
205 /// Other move instructions for MIPS are directly identifiable.
224 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
225 Opc = Mips::SW; in storeRegToStack()
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
227 Opc = Mips::SD; in storeRegToStack()
228 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
229 Opc = Mips::STORE_ACC64; in storeRegToStack()
230 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
231 Opc = Mips::STORE_ACC64DSP; in storeRegToStack()
232 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
233 Opc = Mips::STORE_ACC128; in storeRegToStack()
234 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
235 Opc = Mips::STORE_CCOND_DSP; in storeRegToStack()
236 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
237 Opc = Mips::SWC1; in storeRegToStack()
238 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
239 Opc = Mips::SDC1; in storeRegToStack()
240 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
241 Opc = Mips::SDC164; in storeRegToStack()
243 Opc = Mips::ST_B; in storeRegToStack()
246 Opc = Mips::ST_H; in storeRegToStack()
249 Opc = Mips::ST_W; in storeRegToStack()
252 Opc = Mips::ST_D; in storeRegToStack()
253 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
254 Opc = Mips::SW; in storeRegToStack()
255 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in storeRegToStack()
256 Opc = Mips::SD; in storeRegToStack()
257 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in storeRegToStack()
258 Opc = Mips::SW; in storeRegToStack()
259 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in storeRegToStack()
260 Opc = Mips::SD; in storeRegToStack()
261 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in storeRegToStack()
262 Opc = Mips::SWDSP; in storeRegToStack()
268 if (Mips::HI32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
269 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
270 SrcReg = Mips::K0; in storeRegToStack()
271 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { in storeRegToStack()
272 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); in storeRegToStack()
273 SrcReg = Mips::K0_64; in storeRegToStack()
274 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { in storeRegToStack()
275 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
276 SrcReg = Mips::K0; in storeRegToStack()
277 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { in storeRegToStack()
278 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); in storeRegToStack()
279 SrcReg = Mips::K0_64; in storeRegToStack()
299 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || in loadRegFromStack()
300 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); in loadRegFromStack()
302 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
303 Opc = Mips::LW; in loadRegFromStack()
304 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
305 Opc = Mips::LD; in loadRegFromStack()
306 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
307 Opc = Mips::LOAD_ACC64; in loadRegFromStack()
308 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in loadRegFromStack()
309 Opc = Mips::LOAD_ACC64DSP; in loadRegFromStack()
310 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in loadRegFromStack()
311 Opc = Mips::LOAD_ACC128; in loadRegFromStack()
312 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in loadRegFromStack()
313 Opc = Mips::LOAD_CCOND_DSP; in loadRegFromStack()
314 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
315 Opc = Mips::LWC1; in loadRegFromStack()
316 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
317 Opc = Mips::LDC1; in loadRegFromStack()
318 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
319 Opc = Mips::LDC164; in loadRegFromStack()
321 Opc = Mips::LD_B; in loadRegFromStack()
324 Opc = Mips::LD_H; in loadRegFromStack()
327 Opc = Mips::LD_W; in loadRegFromStack()
330 Opc = Mips::LD_D; in loadRegFromStack()
331 else if (Mips::HI32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
332 Opc = Mips::LW; in loadRegFromStack()
333 else if (Mips::HI64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
334 Opc = Mips::LD; in loadRegFromStack()
335 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
336 Opc = Mips::LW; in loadRegFromStack()
337 else if (Mips::LO64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
338 Opc = Mips::LD; in loadRegFromStack()
339 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) in loadRegFromStack()
340 Opc = Mips::LWDSP; in loadRegFromStack()
352 unsigned Reg = Mips::K0; in loadRegFromStack()
353 unsigned LdOp = Mips::MTLO; in loadRegFromStack()
354 if (DestReg == Mips::HI0) in loadRegFromStack()
355 LdOp = Mips::MTHI; in loadRegFromStack()
358 Reg = Mips::K0_64; in loadRegFromStack()
359 if (DestReg == Mips::HI0_64) in loadRegFromStack()
360 LdOp = Mips::MTHI64; in loadRegFromStack()
362 LdOp = Mips::MTLO64; in loadRegFromStack()
381 case Mips::RetRA: in expandPostRAPseudo()
384 case Mips::ERet: in expandPostRAPseudo()
387 case Mips::PseudoMFHI: in expandPostRAPseudo()
388 expandPseudoMFHiLo(MBB, MI, Mips::MFHI); in expandPostRAPseudo()
390 case Mips::PseudoMFHI_MM: in expandPostRAPseudo()
391 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM); in expandPostRAPseudo()
393 case Mips::PseudoMFLO: in expandPostRAPseudo()
394 expandPseudoMFHiLo(MBB, MI, Mips::MFLO); in expandPostRAPseudo()
396 case Mips::PseudoMFLO_MM: in expandPostRAPseudo()
397 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM); in expandPostRAPseudo()
399 case Mips::PseudoMFHI64: in expandPostRAPseudo()
400 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); in expandPostRAPseudo()
402 case Mips::PseudoMFLO64: in expandPostRAPseudo()
403 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); in expandPostRAPseudo()
405 case Mips::PseudoMTLOHI: in expandPostRAPseudo()
406 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); in expandPostRAPseudo()
408 case Mips::PseudoMTLOHI64: in expandPostRAPseudo()
409 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); in expandPostRAPseudo()
411 case Mips::PseudoMTLOHI_DSP: in expandPostRAPseudo()
412 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); in expandPostRAPseudo()
414 case Mips::PseudoMTLOHI_MM: in expandPostRAPseudo()
415 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false); in expandPostRAPseudo()
417 case Mips::PseudoCVT_S_W: in expandPostRAPseudo()
418 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
420 case Mips::PseudoCVT_D32_W: in expandPostRAPseudo()
421 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; in expandPostRAPseudo()
422 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
424 case Mips::PseudoCVT_S_L: in expandPostRAPseudo()
425 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
427 case Mips::PseudoCVT_D64_W: in expandPostRAPseudo()
428 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; in expandPostRAPseudo()
429 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
431 case Mips::PseudoCVT_D64_L: in expandPostRAPseudo()
432 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
434 case Mips::BuildPairF64: in expandPostRAPseudo()
437 case Mips::BuildPairF64_64: in expandPostRAPseudo()
440 case Mips::ExtractElementF64: in expandPostRAPseudo()
443 case Mips::ExtractElementF64_64: in expandPostRAPseudo()
446 case Mips::MIPSeh_return32: in expandPostRAPseudo()
447 case Mips::MIPSeh_return64: in expandPostRAPseudo()
457 /// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp).
462 case Mips::BBIT0: in isBranchWithImm()
463 case Mips::BBIT1: in isBranchWithImm()
464 case Mips::BBIT032: in isBranchWithImm()
465 case Mips::BBIT132: in isBranchWithImm()
475 case Mips::BEQ: return Mips::BNE; in getOppositeBranchOpc()
476 case Mips::BEQ_MM: return Mips::BNE_MM; in getOppositeBranchOpc()
477 case Mips::BNE: return Mips::BEQ; in getOppositeBranchOpc()
478 case Mips::BNE_MM: return Mips::BEQ_MM; in getOppositeBranchOpc()
479 case Mips::BGTZ: return Mips::BLEZ; in getOppositeBranchOpc()
480 case Mips::BGEZ: return Mips::BLTZ; in getOppositeBranchOpc()
481 case Mips::BLTZ: return Mips::BGEZ; in getOppositeBranchOpc()
482 case Mips::BLEZ: return Mips::BGTZ; in getOppositeBranchOpc()
483 case Mips::BGTZ_MM: return Mips::BLEZ_MM; in getOppositeBranchOpc()
484 case Mips::BGEZ_MM: return Mips::BLTZ_MM; in getOppositeBranchOpc()
485 case Mips::BLTZ_MM: return Mips::BGEZ_MM; in getOppositeBranchOpc()
486 case Mips::BLEZ_MM: return Mips::BGTZ_MM; in getOppositeBranchOpc()
487 case Mips::BEQ64: return Mips::BNE64; in getOppositeBranchOpc()
488 case Mips::BNE64: return Mips::BEQ64; in getOppositeBranchOpc()
489 case Mips::BGTZ64: return Mips::BLEZ64; in getOppositeBranchOpc()
490 case Mips::BGEZ64: return Mips::BLTZ64; in getOppositeBranchOpc()
491 case Mips::BLTZ64: return Mips::BGEZ64; in getOppositeBranchOpc()
492 case Mips::BLEZ64: return Mips::BGTZ64; in getOppositeBranchOpc()
493 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
494 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
495 case Mips::BC1T_MM: return Mips::BC1F_MM; in getOppositeBranchOpc()
496 case Mips::BC1F_MM: return Mips::BC1T_MM; in getOppositeBranchOpc()
497 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM; in getOppositeBranchOpc()
498 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM; in getOppositeBranchOpc()
499 case Mips::BEQZC_MM: return Mips::BNEZC_MM; in getOppositeBranchOpc()
500 case Mips::BNEZC_MM: return Mips::BEQZC_MM; in getOppositeBranchOpc()
501 case Mips::BEQZC: return Mips::BNEZC; in getOppositeBranchOpc()
502 case Mips::BNEZC: return Mips::BEQZC; in getOppositeBranchOpc()
503 case Mips::BLEZC: return Mips::BGTZC; in getOppositeBranchOpc()
504 case Mips::BGEZC: return Mips::BLTZC; in getOppositeBranchOpc()
505 case Mips::BGEC: return Mips::BLTC; in getOppositeBranchOpc()
506 case Mips::BGTZC: return Mips::BLEZC; in getOppositeBranchOpc()
507 case Mips::BLTZC: return Mips::BGEZC; in getOppositeBranchOpc()
508 case Mips::BLTC: return Mips::BGEC; in getOppositeBranchOpc()
509 case Mips::BGEUC: return Mips::BLTUC; in getOppositeBranchOpc()
510 case Mips::BLTUC: return Mips::BGEUC; in getOppositeBranchOpc()
511 case Mips::BEQC: return Mips::BNEC; in getOppositeBranchOpc()
512 case Mips::BNEC: return Mips::BEQC; in getOppositeBranchOpc()
513 case Mips::BC1EQZ: return Mips::BC1NEZ; in getOppositeBranchOpc()
514 case Mips::BC1NEZ: return Mips::BC1EQZ; in getOppositeBranchOpc()
515 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; in getOppositeBranchOpc()
516 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; in getOppositeBranchOpc()
517 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; in getOppositeBranchOpc()
518 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; in getOppositeBranchOpc()
519 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6; in getOppositeBranchOpc()
520 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; in getOppositeBranchOpc()
521 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; in getOppositeBranchOpc()
522 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6; in getOppositeBranchOpc()
523 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6; in getOppositeBranchOpc()
524 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6; in getOppositeBranchOpc()
525 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; in getOppositeBranchOpc()
526 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; in getOppositeBranchOpc()
527 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6; in getOppositeBranchOpc()
528 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6; in getOppositeBranchOpc()
529 case Mips::BEQZC64: return Mips::BNEZC64; in getOppositeBranchOpc()
530 case Mips::BNEZC64: return Mips::BEQZC64; in getOppositeBranchOpc()
531 case Mips::BEQC64: return Mips::BNEC64; in getOppositeBranchOpc()
532 case Mips::BNEC64: return Mips::BEQC64; in getOppositeBranchOpc()
533 case Mips::BGEC64: return Mips::BLTC64; in getOppositeBranchOpc()
534 case Mips::BGEUC64: return Mips::BLTUC64; in getOppositeBranchOpc()
535 case Mips::BLTC64: return Mips::BGEC64; in getOppositeBranchOpc()
536 case Mips::BLTUC64: return Mips::BGEUC64; in getOppositeBranchOpc()
537 case Mips::BGTZC64: return Mips::BLEZC64; in getOppositeBranchOpc()
538 case Mips::BGEZC64: return Mips::BLTZC64; in getOppositeBranchOpc()
539 case Mips::BLTZC64: return Mips::BGEZC64; in getOppositeBranchOpc()
540 case Mips::BLEZC64: return Mips::BGTZC64; in getOppositeBranchOpc()
541 case Mips::BBIT0: return Mips::BBIT1; in getOppositeBranchOpc()
542 case Mips::BBIT1: return Mips::BBIT0; in getOppositeBranchOpc()
543 case Mips::BBIT032: return Mips::BBIT132; in getOppositeBranchOpc()
544 case Mips::BBIT132: return Mips::BBIT032; in getOppositeBranchOpc()
545 case Mips::BZ_B: return Mips::BNZ_B; in getOppositeBranchOpc()
546 case Mips::BZ_H: return Mips::BNZ_H; in getOppositeBranchOpc()
547 case Mips::BZ_W: return Mips::BNZ_W; in getOppositeBranchOpc()
548 case Mips::BZ_D: return Mips::BNZ_D; in getOppositeBranchOpc()
549 case Mips::BZ_V: return Mips::BNZ_V; in getOppositeBranchOpc()
550 case Mips::BNZ_B: return Mips::BZ_B; in getOppositeBranchOpc()
551 case Mips::BNZ_H: return Mips::BZ_H; in getOppositeBranchOpc()
552 case Mips::BNZ_W: return Mips::BZ_W; in getOppositeBranchOpc()
553 case Mips::BNZ_D: return Mips::BZ_D; in getOppositeBranchOpc()
554 case Mips::BNZ_V: return Mips::BZ_V; in getOppositeBranchOpc()
595 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; in loadImmediate()
596 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate()
598 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
630 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || in getAnalyzableBrOpc()
631 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || in getAnalyzableBrOpc()
632 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || in getAnalyzableBrOpc()
633 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || in getAnalyzableBrOpc()
634 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || in getAnalyzableBrOpc()
635 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || in getAnalyzableBrOpc()
636 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || in getAnalyzableBrOpc()
637 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || in getAnalyzableBrOpc()
638 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || in getAnalyzableBrOpc()
639 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || in getAnalyzableBrOpc()
640 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || in getAnalyzableBrOpc()
641 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || in getAnalyzableBrOpc()
642 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || in getAnalyzableBrOpc()
643 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || in getAnalyzableBrOpc()
644 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || in getAnalyzableBrOpc()
645 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || in getAnalyzableBrOpc()
646 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || in getAnalyzableBrOpc()
647 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || in getAnalyzableBrOpc()
648 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || in getAnalyzableBrOpc()
649 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || in getAnalyzableBrOpc()
650 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || in getAnalyzableBrOpc()
651 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || in getAnalyzableBrOpc()
652 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || in getAnalyzableBrOpc()
653 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; in getAnalyzableBrOpc()
661 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) in expandRetRA()
662 .addReg(Mips::RA_64, RegState::Undef); in expandRetRA()
664 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)) in expandRetRA()
665 .addReg(Mips::RA, RegState::Undef); in expandRetRA()
676 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); in expandERet()
717 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
718 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
742 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
745 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
764 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload in expandExtractElementF64()
772 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { in expandExtractElementF64()
786 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
787 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
791 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
799 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
818 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload in expandBuildPairF64()
826 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
842 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) in expandBuildPairF64()
843 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), in expandBuildPairF64()
850 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
861 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; in expandEhReturn()
862 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; in expandEhReturn()
863 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; in expandEhReturn()
864 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in expandEhReturn()