Lines Matching full:mips
1 //===------ SemaMIPS.cpp -------- MIPS target-specific routines -----------===//
9 // This file implements semantic analysis functions specific to MIPS.
34 if (Mips::BI__builtin_mips_addu_qb <= BuiltinID && in CheckMipsBuiltinCpu()
35 BuiltinID <= Mips::BI__builtin_mips_lwx) { in CheckMipsBuiltinCpu()
40 if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID && in CheckMipsBuiltinCpu()
41 BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) { in CheckMipsBuiltinCpu()
47 if (Mips::BI__builtin_msa_add_a_b <= BuiltinID && in CheckMipsBuiltinCpu()
48 BuiltinID <= Mips::BI__builtin_msa_xori_b) { in CheckMipsBuiltinCpu()
69 case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
70 case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
71 case Mips::BI__builtin_mips_append: i = 2; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
72 case Mips::BI__builtin_mips_balign: i = 2; l = 0; u = 3; break; in CheckMipsBuiltinArgument()
73 case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
74 case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
75 case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
79 case Mips::BI__builtin_msa_bclri_b: in CheckMipsBuiltinArgument()
80 case Mips::BI__builtin_msa_bnegi_b: in CheckMipsBuiltinArgument()
81 case Mips::BI__builtin_msa_bseti_b: in CheckMipsBuiltinArgument()
82 case Mips::BI__builtin_msa_sat_s_b: in CheckMipsBuiltinArgument()
83 case Mips::BI__builtin_msa_sat_u_b: in CheckMipsBuiltinArgument()
84 case Mips::BI__builtin_msa_slli_b: in CheckMipsBuiltinArgument()
85 case Mips::BI__builtin_msa_srai_b: in CheckMipsBuiltinArgument()
86 case Mips::BI__builtin_msa_srari_b: in CheckMipsBuiltinArgument()
87 case Mips::BI__builtin_msa_srli_b: in CheckMipsBuiltinArgument()
88 case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7; break; in CheckMipsBuiltinArgument()
89 case Mips::BI__builtin_msa_binsli_b: in CheckMipsBuiltinArgument()
90 case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7; break; in CheckMipsBuiltinArgument()
92 case Mips::BI__builtin_msa_bclri_h: in CheckMipsBuiltinArgument()
93 case Mips::BI__builtin_msa_bnegi_h: in CheckMipsBuiltinArgument()
94 case Mips::BI__builtin_msa_bseti_h: in CheckMipsBuiltinArgument()
95 case Mips::BI__builtin_msa_sat_s_h: in CheckMipsBuiltinArgument()
96 case Mips::BI__builtin_msa_sat_u_h: in CheckMipsBuiltinArgument()
97 case Mips::BI__builtin_msa_slli_h: in CheckMipsBuiltinArgument()
98 case Mips::BI__builtin_msa_srai_h: in CheckMipsBuiltinArgument()
99 case Mips::BI__builtin_msa_srari_h: in CheckMipsBuiltinArgument()
100 case Mips::BI__builtin_msa_srli_h: in CheckMipsBuiltinArgument()
101 case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15; break; in CheckMipsBuiltinArgument()
102 case Mips::BI__builtin_msa_binsli_h: in CheckMipsBuiltinArgument()
103 case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15; break; in CheckMipsBuiltinArgument()
107 case Mips::BI__builtin_msa_cfcmsa: in CheckMipsBuiltinArgument()
108 case Mips::BI__builtin_msa_ctcmsa: i = 0; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
109 case Mips::BI__builtin_msa_clei_u_b: in CheckMipsBuiltinArgument()
110 case Mips::BI__builtin_msa_clei_u_h: in CheckMipsBuiltinArgument()
111 case Mips::BI__builtin_msa_clei_u_w: in CheckMipsBuiltinArgument()
112 case Mips::BI__builtin_msa_clei_u_d: in CheckMipsBuiltinArgument()
113 case Mips::BI__builtin_msa_clti_u_b: in CheckMipsBuiltinArgument()
114 case Mips::BI__builtin_msa_clti_u_h: in CheckMipsBuiltinArgument()
115 case Mips::BI__builtin_msa_clti_u_w: in CheckMipsBuiltinArgument()
116 case Mips::BI__builtin_msa_clti_u_d: in CheckMipsBuiltinArgument()
117 case Mips::BI__builtin_msa_maxi_u_b: in CheckMipsBuiltinArgument()
118 case Mips::BI__builtin_msa_maxi_u_h: in CheckMipsBuiltinArgument()
119 case Mips::BI__builtin_msa_maxi_u_w: in CheckMipsBuiltinArgument()
120 case Mips::BI__builtin_msa_maxi_u_d: in CheckMipsBuiltinArgument()
121 case Mips::BI__builtin_msa_mini_u_b: in CheckMipsBuiltinArgument()
122 case Mips::BI__builtin_msa_mini_u_h: in CheckMipsBuiltinArgument()
123 case Mips::BI__builtin_msa_mini_u_w: in CheckMipsBuiltinArgument()
124 case Mips::BI__builtin_msa_mini_u_d: in CheckMipsBuiltinArgument()
125 case Mips::BI__builtin_msa_addvi_b: in CheckMipsBuiltinArgument()
126 case Mips::BI__builtin_msa_addvi_h: in CheckMipsBuiltinArgument()
127 case Mips::BI__builtin_msa_addvi_w: in CheckMipsBuiltinArgument()
128 case Mips::BI__builtin_msa_addvi_d: in CheckMipsBuiltinArgument()
129 case Mips::BI__builtin_msa_bclri_w: in CheckMipsBuiltinArgument()
130 case Mips::BI__builtin_msa_bnegi_w: in CheckMipsBuiltinArgument()
131 case Mips::BI__builtin_msa_bseti_w: in CheckMipsBuiltinArgument()
132 case Mips::BI__builtin_msa_sat_s_w: in CheckMipsBuiltinArgument()
133 case Mips::BI__builtin_msa_sat_u_w: in CheckMipsBuiltinArgument()
134 case Mips::BI__builtin_msa_slli_w: in CheckMipsBuiltinArgument()
135 case Mips::BI__builtin_msa_srai_w: in CheckMipsBuiltinArgument()
136 case Mips::BI__builtin_msa_srari_w: in CheckMipsBuiltinArgument()
137 case Mips::BI__builtin_msa_srli_w: in CheckMipsBuiltinArgument()
138 case Mips::BI__builtin_msa_srlri_w: in CheckMipsBuiltinArgument()
139 case Mips::BI__builtin_msa_subvi_b: in CheckMipsBuiltinArgument()
140 case Mips::BI__builtin_msa_subvi_h: in CheckMipsBuiltinArgument()
141 case Mips::BI__builtin_msa_subvi_w: in CheckMipsBuiltinArgument()
142 case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
143 case Mips::BI__builtin_msa_binsli_w: in CheckMipsBuiltinArgument()
144 case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31; break; in CheckMipsBuiltinArgument()
146 case Mips::BI__builtin_msa_bclri_d: in CheckMipsBuiltinArgument()
147 case Mips::BI__builtin_msa_bnegi_d: in CheckMipsBuiltinArgument()
148 case Mips::BI__builtin_msa_bseti_d: in CheckMipsBuiltinArgument()
149 case Mips::BI__builtin_msa_sat_s_d: in CheckMipsBuiltinArgument()
150 case Mips::BI__builtin_msa_sat_u_d: in CheckMipsBuiltinArgument()
151 case Mips::BI__builtin_msa_slli_d: in CheckMipsBuiltinArgument()
152 case Mips::BI__builtin_msa_srai_d: in CheckMipsBuiltinArgument()
153 case Mips::BI__builtin_msa_srari_d: in CheckMipsBuiltinArgument()
154 case Mips::BI__builtin_msa_srli_d: in CheckMipsBuiltinArgument()
155 case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
156 case Mips::BI__builtin_msa_binsli_d: in CheckMipsBuiltinArgument()
157 case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63; break; in CheckMipsBuiltinArgument()
159 case Mips::BI__builtin_msa_ceqi_b: in CheckMipsBuiltinArgument()
160 case Mips::BI__builtin_msa_ceqi_h: in CheckMipsBuiltinArgument()
161 case Mips::BI__builtin_msa_ceqi_w: in CheckMipsBuiltinArgument()
162 case Mips::BI__builtin_msa_ceqi_d: in CheckMipsBuiltinArgument()
163 case Mips::BI__builtin_msa_clti_s_b: in CheckMipsBuiltinArgument()
164 case Mips::BI__builtin_msa_clti_s_h: in CheckMipsBuiltinArgument()
165 case Mips::BI__builtin_msa_clti_s_w: in CheckMipsBuiltinArgument()
166 case Mips::BI__builtin_msa_clti_s_d: in CheckMipsBuiltinArgument()
167 case Mips::BI__builtin_msa_clei_s_b: in CheckMipsBuiltinArgument()
168 case Mips::BI__builtin_msa_clei_s_h: in CheckMipsBuiltinArgument()
169 case Mips::BI__builtin_msa_clei_s_w: in CheckMipsBuiltinArgument()
170 case Mips::BI__builtin_msa_clei_s_d: in CheckMipsBuiltinArgument()
171 case Mips::BI__builtin_msa_maxi_s_b: in CheckMipsBuiltinArgument()
172 case Mips::BI__builtin_msa_maxi_s_h: in CheckMipsBuiltinArgument()
173 case Mips::BI__builtin_msa_maxi_s_w: in CheckMipsBuiltinArgument()
174 case Mips::BI__builtin_msa_maxi_s_d: in CheckMipsBuiltinArgument()
175 case Mips::BI__builtin_msa_mini_s_b: in CheckMipsBuiltinArgument()
176 case Mips::BI__builtin_msa_mini_s_h: in CheckMipsBuiltinArgument()
177 case Mips::BI__builtin_msa_mini_s_w: in CheckMipsBuiltinArgument()
178 case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15; break; in CheckMipsBuiltinArgument()
180 case Mips::BI__builtin_msa_andi_b: in CheckMipsBuiltinArgument()
181 case Mips::BI__builtin_msa_nori_b: in CheckMipsBuiltinArgument()
182 case Mips::BI__builtin_msa_ori_b: in CheckMipsBuiltinArgument()
183 case Mips::BI__builtin_msa_shf_b: in CheckMipsBuiltinArgument()
184 case Mips::BI__builtin_msa_shf_h: in CheckMipsBuiltinArgument()
185 case Mips::BI__builtin_msa_shf_w: in CheckMipsBuiltinArgument()
186 case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255; break; in CheckMipsBuiltinArgument()
187 case Mips::BI__builtin_msa_bseli_b: in CheckMipsBuiltinArgument()
188 case Mips::BI__builtin_msa_bmnzi_b: in CheckMipsBuiltinArgument()
189 case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255; break; in CheckMipsBuiltinArgument()
192 case Mips::BI__builtin_msa_copy_s_b: in CheckMipsBuiltinArgument()
193 case Mips::BI__builtin_msa_copy_u_b: in CheckMipsBuiltinArgument()
194 case Mips::BI__builtin_msa_insve_b: in CheckMipsBuiltinArgument()
195 case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break; in CheckMipsBuiltinArgument()
196 case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break; in CheckMipsBuiltinArgument()
198 case Mips::BI__builtin_msa_copy_s_h: in CheckMipsBuiltinArgument()
199 case Mips::BI__builtin_msa_copy_u_h: in CheckMipsBuiltinArgument()
200 case Mips::BI__builtin_msa_insve_h: in CheckMipsBuiltinArgument()
201 case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break; in CheckMipsBuiltinArgument()
202 case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break; in CheckMipsBuiltinArgument()
204 case Mips::BI__builtin_msa_copy_s_w: in CheckMipsBuiltinArgument()
205 case Mips::BI__builtin_msa_copy_u_w: in CheckMipsBuiltinArgument()
206 case Mips::BI__builtin_msa_insve_w: in CheckMipsBuiltinArgument()
207 case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break; in CheckMipsBuiltinArgument()
208 case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break; in CheckMipsBuiltinArgument()
210 case Mips::BI__builtin_msa_copy_s_d: in CheckMipsBuiltinArgument()
211 case Mips::BI__builtin_msa_copy_u_d: in CheckMipsBuiltinArgument()
212 case Mips::BI__builtin_msa_insve_d: in CheckMipsBuiltinArgument()
213 case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break; in CheckMipsBuiltinArgument()
214 case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break; in CheckMipsBuiltinArgument()
217 case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break; in CheckMipsBuiltinArgument()
218 case Mips::BI__builtin_msa_ldi_h: in CheckMipsBuiltinArgument()
219 case Mips::BI__builtin_msa_ldi_w: in CheckMipsBuiltinArgument()
220 case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break; in CheckMipsBuiltinArgument()
221 case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1; break; in CheckMipsBuiltinArgument()
222 case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2; break; in CheckMipsBuiltinArgument()
223 case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4; break; in CheckMipsBuiltinArgument()
224 case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8; break; in CheckMipsBuiltinArgument()
225 case Mips::BI__builtin_msa_ldr_d: i = 1; l = -4096; u = 4088; m = 8; break; in CheckMipsBuiltinArgument()
226 case Mips::BI__builtin_msa_ldr_w: i = 1; l = -2048; u = 2044; m = 4; break; in CheckMipsBuiltinArgument()
227 case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1; break; in CheckMipsBuiltinArgument()
228 case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2; break; in CheckMipsBuiltinArgument()
229 case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4; break; in CheckMipsBuiltinArgument()
230 case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8; break; in CheckMipsBuiltinArgument()
231 case Mips::BI__builtin_msa_str_d: i = 2; l = -4096; u = 4088; m = 8; break; in CheckMipsBuiltinArgument()
232 case Mips::BI__builtin_msa_str_w: i = 2; l = -2048; u = 2044; m = 4; break; in CheckMipsBuiltinArgument()
257 // Semantic checks for a function with the 'interrupt' attribute for MIPS: in handleInterruptAttr()
274 << /*MIPS*/ 0 << 0; in handleInterruptAttr()
280 << /*MIPS*/ 0 << 1; in handleInterruptAttr()