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/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Memory devices
6 menuconfig MEMORY config
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
15 if MEMORY
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
31 controller, say Y or M here.
[all …]
/linux/drivers/memory/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
21 This driver is for the External Memory Controller (EMC) found on
23 This driver is required to change memory timings / clock rate for
24 external memory.
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
33 This driver is for the External Memory Controller (EMC) found on
35 This driver is required to change memory timings / clock rate for
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnuvoton,npcm-memory-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Memory Controller
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
[all …]
H A Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
[all …]
H A Dnvidia,tegra20-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
[all …]
H A Dxlnx,versal-ddrmc-edac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
[all …]
H A Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
15 working with the memory devices supporting up to (LP)DDR4 protocol. It can
17 16-bits or 32-bits or 64-bits wide.
[all …]
H A Dsamsung,exynos5422-dmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
9 Controller device
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Lukasz Luba <lukasz.luba@arm.com>
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
17 DRAM memory chips are connected. The driver is to monitor the controller in
[all …]
H A Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
[all …]
/linux/include/uapi/linux/
H A Dum_timetravel.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (C) 2019 - 2023 Intel Corporation
10 * struct um_timetravel_msg - UM time travel message
14 * This is the message passed between the host (user-mode Linux instance)
30 * @seq: sequence number for the message - shall be reflected in
46 * enum um_timetravel_shared_mem_fds - fds sent in ACK message for START message
50 * @UM_TIMETRAVEL_SHARED_MEMFD: Index of the shared memory file
63 * enum um_timetravel_start_ack - ack-time mask for start message
67 * @UM_TIMETRAVEL_START_ACK_ID: client ID that controller allocated.
73 * enum um_timetravel_ops - Operation codes
[all …]
/linux/drivers/mmc/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
18 tristate "Sunplus SP7021 MMC Controller"
37 bool "Qualcomm Data Mover for SD Card Controller"
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
48 bool "STMicroelectronics STM32 SDMMC Controller"
52 This selects the STMicroelectronics STM32 SDMMC host controller.
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
[all …]
/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linusw@kernel.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
[all …]
H A Dmpc512x-dma.txt1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
4 blocks of memory contents between memory and peripherals or
5 from memory to memory.
7 Refer to "Generic DMA Controller and DMA request bindings" in
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
14 is described in interrupt-controller/interrupts.txt file.
15 - #dma-cells: the length of the DMA specifier, must be <1>.
[all …]
/linux/Documentation/nvme/
H A Dnvme-pci-endpoint-target.rst1 .. SPDX-License-Identifier: GPL-2.0
9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller
10 using an NVMe fabrics target controller configured with the PCI transport type.
16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a
17 regular M.2 SSD. The target controller is created in the same manner as when
18 using NVMe over fabrics: the controller represents the interface to an NVMe
22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe
23 TCP host controller).
51 data buffer is transferred from the host into a local memory buffer before
53 memory buffer is allocated to execute the command and the content of that
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-devices-edac3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
14 Contact: linux-edac@vger.kernel.org
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
27 Contact: linux-edac@vger.kernel.org
28 Description: This attribute file displays, in count of megabytes, of memory
29 that this memory controller manages.
33 Contact: linux-edac@vger.kernel.org
[all …]
/linux/drivers/memory/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
5 Support for the Memory Controller (MC) devices found on
11 tristate "Exynos5422 Dynamic Memory Controller driver"
17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
18 Controller). The driver provides support for Dynamic Voltage and
21 based on DT memory information.
25 bool "Exynos SROM controller driver" if COMPILE_TEST
28 This adds driver for Samsung Exynos SoC SROM controller. The driver
31 is provided, the driver enables support for external memory
/linux/drivers/edac/
H A Dmpc85xx_edac.c2 * Freescale MPC85xx Memory Controller kernel module
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
52 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
55 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
59 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
67 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
71 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
[all …]
/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
19 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
72 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD…
115 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
120 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
126 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM …
[all …]
/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt7622-wed.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The mediatek wireless ethernet dispatch controller can be configured to
21 - enum:
22 - mediatek,mt7622-wed
[all …]
/linux/include/linux/
H A Dedac.h6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
99 * fatal (maybe it is on an unused memory area,
100 * or the memory controller could recover from
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
6 of the EMIF IP and memory parts attached to it. Certain revisions
7 of the EMIF controller also contain optional ECC support, which
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
[all …]
/linux/drivers/dma/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "MediaTek High-Speed DMA controller support"
9 Enable support for High-Speed DMA controller on MediaTek
12 This controller provides the channels which is dedicated to
13 memory-to-memory transfer to offload from CPU through ring-
17 tristate "MediaTek Command-Queue DMA controller support"
23 Enable support for Command-Queue DMA controller on MediaTek
26 This controller provides the channels which is dedicated to
27 memory-to-memory transfer to offload from CPU.

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