Lines Matching +full:memory +full:- +full:controller
1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
12 machine, expose memory ranges as BARs, and perform DMA. They also support
13 scratchpads, which are areas of memory within the NTB that are accessible
22 controller are routed to the other EP controller. Once PCI NTB function
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
55 5) Memory Window (MW)
59 --------------
64 Control/Status Registers for configuring the Endpoint Controller. Host can
68 scratchpad offset and number of memory windows to the host using this region.
72 .. code-block:: text
74 +------------------------+
76 +------------------------+
78 +------------------------+
80 +------------------------+
82 +------------------------+
84 +------------------------+
86 +------------------------+
88 +------------------------+
89 | NO OF MEMORY WINDOW |
90 +------------------------+
91 | MEMORY WINDOW1 OFFSET |
92 +------------------------+
94 +------------------------+
96 +------------------------+
98 +------------------------+
100 +------------------------+
102 +------------------------+
104 +------------------------+
106 +------------------------+
115 MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
118 to the MSI/MSI-X address programmed by the host. The ARGUMENT
120 lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
122 CMD_CONFIGURE_MW (0x2): Command to configure memory window (MW). The
126 the SIZE register and the memory window index should be programmed
149 Address and Size to be used while configuring the memory window.
152 MEMORY WINDOW1 OFFSET:
154 Memory Window 1 and Doorbell registers are packed together in the
156 registers and the latter portion of the region is for memory window 1.
157 This register will specify the offset of the memory window 1.
159 NO OF MEMORY WINDOW:
161 Specifies the number of memory windows supported by the NTB device.
178 in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
179 ring doorbell (MSI-X support will be added later). MSI uses same
180 address for all the interrupts and MSI-X can provide different
181 addresses for different interrupts. The MSI/MSI-X address is provided
182 by the host and the address it gives is based on the MSI/MSI-X
184 using GIC ITS will have the same MSI-X address for all the interrupts.
186 for both MSI and MSI-X, EPF NTB allocates a separate region in the
188 be mapped to the MSI/MSI-X address provided by the host. If a host
197 This holds the MSI/MSI-X data that has to be written to MSI address
202 ---------------------
204 Each host has its own register space allocated in the memory of NTB endpoint
205 controller. They are both readable and writable from both sides of the bridge.
214 -------------------
218 Memory Window:
219 --------------
222 memory window.
228 scratchpad, doorbell, one or more memory windows) to be modeled to achieve
229 NTB functionality. At least one memory window is required while more than
233 If one 32-bit BAR is allocated for each of these regions, the scheme would
243 BAR4 Memory Window 1
244 BAR5 Memory Window 2
248 be enough BARs for all the regions in a platform that supports only 64-bit
263 BAR2 Doorbell + Memory Window 1
264 BAR3 Memory Window 2
265 BAR4 Memory Window 3
266 BAR5 Memory Window 4
272 ----------------------------------
274 .. code-block:: text
276 +-----------------+------->+------------------+ +-----------------+
278 +-----------------+----+ +------------------+<-------+-----------------+
280 +-----------------+ +-->+------------------+<-------+-----------------+
281 | BAR2 | Local Memory | BAR2 |
282 +-----------------+ +-----------------+
284 +-----------------+ +-----------------+
286 +-----------------+ +-----------------+
288 +-----------------+ +-----------------+
289 EP CONTROLLER 1 EP CONTROLLER 2
292 EP controller 1) allocated in local memory. The HOST1 can access the config
293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
294 The peer host (HOST2 connected to EP controller 2) can also access this
295 scratchpad region (peer scratchpad) using BAR1 of EP controller 2. This
299 Modeling Doorbell/Memory Window 1:
300 ----------------------------------
302 .. code-block:: text
304 +-----------------+ +----->+----------------+-----------+-----------------+
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
306 +-----------------+ | +----------------+ +-----------------+
307 | BAR1 | | | Doorbell 2 +---------+ | |
308 +-----------------+----+ +----------------+ | | |
309 | BAR2 | | Doorbell 3 +-------+ | +-----------------+
310 +-----------------+----+ +----------------+ | +-> MSI-X ADDRESS 2 |
311 | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
312 +-----------------+ | |----------------+ | | | |
313 | BAR4 | | | | | | +-----------------+
314 +-----------------+ | | MW1 +---+ | +-->+ MSI-X ADDRESS 3||
315 | BAR5 | | | | | | +-----------------+
316 +-----------------+ +----->-----------------+ | | | |
317 EP CONTROLLER 1 | | | | +-----------------+
318 | | | +---->+ MSI-X ADDRESS 4 |
319 +----------------+ | +-----------------+
320 EP CONTROLLER 2 | | |
322 +-------> MW1 |
325 +-----------------+
331 +-----------------+
335 Above diagram shows how the doorbell and memory window 1 is mapped so that
337 buffers exposed by HOST2 using memory window1 (MW1). Here doorbell and
338 memory window 1 regions are allocated in EP controller 2 outbound (OB) address
339 space. Allocating and configuring BARs for doorbell and memory window1
341 Mapping from EP controller 2 OB space to PCI address space is done when HOST2
344 Modeling Optional Memory Windows:
345 ---------------------------------
347 This is modeled the same was as MW1 but each of the additional memory windows