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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dmicrochip,sam9x75-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAM9X75 LVDS Controller
10 - Dharma Balasubiramani <dharma.b@microchip.com>
13 The Low Voltage Differential Signaling Controller (LVDSC) manages data
14 format conversion from the LCD Controller internal DPI bus to OpenLDI
15 LVDS output signals. LVDSC functions include bit mapping, balanced mode
20 const: microchip,sam9x75-lvds
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H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
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H A Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16 used in LVDS mode, to remap the pixel color codings between those modules.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
25 const: fsl,imx8qxp-pxl2dpi
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
16 The CSR module, as a system controller, contains the LDB's configuration
23 LDB split mode to support a dual link LVDS display. The channel indexes
41 - fsl,imx8qm-ldb
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H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 asynchronous linkage between pixel sources(display controller or
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Timings Controller (TCON)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The TCON acts as a timing controller for RGB, LVDS and TV
18 "#clock-cells":
23 - const: allwinner,sun4i-a10-tcon
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H A Dst,stm32mp25-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 LVDS Display Interface Transmitter
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
16 onto the LVDS PHY.
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H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
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H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson Display Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson Display controller is composed of several components
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
10 - Liu Ying <victor.liu@nxp.com>
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
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/linux/drivers/gpu/drm/stm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Enable support for the on-chip display controller on
17 will be called stm-drm.
27 tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver"
30 Enable support for LVDS encoders on STMicroelectronics SoC.
31 The STM LVDS is a bridge which serialize pixel stream onto
32 a LVDS protocol.
35 called lvds.
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-ringneck-haikou-lvds-9904379.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard.
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
21 brightness-levels = <0 255>;
22 default-brightness-level = <255>;
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
52 if ((rdev->family == CHIP_R420) || in radeon_lookup_i2c_gpio_quirks()
53 (rdev->family == CHIP_R423) || in radeon_lookup_i2c_gpio_quirks()
54 (rdev->family == CHIP_RV410)) { in radeon_lookup_i2c_gpio_quirks()
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || in radeon_lookup_i2c_gpio_quirks()
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || in radeon_lookup_i2c_gpio_quirks()
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { in radeon_lookup_i2c_gpio_quirks()
58 gpio->ucClkMaskShift = 0x19; in radeon_lookup_i2c_gpio_quirks()
59 gpio->ucDataMaskShift = 0x18; in radeon_lookup_i2c_gpio_quirks()
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H A Dradeon_combios.c3 * Copyright 2007-8 Advanced Micro Devices, Inc.
133 struct radeon_device *rdev = dev->dev_private; in combios_get_table_offset()
137 if (!rdev->bios) in combios_get_table_offset()
362 size = RBIOS8(rdev->bios_header_start + 0x6); in combios_get_table_offset()
365 offset = RBIOS16(rdev->bios_header_start + check_offset); in combios_get_table_offset()
379 raw = rdev->bios + edid_info; in radeon_combios_check_hardcoded_edid()
388 rdev->mode_info.bios_hardcoded_edid = edid; in radeon_combios_check_hardcoded_edid()
396 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid)); in radeon_bios_get_hardcoded_edid()
447 if (rdev->family == CHIP_RS300 || in combios_setup_i2c_bus()
448 rdev->family == CHIP_RS400 || in combios_setup_i2c_bus()
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/linux/Documentation/devicetree/bindings/clock/
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments LMK04832 Clock Controller
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
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/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
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/linux/arch/arm/boot/dts/microchip/
H A Dat91-nattis-2-natte-2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
9 /dts-v1/;
10 #include "at91-linea.dtsi"
11 #include "at91-natte.dtsi"
14 model = "Axentia Linea-Nattis v2 Natte v2";
15 compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
18 gpio-keys {
19 compatible = "gpio-keys";
21 key-wakeup {
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp-tx6qp-8137.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lvds.dtsi"
12 model = "Ka-Ro electronics TX6QP-8137 Module";
13 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_usdhc4>;
35 bus-width = <4>;
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3528-ioc-grf
19 - rockchip,rk3528-vo-grf
20 - rockchip,rk3528-vpu-grf
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/linux/include/linux/
H A Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
133 #define VDE_I_LVDSSI 0x08000000 /* LVDS sense interrupt */
136 #define VDE_I_LVDSSIEN 0x40000000 /* LVDS Sense enable */
149 * DMA Controller registers.
162 #define VDMA_DQWCR0 0xe2c /* Count (16-byte) */
177 * Indexed port operations. Note that these are all multi-op
182 #define VIAStatus 0x3DA /* Non-indexed port */
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dactions,s700-pinctrl.txt1 Actions Semi S700 Pin Controller
3 This binding describes the pin controller found in the S700 SoC.
7 - compatible: Should be "actions,s700-pinctrl"
8 - reg: Should contain the register base address and size of
9 the pin controller.
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
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H A Dactions,s500-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi S500 SoC pinmux & GPIO controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
14 Pinmux & GPIO controller manages pin multiplexing & configuration including
16 pinctrl-bindings.txt in this directory for common binding part and usage.
20 const: actions,s500-pinctrl
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/linux/drivers/video/fbdev/via/
H A Dviamode.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
35 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
84 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
123 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
159 {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
190 {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
195 {VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
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