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/linux/arch/arm/mach-socfpga/
H A Dl2_cache.c1 // SPDX-License-Identifier: GPL-2.0-only
11 /* A10 System Manager L2 ECC Control register */
19 /* A10 System Manager L2 ECC IRQ Clear register */
28 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc"); in socfpga_init_l2_ecc()
30 pr_err("Unable to find socfpga-l2-ecc in dtb\n"); in socfpga_init_l2_ecc()
37 pr_err("Unable to find L2 ECC mapping in dtb\n"); in socfpga_init_l2_ecc()
41 /* Enable ECC */ in socfpga_init_l2_ecc()
51 /* Find the L2 EDAC device tree node */ in socfpga_init_arria10_l2_ecc()
52 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc"); in socfpga_init_arria10_l2_ecc()
54 pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n"); in socfpga_init_arria10_l2_ecc()
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/linux/Documentation/devicetree/bindings/arm/calxeda/
H A Dl2ecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs-l2-ecc
26 - description: single bit error interrupt
27 - description: double bit error interrupt
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/linux/drivers/edac/
H A DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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H A Daltera_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
12 #include <linux/firmware/intel/stratix10-smc.h>
17 #include <linux/mfd/altera-sysmgr.h>
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
85 const struct altr_sdram_prv_data *priv = drvdata->data; in altr_sdram_mc_err_handler()
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); in altr_sdram_mc_err_handler()
90 if (status & priv->ecc_stat_ue_mask) { in altr_sdram_mc_err_handler()
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H A Daltera_edac.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
69 /* SDRAM Controller ECC Error Address Register */
72 /*-----------------------------------------*/
139 /* SDRAM Controller ECC Error Address Register */
143 /* SDRAM Controller ECC Diagnostic Register */
198 /* OCRAM ECC Management Group Defines */
207 /* L2 ECC Management Group Defines */
214 /* Arria10 General ECC Block Module Defines */
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H A Dedac_device.h10 * http://www.anime.net/~goemon/linux-ecc/
15 * Refactored for multi-source files:
18 * Please look at Documentation/driver-api/edac.rst for more info about
40 * CPU caches (L1 and L2)
45 * other EDAC/ECC type devices that can be monitored for
50 * cache could be composed of L1, L2 and L3 levels of cache.
52 * L2 and maybe L3 caches.
58 * cpu/cpu0/.. <L1 and L2 block directory>
59 * /L1-cache/ce_count
61 * /L2-cache/ce_count
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H A Dhighbank_l2_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
28 struct hb_l2_drvdata *drvdata = dci->pvt_info; in highbank_l2_err_handler()
30 if (irq == drvdata->sb_irq) { in highbank_l2_err_handler()
31 writel(1, drvdata->base + SR_CLR_SB_ECC_INTR); in highbank_l2_err_handler()
32 edac_device_handle_ce(dci, 0, 0, dci->ctl_name); in highbank_l2_err_handler()
34 if (irq == drvdata->db_irq) { in highbank_l2_err_handler()
35 writel(1, drvdata->base + SR_CLR_DB_ECC_INTR); in highbank_l2_err_handler()
36 edac_device_handle_ue(dci, 0, 0, dci->ctl_name); in highbank_l2_err_handler()
43 { .compatible = "calxeda,hb-sregs-l2-ecc", },
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H A Dmpc85xx_edac.c8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
52 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
55 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
59 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
67 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
71 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
78 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
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/linux/arch/sparc/include/asm/
H A Dchafsr.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * ch --> cheetah
10 * ch+ --> cheetah plus
11 * jp --> jalapeno
15 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
33 /* Hardware corrected E-cache Tag ECC error */
38 /* SW handled correctable E-cache Tag ECC error */
43 /* Uncorrectable E-cache Tag ECC error */
48 /* Uncorrectable system bus data ECC error due to prefetch
64 * This bit is not set when multiple ECC errors happen within a single
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/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
21 typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
64 bits with ECC), the data flows to the CPU using a 128 bits parallel
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/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
36 &L2 {
37 arm,parity-enable;
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H A Darmada-xp-crs328-4c-20s-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS328-4C-20S-4S+ board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS328-4C-20S-4S+";
25 compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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H A Darmada-xp-crs305-1g-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS305-1G-4S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS305-1G-4S+";
25 compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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H A Darmada-xp-crs326-24g-2s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS326-24G-2S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS326-24G-2S+";
25 compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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/linux/lib/
H A Dbch.c15 * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
24 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
30 * Call bch_encode to compute and store ecc parity bytes to a given buffer.
50 * b. Error locator polynomial computation using Berlekamp-Massey algorithm
56 * (BTA) down to a certain degree (4), after which ad hoc low-degree polynomial
63 * - WEWoRC 2009, Graz, Austria, LNCS, Springer, July 2009, to appear.
81 #define GF_N(_p) ((1 << (CONFIG_BCH_CONST_M))-1)
85 #define GF_M(_p) ((_p)->m)
86 #define GF_T(_p) ((_p)->t)
87 #define GF_N(_p) ((_p)->n)
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/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
22 stdout-path = "serial0:115200n8";
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux/arch/mips/mm/
H A Dcex-sb1.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 * Based on SiByte sample software cache-err/cerr.S
31 * the L1 and L2) since it is fetched as 0xa0000100.
35 * (0x170-0x17f) are used to preserve k0, k1, and ra.
44 * CPU-specific location without ruining a register in the
57 * if we can fast-path out of here for a h/w-recovered error.
65 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
93 * External icache errors are due to uncorrectable ECC errors
94 * in the L2 cache or Memory Controller and cannot be
105 * CacheErr-I is valid and we can just invalidate all blocks
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
7 /dts-v1/;
9 #include "qcom-sdx55.dtsi"
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 compatible = "qcom,sdx55-mtp", "qcom,sdx55";
17 qcom,board-id = <0x5010008 0x0>;
24 stdout-path = "serial0:115200n8";
27 reserved-memory {
28 #address-cells = <1>;
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H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x0>;
23 stdout-path = "serial0:921600n8";
26 reserved-memory {
27 #address-cells = <1>;
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H A Dqcom-sdx55-t55.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-t55", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x4>;
23 stdout-path = "serial0:115200n8";
26 reserved-memory {
27 #address-cells = <1>;
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dmarked.json35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…
45 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This imp…
80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
140 … Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction…
155 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
215 …efDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2"
230 …Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is …
240 …data cache was reloaded either shared or modified data from another core's L2/L3 on a different ch…
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