1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg #ifndef _SPARC64_CHAFSR_H 3a439fe51SSam Ravnborg #define _SPARC64_CHAFSR_H 4a439fe51SSam Ravnborg 5a439fe51SSam Ravnborg /* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ 6a439fe51SSam Ravnborg 7a439fe51SSam Ravnborg /* Comments indicate which processor variants on which the bit definition 8a439fe51SSam Ravnborg * is valid. Codes are: 9a439fe51SSam Ravnborg * ch --> cheetah 10a439fe51SSam Ravnborg * ch+ --> cheetah plus 11a439fe51SSam Ravnborg * jp --> jalapeno 12a439fe51SSam Ravnborg */ 13a439fe51SSam Ravnborg 14a439fe51SSam Ravnborg /* All bits of this register except M_SYNDROME and E_SYNDROME are 15a439fe51SSam Ravnborg * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. 16a439fe51SSam Ravnborg */ 17a439fe51SSam Ravnborg 18a439fe51SSam Ravnborg /* Software bit set by linux trap handlers to indicate that the trap was 19a439fe51SSam Ravnborg * signalled at %tl >= 1. 20a439fe51SSam Ravnborg */ 21a439fe51SSam Ravnborg #define CHAFSR_TL1 (1UL << 63UL) /* n/a */ 22a439fe51SSam Ravnborg 23a439fe51SSam Ravnborg /* Unmapped error from system bus for prefetch queue or 24a439fe51SSam Ravnborg * store queue read operation 25a439fe51SSam Ravnborg */ 26a439fe51SSam Ravnborg #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */ 27a439fe51SSam Ravnborg 28a439fe51SSam Ravnborg /* Bus error from system bus for prefetch queue or store queue 29a439fe51SSam Ravnborg * read operation 30a439fe51SSam Ravnborg */ 31a439fe51SSam Ravnborg #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */ 32a439fe51SSam Ravnborg 33a439fe51SSam Ravnborg /* Hardware corrected E-cache Tag ECC error */ 34a439fe51SSam Ravnborg #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */ 35a439fe51SSam Ravnborg /* System interface protocol error, hw timeout caused */ 36a439fe51SSam Ravnborg #define JPAFSR_JETO (1UL << 57UL) /* jp */ 37a439fe51SSam Ravnborg 38a439fe51SSam Ravnborg /* SW handled correctable E-cache Tag ECC error */ 39a439fe51SSam Ravnborg #define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */ 40a439fe51SSam Ravnborg /* Parity error on system snoop results */ 41a439fe51SSam Ravnborg #define JPAFSR_SCE (1UL << 56UL) /* jp */ 42a439fe51SSam Ravnborg 43a439fe51SSam Ravnborg /* Uncorrectable E-cache Tag ECC error */ 44a439fe51SSam Ravnborg #define CHPAFSR_TUE (1UL << 55UL) /* ch+ */ 45a439fe51SSam Ravnborg /* System interface protocol error, illegal command detected */ 46a439fe51SSam Ravnborg #define JPAFSR_JEIC (1UL << 55UL) /* jp */ 47a439fe51SSam Ravnborg 48a439fe51SSam Ravnborg /* Uncorrectable system bus data ECC error due to prefetch 49a439fe51SSam Ravnborg * or store fill request 50a439fe51SSam Ravnborg */ 51a439fe51SSam Ravnborg #define CHPAFSR_DUE (1UL << 54UL) /* ch+ */ 52a439fe51SSam Ravnborg /* System interface protocol error, illegal ADTYPE detected */ 53a439fe51SSam Ravnborg #define JPAFSR_JEIT (1UL << 54UL) /* jp */ 54a439fe51SSam Ravnborg 55a439fe51SSam Ravnborg /* Multiple errors of the same type have occurred. This bit is set when 56a439fe51SSam Ravnborg * an uncorrectable error or a SW correctable error occurs and the status 57a439fe51SSam Ravnborg * bit to report that error is already set. When multiple errors of 58a439fe51SSam Ravnborg * different types are indicated by setting multiple status bits. 59a439fe51SSam Ravnborg * 60a439fe51SSam Ravnborg * This bit is not set if multiple HW corrected errors with the same 61a439fe51SSam Ravnborg * status bit occur, only uncorrectable and SW correctable ones have 62a439fe51SSam Ravnborg * this behavior. 63a439fe51SSam Ravnborg * 64a439fe51SSam Ravnborg * This bit is not set when multiple ECC errors happen within a single 65a439fe51SSam Ravnborg * 64-byte system bus transaction. Only the first ECC error in a 16-byte 66a439fe51SSam Ravnborg * subunit will be logged. All errors in subsequent 16-byte subunits 67a439fe51SSam Ravnborg * from the same 64-byte transaction are ignored. 68a439fe51SSam Ravnborg */ 69a439fe51SSam Ravnborg #define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */ 70a439fe51SSam Ravnborg 71a439fe51SSam Ravnborg /* Privileged state error has occurred. This is a capture of PSTATE.PRIV 72a439fe51SSam Ravnborg * at the time the error is detected. 73a439fe51SSam Ravnborg */ 74a439fe51SSam Ravnborg #define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */ 75a439fe51SSam Ravnborg 76a439fe51SSam Ravnborg /* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error 77a439fe51SSam Ravnborg * bits and record the most recently detected errors. Bits accumulate 78a439fe51SSam Ravnborg * errors that have been detected since the last write to clear the bit. 79a439fe51SSam Ravnborg */ 80a439fe51SSam Ravnborg 81a439fe51SSam Ravnborg /* System interface protocol error. The processor asserts its' ERROR 82a439fe51SSam Ravnborg * pin when this event occurs and it also logs a specific cause code 83a439fe51SSam Ravnborg * into a JTAG scannable flop. 84a439fe51SSam Ravnborg */ 85a439fe51SSam Ravnborg #define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */ 86a439fe51SSam Ravnborg 87a439fe51SSam Ravnborg /* Internal processor error. The processor asserts its' ERROR 88a439fe51SSam Ravnborg * pin when this event occurs and it also logs a specific cause code 89a439fe51SSam Ravnborg * into a JTAG scannable flop. 90a439fe51SSam Ravnborg */ 91a439fe51SSam Ravnborg #define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */ 92a439fe51SSam Ravnborg 93a439fe51SSam Ravnborg /* System request parity error on incoming address */ 94a439fe51SSam Ravnborg #define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */ 95a439fe51SSam Ravnborg 96a439fe51SSam Ravnborg /* HW Corrected system bus MTAG ECC error */ 97a439fe51SSam Ravnborg #define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */ 98a439fe51SSam Ravnborg /* Parity error on L2 cache tag SRAM */ 99a439fe51SSam Ravnborg #define JPAFSR_ETP (1UL << 48UL) /* jp */ 100a439fe51SSam Ravnborg 101a439fe51SSam Ravnborg /* Uncorrectable system bus MTAG ECC error */ 102a439fe51SSam Ravnborg #define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */ 103a439fe51SSam Ravnborg /* Out of range memory error has occurred */ 104a439fe51SSam Ravnborg #define JPAFSR_OM (1UL << 47UL) /* jp */ 105a439fe51SSam Ravnborg 106a439fe51SSam Ravnborg /* HW Corrected system bus data ECC error for read of interrupt vector */ 107a439fe51SSam Ravnborg #define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */ 108a439fe51SSam Ravnborg /* Error due to unsupported store */ 109a439fe51SSam Ravnborg #define JPAFSR_UMS (1UL << 46UL) /* jp */ 110a439fe51SSam Ravnborg 111a439fe51SSam Ravnborg /* Uncorrectable system bus data ECC error for read of interrupt vector */ 112a439fe51SSam Ravnborg #define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */ 113a439fe51SSam Ravnborg 114a439fe51SSam Ravnborg /* Unmapped error from system bus */ 115a439fe51SSam Ravnborg #define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */ 116a439fe51SSam Ravnborg 117a439fe51SSam Ravnborg /* Bus error response from system bus */ 118a439fe51SSam Ravnborg #define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */ 119a439fe51SSam Ravnborg 120a439fe51SSam Ravnborg /* SW Correctable E-cache ECC error for instruction fetch or data access 121a439fe51SSam Ravnborg * other than block load. 122a439fe51SSam Ravnborg */ 123a439fe51SSam Ravnborg #define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */ 124a439fe51SSam Ravnborg 125a439fe51SSam Ravnborg /* Uncorrectable E-cache ECC error for instruction fetch or data access 126a439fe51SSam Ravnborg * other than block load. 127a439fe51SSam Ravnborg */ 128a439fe51SSam Ravnborg #define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */ 129a439fe51SSam Ravnborg 130a439fe51SSam Ravnborg /* Copyout HW Corrected ECC error */ 131a439fe51SSam Ravnborg #define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */ 132a439fe51SSam Ravnborg 133a439fe51SSam Ravnborg /* Copyout Uncorrectable ECC error */ 134a439fe51SSam Ravnborg #define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */ 135a439fe51SSam Ravnborg 136a439fe51SSam Ravnborg /* HW Corrected ECC error from E-cache for writeback */ 137a439fe51SSam Ravnborg #define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */ 138a439fe51SSam Ravnborg 139a439fe51SSam Ravnborg /* Uncorrectable ECC error from E-cache for writeback */ 140a439fe51SSam Ravnborg #define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */ 141a439fe51SSam Ravnborg 142a439fe51SSam Ravnborg /* HW Corrected ECC error from E-cache for store merge or block load */ 143a439fe51SSam Ravnborg #define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */ 144a439fe51SSam Ravnborg 145a439fe51SSam Ravnborg /* Uncorrectable ECC error from E-cache for store merge or block load */ 146a439fe51SSam Ravnborg #define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */ 147a439fe51SSam Ravnborg 148a439fe51SSam Ravnborg /* Uncorrectable system bus data ECC error for read of memory or I/O */ 149a439fe51SSam Ravnborg #define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */ 150a439fe51SSam Ravnborg 151a439fe51SSam Ravnborg /* HW Corrected system bus data ECC error for read of memory or I/O */ 152a439fe51SSam Ravnborg #define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */ 153a439fe51SSam Ravnborg 154a439fe51SSam Ravnborg /* Uncorrectable ECC error from remote cache/memory */ 155a439fe51SSam Ravnborg #define JPAFSR_RUE (1UL << 32UL) /* jp */ 156a439fe51SSam Ravnborg 157a439fe51SSam Ravnborg /* Correctable ECC error from remote cache/memory */ 158a439fe51SSam Ravnborg #define JPAFSR_RCE (1UL << 31UL) /* jp */ 159a439fe51SSam Ravnborg 160a439fe51SSam Ravnborg /* JBUS parity error on returned read data */ 161a439fe51SSam Ravnborg #define JPAFSR_BP (1UL << 30UL) /* jp */ 162a439fe51SSam Ravnborg 163a439fe51SSam Ravnborg /* JBUS parity error on data for writeback or block store */ 164a439fe51SSam Ravnborg #define JPAFSR_WBP (1UL << 29UL) /* jp */ 165a439fe51SSam Ravnborg 166a439fe51SSam Ravnborg /* Foreign read to DRAM incurring correctable ECC error */ 167a439fe51SSam Ravnborg #define JPAFSR_FRC (1UL << 28UL) /* jp */ 168a439fe51SSam Ravnborg 169a439fe51SSam Ravnborg /* Foreign read to DRAM incurring uncorrectable ECC error */ 170a439fe51SSam Ravnborg #define JPAFSR_FRU (1UL << 27UL) /* jp */ 171a439fe51SSam Ravnborg 172a439fe51SSam Ravnborg #define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 173a439fe51SSam Ravnborg CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 174a439fe51SSam Ravnborg CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 175a439fe51SSam Ravnborg CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 176a439fe51SSam Ravnborg CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 177a439fe51SSam Ravnborg #define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \ 178a439fe51SSam Ravnborg CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \ 179a439fe51SSam Ravnborg CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 180a439fe51SSam Ravnborg CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 181a439fe51SSam Ravnborg CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 182a439fe51SSam Ravnborg CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 183a439fe51SSam Ravnborg CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 184a439fe51SSam Ravnborg #define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \ 185a439fe51SSam Ravnborg JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \ 186a439fe51SSam Ravnborg CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \ 187a439fe51SSam Ravnborg JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \ 188a439fe51SSam Ravnborg CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \ 189a439fe51SSam Ravnborg CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \ 190a439fe51SSam Ravnborg CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \ 191a439fe51SSam Ravnborg CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \ 192a439fe51SSam Ravnborg JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \ 193a439fe51SSam Ravnborg JPAFSR_FRC | JPAFSR_FRU) 194a439fe51SSam Ravnborg 195a439fe51SSam Ravnborg /* Active JBUS request signal when error occurred */ 196a439fe51SSam Ravnborg #define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */ 197a439fe51SSam Ravnborg #define JPAFSR_JBREQ_SHIFT 24UL 198a439fe51SSam Ravnborg 199a439fe51SSam Ravnborg /* L2 cache way information */ 200a439fe51SSam Ravnborg #define JPAFSR_ETW (0x3UL << 22UL) /* jp */ 201a439fe51SSam Ravnborg #define JPAFSR_ETW_SHIFT 22UL 202a439fe51SSam Ravnborg 203a439fe51SSam Ravnborg /* System bus MTAG ECC syndrome. This field captures the status of the 204a439fe51SSam Ravnborg * first occurrence of the highest-priority error according to the M_SYND 205a439fe51SSam Ravnborg * overwrite policy. After the AFSR sticky bit, corresponding to the error 206a439fe51SSam Ravnborg * for which the M_SYND is reported, is cleared, the contents of the M_SYND 207a439fe51SSam Ravnborg * field will be unchanged by will be unfrozen for further error capture. 208a439fe51SSam Ravnborg */ 209a439fe51SSam Ravnborg #define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */ 210a439fe51SSam Ravnborg #define CHAFSR_M_SYNDROME_SHIFT 16UL 211a439fe51SSam Ravnborg 212a439fe51SSam Ravnborg /* Agenid Id of the foreign device causing the UE/CE errors */ 213a439fe51SSam Ravnborg #define JPAFSR_AID (0x1fUL << 9UL) /* jp */ 214a439fe51SSam Ravnborg #define JPAFSR_AID_SHIFT 9UL 215a439fe51SSam Ravnborg 216a439fe51SSam Ravnborg /* System bus or E-cache data ECC syndrome. This field captures the status 217a439fe51SSam Ravnborg * of the first occurrence of the highest-priority error according to the 218a439fe51SSam Ravnborg * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the 219a439fe51SSam Ravnborg * error for which the E_SYND is reported, is cleare, the contents of the E_SYND 220a439fe51SSam Ravnborg * field will be unchanged but will be unfrozen for further error capture. 221a439fe51SSam Ravnborg */ 222a439fe51SSam Ravnborg #define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */ 223a439fe51SSam Ravnborg #define CHAFSR_E_SYNDROME_SHIFT 0UL 224a439fe51SSam Ravnborg 225a439fe51SSam Ravnborg /* The AFSR must be explicitly cleared by software, it is not cleared automatically 226a439fe51SSam Ravnborg * by a read. Writes to bits <51:33> with bits set will clear the corresponding 227a439fe51SSam Ravnborg * bits in the AFSR. Bits associated with disrupting traps must be cleared before 228a439fe51SSam Ravnborg * interrupts are re-enabled to prevent multiple traps for the same error. I.e. 229a439fe51SSam Ravnborg * PSTATE.IE and AFSR bits control delivery of disrupting traps. 230a439fe51SSam Ravnborg * 231a439fe51SSam Ravnborg * Since there is only one AFAR, when multiple events have been logged by the 232a439fe51SSam Ravnborg * bits in the AFSR, at most one of these events will have its status captured 233a439fe51SSam Ravnborg * in the AFAR. The highest priority of those event bits will get AFAR logging. 234a439fe51SSam Ravnborg * The AFAR will be unlocked and available to capture the address of another event 235a439fe51SSam Ravnborg * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is 236a439fe51SSam Ravnborg * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites 237a439fe51SSam Ravnborg * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked 238a439fe51SSam Ravnborg * and ready for another event, even though AFSR.CE is still set. The same rules 239a439fe51SSam Ravnborg * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. 240a439fe51SSam Ravnborg */ 241a439fe51SSam Ravnborg 242a439fe51SSam Ravnborg #endif /* _SPARC64_CHAFSR_H */ 243