| /freebsd/sys/contrib/device-tree/src/arm/mediatek/ |
| H A D | mt6592.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&sysirq>;
89 sysirq: interrupt-controller@10200220 {
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 interrupt-parent = <&gic>;
97 gic: interrupt-controller@10211000 {
99 interrupt-controller;
100 #interrupt-cells = <3>;
[all …]
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| H A D | mt8127.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&sysirq>;
83 interrupt-parent = <&gic>;
111 sysirq: interrupt-controller@10200100 {
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 interrupt-parent = <&gic>;
120 gic: interrupt-controller@10211000 {
122 interrupt-controller;
[all …]
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | mpc8540ads.dts | 68 interrupt-parent = <&mpic>;
74 interrupt-parent = <&mpic>;
83 interrupt-parent = <&mpic>;
94 interrupt-parent = <&mpic>;
110 interrupt-parent = <&mpic>;
118 interrupt-parent = <&mpic>;
126 interrupt-parent = <&mpic>;
134 interrupt-parent = <&mpic>;
150 interrupt-parent = <&mpic>;
161 interrupt-parent = <&mpic>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/synaptics/ |
| H A D | berlin2.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 interrupt-parent = <&gic>;
121 gic: interrupt-controller@ad1000 {
124 interrupt-controller;
125 #interrupt-cells = <3>;
182 interrupt-parent = <&aic>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-sprd.txt | 5 interrupt is shared for all of the banks handled by the controller.
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Should be <2>. Specifies the number of cells needed
16 to encode interrupt source.
17 - interrupts: Should be the port interrupt shared by all the gpios.
25 interrupt-controller;
26 #interrupt-cells = <2>;
|
| H A D | sgpio-aspeed.txt | 7 - Support interrupt option for each input port and various interrupt
21 - interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
22 - interrupt-controller : Mark the GPIO controller as an interrupt-controller
29 The sgpio and interrupt properties are further described in their respective
33 - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
43 interrupt-controller;
|
| H A D | brcm,brcmstb-gpio.yaml | 12 interrupt is shared for all of the banks handled by the controller.
49 The interrupt shared by all GPIO lines for this controller.
51 "#interrupt-cells":
63 interrupt-controller: true
85 #interrupt-cells = <2>;
88 interrupt-controller;
90 interrupt-parent = <&irq0_intc>;
98 #interrupt-cells = <2>;
101 interrupt-controller;
103 interrupt-parent = <&irq0_aon_intc>;
|
| H A D | nvidia,tegra186-gpio.txt | 48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
56 interrupt signals generated by a set-of-ports. The intent is for each generated
90 Array of interrupt specifiers.
91 The interrupt outputs from the HW block, one per set of ports, in the
112 - interrupt-controller
114 Marks the device node as an interrupt controller/provider.
115 - #interrupt-cells
118 Indicates how many cells are used in a consumer's interrupt specifier.
132 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
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| H A D | abilis,tb10x-gpio.txt | 13 - interrupt-controller: Marks the device node as an interrupt controller.
14 - #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
15 - interrupts: Defines the interrupt line connecting this GPIO controller to
16 its parent interrupt controller.
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 interrupt-parent = <&tb10x_ictl>;
|
| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hi6220.dtsi | 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
231 gic: interrupt-controller@f6801000 {
238 #interrupt-cells = <3>;
239 interrupt-controller;
245 interrupt-parent = <&gic>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynosautov9-pinctrl.dtsi | 17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 interrupt-parent = <&gic>;
54 interrupt-controller;
55 #interrupt-cells = <2>;
76 interrupt-controller;
77 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie_w_reg.h | 374 * [0x0] Interrupt Cause Register
377 * cleared after MSI-X message associated with this specific interrupt
380 * associated bit in the Interrupt Cause Set register
385 * to set a bit in the Interrupt Cause register, the specific bit is set
386 * to ensure the interrupt indication is not lost.
391 * [0x8] Interrupt Cause Set Register
393 * enabling software to generate a hardware interrupt. Write 0 has no
399 * [0x10] Interrupt Mask Register
401 * message associatd with the associated interrupt bit is sent (AXI
407 * [0x18] Interrupt Mask Clear Register
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | wm831x.txt | 23 - interrupts : The interrupt line the IRQ signal for the device is
26 - interrupt-controller : wm831x devices contain interrupt controllers and
27 may provide interrupt services to other devices.
28 - #interrupt-cells: Must be 2. The first cell is the IRQ number, and the
30 ../interrupt-controller/interrupts.txt
64 interrupt-parent = <&gic>;
66 interrupt-controller;
67 #interrupt-cells = <2>;
|
| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | cpcap-battery.yaml | 28 - description: eol interrupt
29 - description: low battery percentage interrupt
30 - description: critical battery percentage interrupt
31 - description: charger detect interrupt
32 - description: battery detect interrupt
33 - description: coulomb counter calibration interrupt
35 interrupt-names:
63 - interrupt-names
78 interrupt-names =
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | warp.dts | 50 UIC0: interrupt-controller0 {
52 interrupt-controller;
57 #interrupt-cells = <2>;
60 UIC1: interrupt-controller1 {
62 interrupt-controller;
67 #interrupt-cells = <2>;
69 interrupt-parent = <&UIC0>;
104 interrupt-parent = <&MAL0>;
106 #interrupt-cells = <1>;
109 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
[all …]
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| /freebsd/sys/dts/arm/ |
| H A D | db78460.dts | 73 interrupt-controller;
75 #interrupt-cells = <1>;
89 interrupt-parent = <&MPIC>;
99 interrupt-parent = <&MPIC>;
108 interrupt-parent = <&MPIC>;
118 interrupt-parent = <&MPIC>;
128 interrupt-parent = <&MPIC>;
138 interrupt-parent = <&MPIC>;
148 interrupt-parent = <&MPIC>;
231 interrupt-parent = <&MPIC>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | arm,mhuv3.yaml | 59 region, wherein the MHU Doorbell is used strictly as an interrupt generation
79 region, wherein the MHU FastChannel is used as an interrupt generation
114 interrupt-names:
140 description: PBX/MBX Combined interrupt
142 description: PBX/MBX FIFO Combined interrupt
144 description: PBX/MBX FIFO Channel <N> Low Tide interrupt
146 description: PBX/MBX FIFO Channel <N> High Tide interrupt
148 description: PBX/MBX FIFO Channel <N> Flush interrupt
150 description: MBX Doorbell Channel <N> Transfer interrupt
152 description: MBX FastChannel <N> Transfer interrupt
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/iio/accel/ |
| H A D | bosch,bma255.yaml | 49 Without interrupt-names, the first interrupt listed must be the one
50 connected to the INT1 pin, the second (optional) interrupt listed must be
54 BMC156 does not have an INT1 pin, therefore the first interrupt pin is
57 interrupt-names:
82 #include <dt-bindings/interrupt-controller/irq.h>
92 interrupt-names = "INT1";
96 #include <dt-bindings/interrupt-controller/irq.h>
106 interrupt-names = "INT2";
110 # include <dt-bindings/interrupt-controller/irq.h>
|
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | rockchip-dw-pcie-common.yaml | 45 Combined system interrupt, which is used to signal the following
50 Combined PM interrupt, which is used to signal the following
55 Combined message interrupt, which is used to signal the following
59 Combined legacy interrupt, which is used to signal the following
63 Combined error interrupt, which is used to signal the following
68 eDMA write channel 0 interrupt
70 eDMA write channel 1 interrupt
72 eDMA read channel 0 interrupt
74 eDMA read channel 1 interrupt
76 interrupt-names:
|
| H A D | nvidia,tegra194-pcie.yaml | 52 - description: controller interrupt
53 - description: MSI interrupt
55 interrupt-names:
239 - interrupt-names
240 - interrupt-map
241 - interrupt-map-mask
256 #include <dt-bindings/interrupt-controller/arm-gic.h>
290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
291 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
292 interrupt-names = "intr", "msi";
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/renesas/ |
| H A D | r9a08g045.dtsi | 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 interrupt-parent = <&gic>;
66 interrupt-names = "eri", "rxi", "txi",
86 interrupt-names = "tei", "ri", "ti", "spi", "sti",
108 interrupt-names = "tei", "ri", "ti", "spi", "sti",
130 interrupt-names = "tei", "ri", "ti", "spi", "sti",
152 interrupt-names = "tei", "ri", "ti", "spi", "sti",
180 interrupt-names = "lpm_int", "ca55stbydone_int",
190 interrupt-controller;
191 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_enet.h | 104 /**< 10GEC MDIO scan event interrupt */
106 /**< 10GEC MDIO command completion interrupt */
108 /**< 10GEC, mEMAC Remote fault interrupt */
110 /**< 10GEC, mEMAC Local fault interrupt */
112 /**< 10GEC, mEMAC Transmit frame ECC error interrupt */
114 /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */
116 /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */
118 /**< 10GEC Transmit frame error interrupt */
120 /**< 10GEC, mEMAC Receive FIFO overflow interrupt */
122 /**< 10GEC, mEMAC Receive frame ECC error interrupt */
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | emev2.dtsi | 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
45 gic: interrupt-controller@e0020000 {
47 interrupt-controller;
48 #interrupt-cells = <3>;
57 interrupt-affinity = <&cpu0>, <&cpu1>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
225 interrupt-controller;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mips/cavium/ |
| H A D | cib.txt | 1 * Cavium Interrupt Bus widget
8 - interrupt-controller: This is an interrupt controller.
18 - #interrupt-cells: Must be <2>. The first cell is the bit within the
24 interrupt-controller@107000000e000 {
30 interrupt-controller;
31 interrupt-parent = <&ciu>;
40 #interrupt-cells = <2>;
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/gyroscope/ |
| H A D | nxp,fxas21002c.yaml | 36 description: Either interrupt may be triggered on rising or falling edges.
38 interrupt-names:
48 description: the interrupt/data ready line will be configured as open drain,
49 which is useful if several sensors share the same interrupt
66 #include <dt-bindings/interrupt-controller/irq.h>
79 interrupt-parent = <&gpio1>;
81 interrupt-names = "INT1";
94 interrupt-parent = <&gpio2>;
96 interrupt-names = "INT2";
|