1*c66ec88fSEmmanuel VadotSpreadtrum GPIO controller bindings 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe controller's registers are organized as sets of sixteen 16-bit 4*c66ec88fSEmmanuel Vadotregisters with each set controlling a bank of up to 16 pins. A single 5*c66ec88fSEmmanuel Vadotinterrupt is shared for all of the banks handled by the controller. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties: 8*c66ec88fSEmmanuel Vadot- compatible: Should be "sprd,sc9860-gpio". 9*c66ec88fSEmmanuel Vadot- reg: Define the base and range of the I/O address space containing 10*c66ec88fSEmmanuel Vadotthe GPIO controller registers. 11*c66ec88fSEmmanuel Vadot- gpio-controller: Marks the device node as a GPIO controller. 12*c66ec88fSEmmanuel Vadot- #gpio-cells: Should be <2>. The first cell is the gpio number and 13*c66ec88fSEmmanuel Vadotthe second cell is used to specify optional parameters. 14*c66ec88fSEmmanuel Vadot- interrupt-controller: Marks the device node as an interrupt controller. 15*c66ec88fSEmmanuel Vadot- #interrupt-cells: Should be <2>. Specifies the number of cells needed 16*c66ec88fSEmmanuel Vadotto encode interrupt source. 17*c66ec88fSEmmanuel Vadot- interrupts: Should be the port interrupt shared by all the gpios. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotExample: 20*c66ec88fSEmmanuel Vadot ap_gpio: gpio@40280000 { 21*c66ec88fSEmmanuel Vadot compatible = "sprd,sc9860-gpio"; 22*c66ec88fSEmmanuel Vadot reg = <0 0x40280000 0 0x1000>; 23*c66ec88fSEmmanuel Vadot gpio-controller; 24*c66ec88fSEmmanuel Vadot #gpio-cells = <2>; 25*c66ec88fSEmmanuel Vadot interrupt-controller; 26*c66ec88fSEmmanuel Vadot #interrupt-cells = <2>; 27*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 28*c66ec88fSEmmanuel Vadot }; 29