1*852ba100SJustin Hibbits /* 2*852ba100SJustin Hibbits * Copyright 2008-2012 Freescale Semiconductor Inc. 3*852ba100SJustin Hibbits * 4*852ba100SJustin Hibbits * Redistribution and use in source and binary forms, with or without 5*852ba100SJustin Hibbits * modification, are permitted provided that the following conditions are met: 6*852ba100SJustin Hibbits * * Redistributions of source code must retain the above copyright 7*852ba100SJustin Hibbits * notice, this list of conditions and the following disclaimer. 8*852ba100SJustin Hibbits * * Redistributions in binary form must reproduce the above copyright 9*852ba100SJustin Hibbits * notice, this list of conditions and the following disclaimer in the 10*852ba100SJustin Hibbits * documentation and/or other materials provided with the distribution. 11*852ba100SJustin Hibbits * * Neither the name of Freescale Semiconductor nor the 12*852ba100SJustin Hibbits * names of its contributors may be used to endorse or promote products 13*852ba100SJustin Hibbits * derived from this software without specific prior written permission. 14*852ba100SJustin Hibbits * 15*852ba100SJustin Hibbits * 16*852ba100SJustin Hibbits * ALTERNATIVELY, this software may be distributed under the terms of the 17*852ba100SJustin Hibbits * GNU General Public License ("GPL") as published by the Free Software 18*852ba100SJustin Hibbits * Foundation, either version 2 of that License or (at your option) any 19*852ba100SJustin Hibbits * later version. 20*852ba100SJustin Hibbits * 21*852ba100SJustin Hibbits * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22*852ba100SJustin Hibbits * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23*852ba100SJustin Hibbits * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24*852ba100SJustin Hibbits * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25*852ba100SJustin Hibbits * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26*852ba100SJustin Hibbits * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27*852ba100SJustin Hibbits * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28*852ba100SJustin Hibbits * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29*852ba100SJustin Hibbits * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30*852ba100SJustin Hibbits * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31*852ba100SJustin Hibbits */ 32*852ba100SJustin Hibbits 33*852ba100SJustin Hibbits #ifndef __FSL_ENET_H 34*852ba100SJustin Hibbits #define __FSL_ENET_H 35*852ba100SJustin Hibbits 36*852ba100SJustin Hibbits /** 37*852ba100SJustin Hibbits @Description Ethernet MAC-PHY Interface 38*852ba100SJustin Hibbits */ 39*852ba100SJustin Hibbits 40*852ba100SJustin Hibbits enum enet_interface { 41*852ba100SJustin Hibbits E_ENET_IF_MII = 0x00010000, /**< MII interface */ 42*852ba100SJustin Hibbits E_ENET_IF_RMII = 0x00020000, /**< RMII interface */ 43*852ba100SJustin Hibbits E_ENET_IF_SMII = 0x00030000, /**< SMII interface */ 44*852ba100SJustin Hibbits E_ENET_IF_GMII = 0x00040000, /**< GMII interface */ 45*852ba100SJustin Hibbits E_ENET_IF_RGMII = 0x00050000, /**< RGMII interface */ 46*852ba100SJustin Hibbits E_ENET_IF_TBI = 0x00060000, /**< TBI interface */ 47*852ba100SJustin Hibbits E_ENET_IF_RTBI = 0x00070000, /**< RTBI interface */ 48*852ba100SJustin Hibbits E_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */ 49*852ba100SJustin Hibbits E_ENET_IF_XGMII = 0x00090000, /**< XGMII interface */ 50*852ba100SJustin Hibbits E_ENET_IF_QSGMII = 0x000a0000, /**< QSGMII interface */ 51*852ba100SJustin Hibbits E_ENET_IF_XFI = 0x000b0000 /**< XFI interface */ 52*852ba100SJustin Hibbits }; 53*852ba100SJustin Hibbits 54*852ba100SJustin Hibbits /** 55*852ba100SJustin Hibbits @Description Ethernet Speed (nominal data rate) 56*852ba100SJustin Hibbits */ 57*852ba100SJustin Hibbits enum enet_speed { 58*852ba100SJustin Hibbits E_ENET_SPEED_10 = 10, /**< 10 Mbps */ 59*852ba100SJustin Hibbits E_ENET_SPEED_100 = 100, /**< 100 Mbps */ 60*852ba100SJustin Hibbits E_ENET_SPEED_1000 = 1000, /**< 1000 Mbps = 1 Gbps */ 61*852ba100SJustin Hibbits E_ENET_SPEED_2500 = 2500, /**< 2500 Mbps = 2.5 Gbps */ 62*852ba100SJustin Hibbits E_ENET_SPEED_10000 = 10000 /**< 10000 Mbps = 10 Gbps */ 63*852ba100SJustin Hibbits }; 64*852ba100SJustin Hibbits 65*852ba100SJustin Hibbits enum mac_type { 66*852ba100SJustin Hibbits E_MAC_DTSEC, 67*852ba100SJustin Hibbits E_MAC_TGEC, 68*852ba100SJustin Hibbits E_MAC_MEMAC 69*852ba100SJustin Hibbits }; 70*852ba100SJustin Hibbits 71*852ba100SJustin Hibbits /**************************************************************************//** 72*852ba100SJustin Hibbits @Description Enum for inter-module interrupts registration 73*852ba100SJustin Hibbits *//***************************************************************************/ 74*852ba100SJustin Hibbits enum fman_event_modules { 75*852ba100SJustin Hibbits E_FMAN_MOD_PRS, /**< Parser event */ 76*852ba100SJustin Hibbits E_FMAN_MOD_KG, /**< Keygen event */ 77*852ba100SJustin Hibbits E_FMAN_MOD_PLCR, /**< Policer event */ 78*852ba100SJustin Hibbits E_FMAN_MOD_10G_MAC, /**< 10G MAC event */ 79*852ba100SJustin Hibbits E_FMAN_MOD_1G_MAC, /**< 1G MAC event */ 80*852ba100SJustin Hibbits E_FMAN_MOD_TMR, /**< Timer event */ 81*852ba100SJustin Hibbits E_FMAN_MOD_FMAN_CTRL, /**< FMAN Controller Timer event */ 82*852ba100SJustin Hibbits E_FMAN_MOD_MACSEC, 83*852ba100SJustin Hibbits E_FMAN_MOD_DUMMY_LAST 84*852ba100SJustin Hibbits }; 85*852ba100SJustin Hibbits 86*852ba100SJustin Hibbits /**************************************************************************//** 87*852ba100SJustin Hibbits @Description Enum for interrupts types 88*852ba100SJustin Hibbits *//***************************************************************************/ 89*852ba100SJustin Hibbits enum fman_intr_type { 90*852ba100SJustin Hibbits E_FMAN_INTR_TYPE_ERR, 91*852ba100SJustin Hibbits E_FMAN_INTR_TYPE_NORMAL 92*852ba100SJustin Hibbits }; 93*852ba100SJustin Hibbits 94*852ba100SJustin Hibbits /**************************************************************************//** 95*852ba100SJustin Hibbits @Description enum for defining MAC types 96*852ba100SJustin Hibbits *//***************************************************************************/ 97*852ba100SJustin Hibbits enum fman_mac_type { 98*852ba100SJustin Hibbits E_FMAN_MAC_10G = 0, /**< 10G MAC */ 99*852ba100SJustin Hibbits E_FMAN_MAC_1G /**< 1G MAC */ 100*852ba100SJustin Hibbits }; 101*852ba100SJustin Hibbits 102*852ba100SJustin Hibbits enum fman_mac_exceptions { 103*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0, 104*852ba100SJustin Hibbits /**< 10GEC MDIO scan event interrupt */ 105*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_MDIO_CMD_CMPL, 106*852ba100SJustin Hibbits /**< 10GEC MDIO command completion interrupt */ 107*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_REM_FAULT, 108*852ba100SJustin Hibbits /**< 10GEC, mEMAC Remote fault interrupt */ 109*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_LOC_FAULT, 110*852ba100SJustin Hibbits /**< 10GEC, mEMAC Local fault interrupt */ 111*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_1TX_ECC_ER, 112*852ba100SJustin Hibbits /**< 10GEC, mEMAC Transmit frame ECC error interrupt */ 113*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_TX_FIFO_UNFL, 114*852ba100SJustin Hibbits /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */ 115*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_TX_FIFO_OVFL, 116*852ba100SJustin Hibbits /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */ 117*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_TX_ER, 118*852ba100SJustin Hibbits /**< 10GEC Transmit frame error interrupt */ 119*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_FIFO_OVFL, 120*852ba100SJustin Hibbits /**< 10GEC, mEMAC Receive FIFO overflow interrupt */ 121*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_ECC_ER, 122*852ba100SJustin Hibbits /**< 10GEC, mEMAC Receive frame ECC error interrupt */ 123*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_JAB_FRM, 124*852ba100SJustin Hibbits /**< 10GEC Receive jabber frame interrupt */ 125*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_OVRSZ_FRM, 126*852ba100SJustin Hibbits /**< 10GEC Receive oversized frame interrupt */ 127*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_RUNT_FRM, 128*852ba100SJustin Hibbits /**< 10GEC Receive runt frame interrupt */ 129*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_FRAG_FRM, 130*852ba100SJustin Hibbits /**< 10GEC Receive fragment frame interrupt */ 131*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_LEN_ER, 132*852ba100SJustin Hibbits /**< 10GEC Receive payload length error interrupt */ 133*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_CRC_ER, 134*852ba100SJustin Hibbits /**< 10GEC Receive CRC error interrupt */ 135*852ba100SJustin Hibbits E_FMAN_MAC_EX_10G_RX_ALIGN_ER, 136*852ba100SJustin Hibbits /**< 10GEC Receive alignment error interrupt */ 137*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_BAB_RX, 138*852ba100SJustin Hibbits /**< dTSEC Babbling receive error */ 139*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_RX_CTL, 140*852ba100SJustin Hibbits /**< dTSEC Receive control (pause frame) interrupt */ 141*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET, 142*852ba100SJustin Hibbits /**< dTSEC Graceful transmit stop complete */ 143*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_BAB_TX, 144*852ba100SJustin Hibbits /**< dTSEC Babbling transmit error */ 145*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_TX_CTL, 146*852ba100SJustin Hibbits /**< dTSEC Transmit control (pause frame) interrupt */ 147*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_TX_ERR, 148*852ba100SJustin Hibbits /**< dTSEC Transmit error */ 149*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_LATE_COL, 150*852ba100SJustin Hibbits /**< dTSEC Late collision */ 151*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_COL_RET_LMT, 152*852ba100SJustin Hibbits /**< dTSEC Collision retry limit */ 153*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_TX_FIFO_UNDRN, 154*852ba100SJustin Hibbits /**< dTSEC Transmit FIFO underrun */ 155*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_MAG_PCKT, 156*852ba100SJustin Hibbits /**< dTSEC Magic Packet detection */ 157*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_MII_MNG_RD_COMPLET, 158*852ba100SJustin Hibbits /**< dTSEC MII management read completion */ 159*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_MII_MNG_WR_COMPLET, 160*852ba100SJustin Hibbits /**< dTSEC MII management write completion */ 161*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET, 162*852ba100SJustin Hibbits /**< dTSEC Graceful receive stop complete */ 163*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_TX_DATA_ERR, 164*852ba100SJustin Hibbits /**< dTSEC Internal data error on transmit */ 165*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_RX_DATA_ERR, 166*852ba100SJustin Hibbits /**< dTSEC Internal data error on receive */ 167*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_1588_TS_RX_ERR, 168*852ba100SJustin Hibbits /**< dTSEC Time-Stamp Receive Error */ 169*852ba100SJustin Hibbits E_FMAN_MAC_EX_1G_RX_MIB_CNT_OVFL, 170*852ba100SJustin Hibbits /**< dTSEC MIB counter overflow */ 171*852ba100SJustin Hibbits E_FMAN_MAC_EX_TS_FIFO_ECC_ERR, 172*852ba100SJustin Hibbits /**< mEMAC Time-stamp FIFO ECC error interrupt; 173*852ba100SJustin Hibbits not supported on T4240/B4860 rev1 chips */ 174*852ba100SJustin Hibbits }; 175*852ba100SJustin Hibbits 176*852ba100SJustin Hibbits #define ENET_IF_SGMII_BASEX 0x80000000 177*852ba100SJustin Hibbits /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC 178*852ba100SJustin Hibbits and phy or backplane; 179*852ba100SJustin Hibbits Note: 1000BaseX auto-negotiation relates only to interface between MAC 180*852ba100SJustin Hibbits and phy/backplane, SGMII phy can still synchronize with far-end phy at 181*852ba100SJustin Hibbits 10Mbps, 100Mbps or 1000Mbps */ 182*852ba100SJustin Hibbits 183*852ba100SJustin Hibbits enum enet_mode { 184*852ba100SJustin Hibbits E_ENET_MODE_INVALID = 0, 185*852ba100SJustin Hibbits /**< Invalid Ethernet mode */ 186*852ba100SJustin Hibbits E_ENET_MODE_MII_10 = (E_ENET_IF_MII | E_ENET_SPEED_10), 187*852ba100SJustin Hibbits /**< 10 Mbps MII */ 188*852ba100SJustin Hibbits E_ENET_MODE_MII_100 = (E_ENET_IF_MII | E_ENET_SPEED_100), 189*852ba100SJustin Hibbits /**< 100 Mbps MII */ 190*852ba100SJustin Hibbits E_ENET_MODE_RMII_10 = (E_ENET_IF_RMII | E_ENET_SPEED_10), 191*852ba100SJustin Hibbits /**< 10 Mbps RMII */ 192*852ba100SJustin Hibbits E_ENET_MODE_RMII_100 = (E_ENET_IF_RMII | E_ENET_SPEED_100), 193*852ba100SJustin Hibbits /**< 100 Mbps RMII */ 194*852ba100SJustin Hibbits E_ENET_MODE_SMII_10 = (E_ENET_IF_SMII | E_ENET_SPEED_10), 195*852ba100SJustin Hibbits /**< 10 Mbps SMII */ 196*852ba100SJustin Hibbits E_ENET_MODE_SMII_100 = (E_ENET_IF_SMII | E_ENET_SPEED_100), 197*852ba100SJustin Hibbits /**< 100 Mbps SMII */ 198*852ba100SJustin Hibbits E_ENET_MODE_GMII_1000 = (E_ENET_IF_GMII | E_ENET_SPEED_1000), 199*852ba100SJustin Hibbits /**< 1000 Mbps GMII */ 200*852ba100SJustin Hibbits E_ENET_MODE_RGMII_10 = (E_ENET_IF_RGMII | E_ENET_SPEED_10), 201*852ba100SJustin Hibbits /**< 10 Mbps RGMII */ 202*852ba100SJustin Hibbits E_ENET_MODE_RGMII_100 = (E_ENET_IF_RGMII | E_ENET_SPEED_100), 203*852ba100SJustin Hibbits /**< 100 Mbps RGMII */ 204*852ba100SJustin Hibbits E_ENET_MODE_RGMII_1000 = (E_ENET_IF_RGMII | E_ENET_SPEED_1000), 205*852ba100SJustin Hibbits /**< 1000 Mbps RGMII */ 206*852ba100SJustin Hibbits E_ENET_MODE_TBI_1000 = (E_ENET_IF_TBI | E_ENET_SPEED_1000), 207*852ba100SJustin Hibbits /**< 1000 Mbps TBI */ 208*852ba100SJustin Hibbits E_ENET_MODE_RTBI_1000 = (E_ENET_IF_RTBI | E_ENET_SPEED_1000), 209*852ba100SJustin Hibbits /**< 1000 Mbps RTBI */ 210*852ba100SJustin Hibbits E_ENET_MODE_SGMII_10 = (E_ENET_IF_SGMII | E_ENET_SPEED_10), 211*852ba100SJustin Hibbits /**< 10 Mbps SGMII with auto-negotiation between MAC and 212*852ba100SJustin Hibbits SGMII phy according to Cisco SGMII specification */ 213*852ba100SJustin Hibbits E_ENET_MODE_SGMII_100 = (E_ENET_IF_SGMII | E_ENET_SPEED_100), 214*852ba100SJustin Hibbits /**< 100 Mbps SGMII with auto-negotiation between MAC and 215*852ba100SJustin Hibbits SGMII phy according to Cisco SGMII specification */ 216*852ba100SJustin Hibbits E_ENET_MODE_SGMII_1000 = (E_ENET_IF_SGMII | E_ENET_SPEED_1000), 217*852ba100SJustin Hibbits /**< 1000 Mbps SGMII with auto-negotiation between MAC and 218*852ba100SJustin Hibbits SGMII phy according to Cisco SGMII specification */ 219*852ba100SJustin Hibbits E_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 220*852ba100SJustin Hibbits | E_ENET_SPEED_10), 221*852ba100SJustin Hibbits /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between 222*852ba100SJustin Hibbits MAC and SGMII phy or backplane */ 223*852ba100SJustin Hibbits E_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 224*852ba100SJustin Hibbits | E_ENET_SPEED_100), 225*852ba100SJustin Hibbits /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between 226*852ba100SJustin Hibbits MAC and SGMII phy or backplane */ 227*852ba100SJustin Hibbits E_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 228*852ba100SJustin Hibbits | E_ENET_SPEED_1000), 229*852ba100SJustin Hibbits /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between 230*852ba100SJustin Hibbits MAC and SGMII phy or backplane */ 231*852ba100SJustin Hibbits E_ENET_MODE_QSGMII_1000 = (E_ENET_IF_QSGMII | E_ENET_SPEED_1000), 232*852ba100SJustin Hibbits /**< 1000 Mbps QSGMII with auto-negotiation between MAC and 233*852ba100SJustin Hibbits QSGMII phy according to Cisco QSGMII specification */ 234*852ba100SJustin Hibbits E_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_QSGMII 235*852ba100SJustin Hibbits | E_ENET_SPEED_1000), 236*852ba100SJustin Hibbits /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between 237*852ba100SJustin Hibbits MAC and QSGMII phy or backplane */ 238*852ba100SJustin Hibbits E_ENET_MODE_XGMII_10000 = (E_ENET_IF_XGMII | E_ENET_SPEED_10000), 239*852ba100SJustin Hibbits /**< 10000 Mbps XGMII */ 240*852ba100SJustin Hibbits E_ENET_MODE_XFI_10000 = (E_ENET_IF_XFI | E_ENET_SPEED_10000) 241*852ba100SJustin Hibbits /**< 10000 Mbps XFI */ 242*852ba100SJustin Hibbits }; 243*852ba100SJustin Hibbits 244*852ba100SJustin Hibbits enum fmam_mac_statistics_level { 245*852ba100SJustin Hibbits E_FMAN_MAC_NONE_STATISTICS, /**< No statistics */ 246*852ba100SJustin Hibbits E_FMAN_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; 247*852ba100SJustin Hibbits Optimized for performance */ 248*852ba100SJustin Hibbits E_FMAN_MAC_FULL_STATISTICS /**< All counters available; Not 249*852ba100SJustin Hibbits optimized for performance */ 250*852ba100SJustin Hibbits }; 251*852ba100SJustin Hibbits 252*852ba100SJustin Hibbits #define _MAKE_ENET_MODE(_interface, _speed) (enum enet_mode)((_interface) \ 253*852ba100SJustin Hibbits | (_speed)) 254*852ba100SJustin Hibbits 255*852ba100SJustin Hibbits #define _ENET_INTERFACE_FROM_MODE(mode) (enum enet_interface) \ 256*852ba100SJustin Hibbits ((mode) & 0x0FFF0000) 257*852ba100SJustin Hibbits #define _ENET_SPEED_FROM_MODE(mode) (enum enet_speed)((mode) & 0x0000FFFF) 258*852ba100SJustin Hibbits #define _ENET_ADDR_TO_UINT64(_enet_addr) \ 259*852ba100SJustin Hibbits (uint64_t)(((uint64_t)(_enet_addr)[0] << 40) | \ 260*852ba100SJustin Hibbits ((uint64_t)(_enet_addr)[1] << 32) | \ 261*852ba100SJustin Hibbits ((uint64_t)(_enet_addr)[2] << 24) | \ 262*852ba100SJustin Hibbits ((uint64_t)(_enet_addr)[3] << 16) | \ 263*852ba100SJustin Hibbits ((uint64_t)(_enet_addr)[4] << 8) | \ 264*852ba100SJustin Hibbits ((uint64_t)(_enet_addr)[5])) 265*852ba100SJustin Hibbits 266*852ba100SJustin Hibbits #define _MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \ 267*852ba100SJustin Hibbits do { \ 268*852ba100SJustin Hibbits int i; \ 269*852ba100SJustin Hibbits for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \ 270*852ba100SJustin Hibbits (_enet_addr)[i] = (uint8_t)((_addr64) >> ((5-i)*8));\ 271*852ba100SJustin Hibbits } while (0) 272*852ba100SJustin Hibbits 273*852ba100SJustin Hibbits #endif /* __FSL_ENET_H */ 274