Lines Matching full:interrupt
374 * [0x0] Interrupt Cause Register
377 * cleared after MSI-X message associated with this specific interrupt
380 * associated bit in the Interrupt Cause Set register
385 * to set a bit in the Interrupt Cause register, the specific bit is set
386 * to ensure the interrupt indication is not lost.
391 * [0x8] Interrupt Cause Set Register
393 * enabling software to generate a hardware interrupt. Write 0 has no
399 * [0x10] Interrupt Mask Register
401 * message associatd with the associated interrupt bit is sent (AXI
407 * [0x18] Interrupt Mask Clear Register
417 * [0x20] Interrupt Status Register
418 * This register latches the status of the interrupt source.
422 /* [0x28] Interrupt Control Register */
426 * [0x30] Interrupt Mask Register
437 * [0x38] Interrupt Log Register
670 /* mask the interrupt to the soc in case correctable error occur in the ARI. */
683 /* Transmit INT_A Interrupt ControlEvery transition from 0 to 1 ... */
685 /* A request to generate an outbound MSI interrupt when MSI is e ... */
715 * logged information will only be valid when the interrupt is cleared .
907 * Transmit INT_A Interrupt Control
908 * Every transition from 0 to 1 schedules an Assert_ INT interrupt message for
910 * Every transition from 1 to 0, schedules a Deassert_INT interrupt message for
911 * transmit. Which interrupt, the PCIe only use INTA message.
915 * A request to generate an outbound MSI interrupt when MSI is enabled. Change
1059 * MSI Controller Interrupt
1060 * MSI interrupt is being received. Write zero to clear this bit
1113 * - PME Interrupt Enable bit in the Root Control register is set to 1.
1122 * - PME Interrupt Enable bit in the Root Control register is set to 1.
1182 * interrupt only for EP mode.
1201 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
1206 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
1207 * the posedge of the interrupt source, i.e., when interrupt source =1 and
1208 * Interrupt Status = 0.
1209 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1210 * interrupt source =1.
1214 * When Moderation_Reset =1, all Moderation timers associated with the interrupt
1215 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1281 * register bit 15) is updated and the Link Autonomous Bandwidth Interrupt
1319 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
1324 * When Set_on_Posedge =1, the bits in the interrupt Cause register are set on
1325 * the posedge of the interrupt source, i.e., when Interrupt Source =1 and
1326 * Interrupt Status = 0.
1327 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1328 * Interrupt Source =1.
1332 * When Moderation_Reset =1, all Moderation timers associated with the interrupt
1333 * cause bits are cleared to 0, enabling an immediate interrupt assertion if any
1362 /* VPD interrupt, ot read/write frpm EEPROM */
1403 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
1408 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
1409 * the posedge of the interrupt source, i.e., when interrupt source =1 and
1410 * Interrupt Status = 0.
1411 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1412 * interrupt source =1.
1416 * When Moderation_Reset =1, all Moderation timers associated with the interrupt
1417 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1456 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
1461 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
1462 * the posedge of the interrupt source, i.e., when interrupt source =1 and
1463 * Interrupt Status = 0.
1464 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
1465 * interrupt source =1.
1469 * When Moderation_Reset =1, all Moderation timers associated with the interrupt
1470 * cause bits are cleared to 0, enabling immediate interrupt assertion if any